JPH1091544A - Bus control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an information equipment using a general-purpose bus from becoming an operation impossible state by setting a response propriety register in a response denial state when a writing operation is not executed even once on a peculiar information register through the bus. SOLUTION: A protection circuit 1 is composed of a D-type flip flop 11 and a gate circuit 12. The D-type flip flop 11 is set so that Q output becomes a high level by a reset signal generated when power is supplied. When writing into the peculiar information register 7 is not executed even once before a response possible register 6 becomes a response possible state, a clock signal to the D-type flip flop 11 is not given. Thus, the Q output of the D-type flip flop 11 is set to be high as it is. Even if a signal (a) for setting the response propriety register 6 in the response possible state is outputted from an address command decoding part 9, the signal (a) is not inputted to the response propriety register 6 and the response propriety register 6 holds the response denial state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control circuit in each option card which is used for an information processing device such as a personal computer and controls a general-purpose bus to which an option card can be connected. The present invention relates to a bus control circuit capable of preventing an information processing device from operating in an inoperable state.

[0002]

2. Description of the Related Art The functions required of an information processing apparatus vary from user to user, but if an information processing apparatus capable of coping with all of the various functions requested by each user is provided, the cost of the information processing apparatus increases. Become. Therefore, the information processing device bus (system bus, common data line)
2. Description of the Related Art Conventionally, there has been provided a method in which a general-purpose bus to which various option cards can be connected, and a user connects an option card having a function suitable for his / her request to the general-purpose bus. FIG. 4 is a diagram showing a bus and a bus control circuit (bus interface circuit) of a conventional option card.
2), a unique information register 7 in which various information specific to the option card such as a memory address are set, and a card ID in which a card identification code for distinguishing a plurality of option cards is set. A register 8 includes an address command decoding unit 9 for analyzing an address command input via a bus. In the bus control circuit having such a configuration, when power is turned on, a system control unit (not shown) sets various information unique to the option card, such as a memory address to the unique information register 7 and an interrupt level, via the bus. The response enable / disable register 6 is set to a response enable state. That is, when the address specified by the system control unit matches the value of the card ID register 8, the address command decoding unit 9 sets the response availability register 6 to the response enabled state. When the function of the option card is used via the bus, it is determined whether or not the output of the response enable / disable register 6 is available. Then, subsequent use becomes possible.

[0003]

However, in the prior art as described above, if the response enable / disable register 6 is set to a response enable state without setting a memory address or the like in the unique information register 7, for example, However, in the worst case, there is a problem that the system becomes inoperable in the worst case, such as address duplication with the memory (I / O) area of the option card. An object of the present invention is to provide a bus control circuit that solves the above-described problems of the related art and can prevent an information device using a general-purpose bus to which an option card can be connected from falling into an inoperable state. is there.

[0004]

According to a first aspect of the present invention, there is provided a bus control circuit for controlling a general-purpose bus to which an option card can be connected. A response enable / disable register for outputting whether or not a response is possible, a unique information register in which various information specific to the option card are set, and a response when no write operation has been performed on the unique information register via the bus. A protection circuit for setting the enable / disable register to a response-impossible state. In the bus control circuit for controlling a general-purpose bus to which an option card can be connected, a response enable / disable register for outputting whether or not the option card can respond to the bus is provided. The internal operation of the option card in which the various information is set and the response enable / disable register is in a response enabled state when the write operation has never been performed on the unique information register via the bus. And a protection circuit for changing the state to an inoperable state. According to a third aspect of the present invention, in a bus control circuit for controlling a general-purpose bus to which an option card can be connected, a response enable / disable register for outputting whether or not the option card can respond to the bus; When the response information register is set to a response-enabled state without a write operation being performed on the unique information register via the bus, and the unique information register has a predetermined And an interrupt generation circuit for outputting an interrupt signal requesting the information setting to the bus.

[0005]

According to the first aspect of the present invention, if writing to the unique information register is never performed, the response permission / inhibition register is set to a response permission state from outside the option card. Can not. According to the second aspect of the present invention, if no writing is performed to the unique information register, the option card does not operate even if the response possibility register is in the response possible state. According to the third aspect of the present invention, if the response enable / disable register is set to the response enable state without any write operation being performed on the unique information register, an interrupt requesting predetermined information setting to the unique information register is made. The signal is output to the bus.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration block diagram of a bus control circuit showing a first embodiment of the present invention. As shown in the figure, the bus control circuit of this embodiment includes a response enable / disable register 6, a unique information register 7, a card ID register 8, an address command decoding unit 9, and further includes a protection circuit 1. Note that, in FIG.
An AD (read) signal, a dashed line indicates a WRITE (write) signal, and a solid line indicates other signals. The protection circuit 1
The D type flip-flop 11 includes a gate circuit 12, and the D type flip-flop 11 has a Q output of Hi according to a RESET signal generated when power is turned on.
gh level. When the power is turned on, an initialization unit of a system control unit (not shown) is started. Usually, the initialization unit first sets a memory address and the like in the unique information register 7. That is, the address command decoding unit 9 receives a command from the initialization unit and issues a WRITE signal for writing to the unique information register 7.

[0007] The WRITE signal is also input to the D-type flip-flop 11 as a clock signal.
Since the D input terminal of the type flip-flop 11 is connected to the ground, the Q output of the type flip-flop 11 changes to Low level according to the input of the clock signal. Therefore, upon receiving a command from the initialization means to set the response enable / disable register 6 to the response enable state, the address command decoding unit 9 causes the signal a (Low) for setting the response enable / disable register 6 to the response enable state.
When the signal a is output, the signal a passes through the gate 12 and is given to the response possibility register 6. That is, since the signal a which was conventionally directly supplied from the address command decoding unit 9 to the response permission / inhibition register 6 is supplied through the protection circuit 1 in this embodiment, the writing into the unique information register 7 is performed once beforehand. But if done, the signal a
Operates similarly to the conventional bus control circuit.

On the other hand, if the writing to the unique information register 7 is never performed before the responsive register 6 is set to the responsive state, that is, the unique information register 7
If no information such as a memory address is selected for the D-type flip-flop 11, the clock signal is not supplied to the D-type flip-flop 11, so that the Q output of the D-type flip-flop 11 is Hi.
gh level. Therefore, even if the signal a for setting the response enable / disable register 6 to the response enable state is output from the address / command decode unit 9, the signal a is not input to the response enable / disable register 6, and the response enable / disable register 6 is set in the response disable state. (When the power is turned on, the response permission / inhibition register 6 is automatically set to the response permission / inhibition state). According to this embodiment, even if for some reason the initialization means issues a command to set the response permission / inhibition register 6 to the response permission state without writing to the unique information register 7,
Since the response permission / inhibition register 6 holds the response / non-response state, the option card does not operate thereafter, so that the occurrence of a system inoperative state due to duplication of memory addresses and the like can be prevented.

FIG. 2 is a block diagram showing the configuration of a bus control circuit according to a second embodiment of the present invention. As shown in the figure, the bus control circuit of this embodiment also includes a response enable / disable register 6, a unique information register 7, a card ID register 8, an address command decoding unit 9, and a protection circuit 1. This is different from the first embodiment. That is, the signal "a" for setting the response enable / disable register 6 to the response enable state is directly input to the response enable / disable register 6 similarly to the conventional control circuit shown in FIG. Is output. This signal b is a command sent via a bus when trying to use a functional resource (hereinafter abbreviated as a resource) provided by this option card (an option card providing a memory area in the illustrated example). This is a signal output by the address command decoding unit 9 when received. The signal c is, for example, a memory chip selection signal for making the provided resource (memory area) operable. When the signal c is at the Low level, the provided resource becomes operable.

In this embodiment, when the address command decoding unit 9 outputs a signal a to the response permission / inhibition register 6 in response to a command from the initialization unit, the writing into the unique information register 7 is performed. Irrespective of the presence or absence of the response, the response enabled state is set in the response enabled / disabled register 6 as before. Therefore, thereafter, an instruction for using the resources of the option card is input to the address command decoding unit 9 from outside the option card via a bus. As described above, the signal b is output. If the writing to the unique information register 7 has never been performed before the output of the signal b, the Q output of the D-type flip-flop 11 becomes as described above. Since the signal remains at the high level, the signal c is not output from the gate 12. On the other hand, if the writing to the unique information register 7 is performed even once and information such as a memory address is set in the unique information register 7, the Q output becomes Low level, so that the signal c is output from the gate 12. Is done. Therefore, according to this embodiment, if a resource (for example, a memory area) of an option card is used without writing a memory address or the like to the unique information register 7, the resource becomes inoperable. In addition, the inoperable state of the system due to duplication of memory addresses does not occur. That is, the same object as in the first embodiment can be achieved by the second embodiment.

According to the first and second embodiments described above, it is possible to prevent the system from falling into an inoperable state or the like. However, since the unique information is not set in the unique information register 7, the desired information is not obtained. The problem remains that the option card cannot be used. The third embodiment of the present invention shown in FIG. 3 is to solve the above-mentioned problem that the option card cannot be used, and if the unique information is not set in the unique information register 7, the automatic operation is performed. A configuration is provided in which a desired option card can be used in such a manner as to be set in a desired manner. In other words, the provision of the interrupt generation circuit 2 as shown in FIG. 2 ensures that the unique information is set in the unique information register 7 and that the option card can be used. The interrupt generation circuit 2 has D-type flip-flops 11 and 13 and a gate 14.

In such a configuration, when the signal a for setting the response enable / disable register 6 to the response enable state is output from the address command decoding unit 9, the response enable / disable register 6 is set regardless of the setting of the unique information register 7. Is made ready for response, and the signal a is input to the gate 14 in the interrupt generation circuit 2. At this time, if the writing to the unique information register 7 has never been performed beforehand, the Q output of the flip-flop 11 remains at the High level, so that the signal d is output from the gate circuit 14, and 13 goes low (signal present). That is, the interrupt signal INTRQ is output to the bus. The above-mentioned interrupt is an interrupt for activating a program for setting unique information in the unique information register 7. Therefore, when this interrupt is received by the system control unit, the unique information register is transmitted via the address command decode unit 9. 7 is set.
On the other hand, if the writing to the unique information register 7 has been performed even once, the signal d is not output because the Q output of the flip-flop 11 is at the low level.
Therefore, no interrupt signal INTRQ is output.

[0013]

As described above, according to the present invention,
According to the first aspect of the present invention, if writing to the unique information register is never performed, the response enable / disable register cannot be set to the response enabled state. Therefore, the option card is used without writing to the unique information register. Therefore, it is possible to prevent the system from becoming inoperable due to duplication of memory addresses. According to the second aspect of the present invention, if the writing to the unique information register is never performed, the desired option card does not operate even if the response possible / impossible register is in the response enabled state. This prevents the option card from operating without performing the above operation, thereby preventing the system from becoming inoperable due to duplication of memory addresses. Claim 3
In the invention described above, if the response enable / disable register is set to the response enable state without performing a write operation to the unique information register even once, an interrupt signal requesting a predetermined information setting to the unique information register is sent to the bus. Is output to the unique information register.
Therefore, the situation in which the system becomes inoperable due to duplication of memory addresses or the like does not occur, and the option card can be used.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a bus control circuit showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a bus control circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration block diagram of a bus control circuit showing a third embodiment of the present invention.

FIG. 4 is a configuration block diagram of a bus control circuit showing an example of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Protection circuit, 2 ... Interrupt generation circuit, 6 ... Response availability register, 7 ... Unique information register, 8 ... Card identification code register, 9 ... Address command decoding part.

Claims (3)

[Claims] In a bus control circuit for controlling a general-purpose bus to which an option card can be connected, a response enable / disable register for outputting whether an option card can respond to the bus and various information specific to the option card are set. A unique information register, and a protection circuit for setting the response enable / disable register to a non-response state if a write operation has never been performed on the unique information register via a bus. circuit. 2. A bus control circuit for controlling a general-purpose bus to which an option card can be connected, wherein a response enable / disable register for outputting whether the option card can respond to the bus and various information unique to the option card are set. The internal operation state of the option card is set to an inoperable state even if the response enable / disable register is in a response enable state when no write operation has been performed on the unique information register and the unique information register via the bus. A bus control circuit, comprising: 3. A bus control circuit for controlling a general-purpose bus to which an option card can be connected, wherein a response enable / disable register for outputting whether the option card can respond to the bus and various information specific to the option card are set. Requesting a predetermined information setting in the unique information register when the response possible / impossible register is set to a response enabled state without performing a write operation to the unique information register via the bus. A bus control circuit, comprising: an interrupt generation circuit that outputs an interrupt signal to be transmitted to a bus.