JP2774110B2 - Inverter device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device that supplies high frequency power to a load circuit by alternately turning on and off two switching elements connected in series.

[Prior Art] FIG. 5 is a circuit diagram of a conventional inverter device, and FIG.
The figure is the operation waveform diagram. Connect a series circuit of switching elements Q ₁ and Q ₂ in parallel with the power
₂ , a load circuit Z is connected in parallel. The load circuit Z comprises a resonant circuit consisting of the choke L ₀ and capacitor C _0, the voltage developed across the capacitor C ₀ is applied to the load l.
OSC is an oscillation circuit that generates oscillation outputs V _A and V _B that alternately alternate between “High” level and “Low” level. Drive circuit A
Is a drive circuit of the switching elements Q _1, transistor
Tr ₅ including to Tr ₉ and the resistor R ₃ to R _5. Drive circuit B is a drive circuit of the switching element Q _2, the transistor Tr ₁₀ to Tr ₁₄
And a resistor R ₇ to R _9. The drive circuit A includes a transistor
Via a level shift circuit C including tr ₁ to Tr ₄ and the resistor R ₆ and the resistor R _10, the oscillation output V _A of the oscillator OSC is supplied. The driving circuit B, and through the resistor R ₁₁ is the oscillation output V _B of the oscillator OSC is supplied.

The level shift circuit C described above, was converted to a current signal input to the first current mirror circuit consisting of transistors Tr _1, Tr ₂ a voltage signal of the oscillation output V _A via a resistor R _10, the current signal through the second current mirror circuit consisting of transistors Tr _3, Tr ₄ and transmitted to the resistor R _6, and converts the voltage signals V _R by resistance R _6. Power for the upper circuit including a driving circuit A, the capacitor C ₁ is charged through the resistor R ₁
It is supplied by the power source of the lower circuit including a driving circuit B is supplied by the capacitor C ₂ is charged through the resistor R _2.
The change in the voltage V ₂ due to the switching of the switching elements Q ₁ and Q ₂ is applied between the collector and the emitter of the transistor Tr ₂ via the power supply capacitor C ₁ and the transistor Tr ₃ .
The current signal is stably transmitted by the constant current characteristic of the current mirror circuit.

6 at time t ₀ of Figure, the oscillation output V _A becomes "High" level, the base current is supplied through a resistor R ₁₀ to the transistor Tr _1, Tr _2, the current between the collector and emitter of the transistor Tr ₂ Flows. This current is applied to the transistor Tr ₃ ,
Flows to Tr _4, is transmitted to the collector of the transistor Tr _4,
The resistor R ₆ is converted into a voltage signal V _R, the voltage signal V _R is "Hi
gh "level. As a result, the transistors Tr ₅ and Tr ₆ are turned on, the transistors Tr ₇ and Tr ₉ are turned off, and the transistor T 5 is turned off.
r ₈ is turned on, the voltage V ₉ becomes a "High" level, the ON signal is supplied to the switching element Q _1. At this time,
Current I ₁ of the switching element Q ₁ is flowing in the negative direction. This capacitor C ₀ and the choke L ₀ is set higher oscillation frequency of the oscillation circuit OSC than the resonance frequency with the load circuit Z containing is because the current phase is delayed, in this case, switching At the time of switching of the elements Q ₁ and Q _2, the currents I ₁ and I _{2 first} flow from the negative direction, so that the switching loss of the switching elements Q ₁ and Q ₂ can be reduced.

When the time t ₁ in the oscillation output V _A becomes "Low" level, the collector current of the transistor Tr ₂ stops flowing, the voltage signal V _R
Also becomes "Low" level, the voltage V ₉ becomes "Low" level, the switching element Q ₁ is turned off. At this time, as tries to continue the current flowing in the choke L ₀ flows will flow a negative direction of the current to the switching element Q _2.
At the same time, the oscillation output V _B becomes a "High" level, the transistor Tr ₁₂ via the resistor R _11, Tr ₁₃ is turned on, the transistor Tr
₁₁ , Tr ₁₄ is turned off, transistor Tr ₁₀ is turned on,
Output voltage V ₁₁ becomes a "High" level, is supplied on signal to the switching element Q _2, current I ₂ flows.

Again the switching element Q ₂ is turned off at time t _2, the switching element Q ₁ is turned on, in this repetition, and supplies high-frequency power to the load circuit Z. The voltage V ₂ as shown in Figure No. 6 (h), when the current I ₁ is negative direction, because from the load circuit Z a regenerative current to the DC power source E, a little higher than the level V _E of current power supply E I do. Further, when the current I ₂ is negative, the voltage V ₂ due to the inductance component of the load circuit Z is a lower potential than the zero level.

[Problem to be Solved by the Invention] In the above-described conventional technology, the oscillation circuit OSC and the driving circuits A and B
In addition, when the level shift circuit C is integrated in a junction-separated semiconductor integrated circuit having a structure in which a withstand voltage is provided by a PN junction, there is a problem that a malfunction occurs in the inverter device. Hereinafter, this point will be described.

As shown in FIG. 7, on the P-type substrate 1,
An N-type epitaxial layer 2 is formed, and this is
Each element is formed on the separated N-type epitaxial layer 2. The feature is that the breakdown voltage is separated by a PN junction between the P-type substrate 1 and the N-type epitaxial layer 2, and the P-type substrate 1 is usually connected to a reference potential on a circuit. In the circuit of FIG. 5 is a negative electrode of the voltage V ₀ is the reference potential of the DC power source E. P-type substrate 1
Is at the lowest potential in terms of circuit operation, it can be separated from the N-type epitaxial layer 2 by the reverse characteristic of the PN junction, and each element is separated by the P-type diffusion layer 3 so that the driving circuits A and B
Circuits operating at different potentials can be configured on the same chip. An N ⁺ diffusion layer 4 is provided below the N-type epitaxial layer 2.

FIG. 7 illustrates the structure of an NPN transistor and a PNP transistor. The NPN transistor, with the N-type epitaxial layer 2 on the N ⁺ diffusion layer 7 is provided a collector region, provided with a base region formed of P-type diffusion layer 5, from the N ⁺ diffusion layer 6 in the P-type diffusion layer 5 In which an emitter region is provided. In the PNP transistor, an N ⁺ diffusion layer 8 is provided in the N type epitaxial layer 2 to serve as a base region, and a collector region formed of a P type diffusion layer 9 and an emitter region formed of a P type diffusion layer 10 are provided. is there.

When the circuit shown in FIG. 5 is configured in such a semiconductor integrated circuit, so-called parasitic diodes D _{1 to} D _{6 formed} between the drive circuit A and the transistors Tr ₃ and Tr ₄ and the reference potential V _0.
8 is shown in FIG. Further, in order to connect each element inside the semiconductor integrated circuit to form a circuit,
As shown in the drawing, an insulating layer 11 made of a silicon oxide film or the like is provided on the element, and wirings 12 to 15 made of an aluminum film or the like are formed thereon. The wirings 12 to 15 and the element are connected by a contact made of an aluminum film or the like. If the wirings 12 to 15 cannot be implemented in one plane, the wiring is implemented by performing two-layer wiring or the like. In this case, as shown in FIG. 9, it is general that the capacitance component Cx becomes large by shortening the distance between the wirings or arranging the wirings in parallel over a long distance.

When the circuit shown in FIG. 8 is operated in such a state, the operation waveform of each part is as shown in FIG. Time t ₀
In the oscillation output V _A becomes "High" level, the switching element Q ₁ in the same manner as the circuit of FIG. 5 is turned on, the voltage V ₂ becomes high level. When the current I ₁ flows and the oscillation output _VA goes to “Low” level at time t ₁ , the switching element Q ₁ turns off,
And tries to continue to flow a current flowing in the choke L _0, flows a negative direction of the current to the switching element Q _2. In this case, towards the driving circuit B from the drive circuit A becomes a high potential, so that the instantaneous voltage V ₂ drops. At this time, inside the drive circuit A, since the voltage V _R is "Low" level, the transistors Tr _5, Tr ₆ are turned off, the transistor Tr _7, Tr ₉ is turned on by the bias resistors R _4, R ₃ I have. Thus, the current is easily diverted by choke L ₀ through the parasitic diode D _2, D _5. Accordingly, when the shunt current from the diode D ₂ when you flow into, so that the voltage V ₇ rises. As shown in FIG. 9, voltage and wire 15 to be applied in the voltage V ₇ V _R
If the applied wire 14 and is near the because the capacitive component Cx large, if increasing the voltage V ₇ and the voltage V _9, a current flows through the resistor R ₆ via a capacitive component Cx, the voltage V _R It is easy to rise. In this state, at time t _12, the transistor Tr ₆ is turned on the voltage V _R rises, so the voltage V ₇ further increases, the transistor Tr ₈ is turned on, the voltage V
₉ becomes "High" level. Thus, since then on the switching element Q ₁ is, become a positive voltage is the voltage V ₂ with respect to the reference potential V _0, this time, already input signal V ₁₁ of the switching element Q ₂ is "High" level, Switching element Q ₁
Q ₂ is that ends up on at the same time as.

If a current path via such a parasitic diode exists inside the semiconductor integrated circuit, a voltage appears via somewhere in the wiring through the parasitic diode as noise, and it is difficult to eliminate this type of malfunction. Was.

The present invention has been made in view of such a point,
It is an object of the present invention to provide an inverter device that eliminates a malfunction of a circuit due to a parasitic diode and enables a stable operation.

[Means for Solving the Problems] In the present invention, in order to solve the above problems, as shown in FIG. 1, two main switching elements Q ₁ , a series circuit of a Q _2, at least one of parallel to the main switching element Q _2, at least the load circuit Z which includes an inductance component (choke L ₀₎ is connected, each of the main switching element Q _1, Q ₂ drive circuit
A and B are configured on a junction-separated type semiconductor integrated circuit that has a withstand voltage by PN junction, and each drive circuit A and B is an output switching element that supplies a drive current directly to the main switching elements Q ₁ and Q ₂ (Transistors Tr _{8 to} Tr ₁₁ ) and a former stage for supplying a control signal to the output switching element, and the driving circuit A on the high potential side when viewed from the P-type region in the PN junction is the two main circuits. The power is supplied from a second DC power supply (capacitor C ₁ ) having one end connected to a connection point between the switching elements Q ₁ and Q ₂ , and is connected between the output switching element and the second DC power supply in the high-potential side drive circuit A. it is characterized in that formed by inserting a resistor R ₁₂ between the front portion of the drive circuit a in the high-potential side and the connection point between the one end.

[Operation] The operation of the present invention will be described below with reference to the circuit of FIG.
Of the drive circuits A and B separated from the PN junction, the drive circuit A on the high potential side when viewed from the P-type region connected to the reference potential V ₀ has one end connected to the connection point of the main switching elements Q ₁ and Q _2. is powered by a capacitor connected C _1, the current flowing in the element of the first part of the drive circuit a, it flows to the connection point of the main switching element Q _1, Q _2. When the main switching element Q ₁ is turned off,
More than the potential V _{2 at} the connection point with the main switching elements Q ₁ and Q ₂ ,
The potential V _{0 in} the P-type region becomes higher, and a current tends to flow through the PN junction to the element at the preceding stage of the driving circuit A. However, since this current is suppressed by the resistor R ₁₂ , malfunction may occur. Is not invited.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. A series circuit of switching elements Q ₁ and Q ₂ is connected to both ends of the DC power supply E. The switching elements Q ₁ and Q ₂ are configured by transistors in which diodes are connected in anti-parallel, for example. Each switching element Q ₁ , Q ₂ is the output V ₉ , V
_{On /} off driving is performed by ₁₁ respectively. The one ends of the switching element Q _2, via a choke L _0, a parallel circuit of the load l and the capacitor C ₀ is connected. As the load 1, for example, a discharge lamp is used.

The series circuit of the resistor R ₁ and the capacitor C ₁ connected to both ends of the switching element Q ₁ is the power supply circuit of the upper circuit, and the series circuit of the resistor R ₂ and the capacitor C ₂ connected to both ends of the current power supply E is the lower circuit. This is the power supply circuit of the side circuit. Oscillation circuit OSC powered by the capacitor C ₂ has two oscillation output V _A, and outputs the V _B. Oscillation output V _B is input to the driving circuit B, oscillation output
_VA is input to the drive circuit A via the level shift circuit C. The level shift circuit C is made of a transistor Tr ₁ to Tr ₄ and resistors R _6, R _10, and performs signal transmission without using an insulating element of transformer or the like. The transistor Tr ₁ is supplied oscillation output V _A of the oscillator OSC via a resistor R _10. The transistors Tr ₁ and Tr _{2 form} a current mirror circuit, and the same current as the current flowing through the transistor Tr ₁ also flows through the transistor Tr ₂ . Current flowing through the transistor Tr ₂ is supplied to the current mirror circuit consisting of transistors Tr _3, Tr _4, the same current as the current flowing through the transistor Tr ₃ also flows to the transistor Tr _4. Transistor Tr ₄ is connected to resistor R ₆ in series, it is connected across the capacitor C ₁ via the resistor R _12.

Voltage V _R generated in the resistor R ₆ is applied to the base of the transistor Tr _5, Tr ₆ in the drive circuit A. The emitter of the transistor Tr _5, Tr _6, Tr ₇ is connected to the negative terminal of the capacitor C ₁ via the resistor R _12, collector resistors R _3, R _4, positive terminal of the capacitor C ₁ via the R ₅ It is connected. To the base of the transistor Tr collector of ₅ transistor Tr _9, the collector of the transistor Tr ₆ to the base of the transistor Tr _7,
The collector of the transistor Tr ₇ are respectively connected to the base of the transistor Tr _8. The collector of the transistor Tr ₈ are connected to the positive terminal of the capacitor C _1, a transistor Tr
₉ of the emitter is connected to the negative terminal of the capacitor C _1. The emitter of the transistor Tr ₈ are connected in common to the collector of the transistor Tr _9, and supplies a drive signal from the connection point to the switching element Q _1.

On the other hand, the oscillation output V _B of the oscillator OSC via a resistor R ₁₁ is applied to the base of the transistor Tr _12, Tr ₁₃ in the drive circuit B. The emitter of the transistor Tr _12, Tr _13, Tr ₁₄ is connected to the negative terminal of the capacitor C _2, the collector is connected to the positive terminal of the capacitor C ₂ through a resistor _{R 9, R 8, R 7} . The collector of the transistor Tr ₁₂ is the transistor Tr ₁₁
The base, the collector of the transistor Tr ₁₃ to the base of the transistor Tr _14, the collector of the transistor Tr ₁₄ are connected to the base of the transistor Tr _10. The collector of the transistor Tr ₁₀ is connected to the positive terminal of the capacitor C _2, the emitter of the transistor Tr ₁₁ is connected to the negative terminal of the capacitor C _2. The emitter of the transistor Tr ₁₀ are connected in common to the collector of the transistor Tr _11, and supplies a drive signal from the connection point to the switching element Q _2.

This embodiment is different from the driving circuit A in that the switching element
Transistors Tr ₈ and Tr ₉ that supply on / off current directly to Q ₁
When the transistor Tr ₃ to Tr ₇ and the resistor R ₃ to R ₅ in the preceding stage
It is obtained by inserting the resistor R ₁₂ between the negative line of the power supply become more circuits. A partial view due to the insertion of the resistor R ₁₂ to the drive circuit A shown in Figure 2. FIG. 3 shows operation waveforms of each part of the circuit. In FIG.
V _R , V ₆ , V ₇ , V ₁₂ , and V ₉ are based on the voltage V ₂ . The oscillation output V _A becomes "High" level at time t _0, in the same manner as the circuit of Figure 5 the switching element Q ₁ is turned on. At this time, a voltage signal V _R is "High" level, the transistors Tr _5, Tr ₆ are turned on, the transistor Tr ₇ is turned off. Voltage V ₁₂ generated in the resistor R ₁₂ is raised by the operating current.

The oscillation output V _A becomes "Low" level at time t _1, the switching element Q ₁ is turned off. Current flowing through the choke L ₀ is then tries to continue to flow, flows through the switching element Q ₂ in the negative direction, a negative voltage with respect to the voltage V ₂ reference potential V _0, the reference potential V it is voltage V _{2 0} Higher than. At this time, since the voltage V _R, the drive circuit A becomes "Low" level, the transistors Tr _5, Tr ₆ are turned off, the transistor Tr _7, Tr ₉ is turned on,
Transistor Tr ₈ is off. Then, the reference potential V ₀
By who is higher than the voltage V _2, transistor
The current is easily bypassed via the parasitic diodes D ₂ and D ₅ connected to Tr ₇ and Tr ₉ .

However, the current flowing through the parasitic diode D ₂ is to be suppressed by the resistor R ₁₂ according to the present invention. Further, as shown in FIG. 9, the capacitance component Cx increases due to the internal wiring of the semiconductor integrated circuit.
Even if the wirings of V _R and V ₇ are close to each other, a malfunction as in the related art will not occur. This is because, as shown in FIG. 2, on the path that flows from both ends of the load circuit Z via the diode D _2, to become the resistance R ₁₂ to the emitter side of the transistor Tr ₆ are connected, the voltage V _{When 7} rises,
Even if its impact on the voltage V _R appearing by the capacity component Cx, by resistor R ₁₂ acts an emitter resistor are those possible to prevent the transistor Tr ₆ is fully activated.

That is, at time t _12, the transistor Tr _5, Tr ₆ is turned off, the transistor Tr ₇ is ON, will be the voltage V ₁₂ applied to the resistor R _12, therefore, the transistors in increase in the voltage V _R Even if Tr ₆ tries to turn on, resistance R ₁₂
Will not turn on completely due to the presence of
V ₆ hardly drops. Thus, the transistor Tr ₇ is not turned off, the voltage V ₇ does not increase greatly. Thus, no transistor Tr ₈ is turned on, the voltage V ₉ does not lead to turn on the switching element Q _1.

Thus, by inserting the resistor R _12, the switching element Q ₁ is turned off, even if the reference potential V ₀ which than the voltage V ₂ becomes high potential, the load current to be diverted from the parasitic diode D ₂ As a result, the oscillating operation of the inverter device is stabilized.

FIG. 4 is a circuit diagram of a second embodiment of the present invention. In the present embodiment, in addition to the resistor R ₁₂ for preventing malfunction is obtained by connecting a capacitor C ₃ for diversion. By connecting the capacitor C _3, when a reverse current to the switching element Q ₂ is going flow into the parasitic diode, to connect the element with low impedance between the reference potential V ₀ which the potential V ₁₂ As a result, the shunt current to the parasitic diode can be reduced. By providing such a capacitor C _3, in which it is possible to enhance the effect of the resistance R ₁₂ for preventing malfunction further.

The resistor R ₁₂ is also the case where the circuit configuration of the front portion to provide a control signal to the transistor Tr _8, Tr ₉ for output in the driving circuit A is different from the circuit configuration shown in FIG. 1, malfunctioning easy transistors The same effect can be obtained as long as the structure is inserted into the emitter circuit.

Further, even if the load circuit Z only includes the choke L ₀ and does not include the capacitor C ₀ , the same applies to a load circuit that can generate a state where the reference potential V ₀ is higher than the voltage V ₂ . An effect can be obtained.

[Effects of the Invention] As described above, the present invention provides an inverter device that supplies high-frequency power to a load circuit including an inductance component by alternately turning on and off two main switching elements connected in series. When the driving circuit of the element is formed on a junction-separated type semiconductor integrated circuit having a withstand voltage by a PN junction, the connection point between the two main switching elements and the high potential side when viewed from the P-type region in the PN junction Since a resistor is inserted between the previous stage and the drive circuit, a part of the load current caused by the inductance component can be suppressed from flowing through the PN junction, thereby preventing the circuit from malfunctioning. Therefore, there is an effect that a highly reliable inverter device can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a main part circuit diagram for explaining the operation of the same, FIG. 3 is an operation waveform diagram of the same, and FIG. FIG. 5 is a circuit diagram of a conventional example, FIG. 6 is an operation waveform diagram of the same example, FIG. 7 is a cross-sectional view of a junction-separated type semiconductor integrated circuit, and FIG. FIG. 9 is an equivalent circuit diagram of the example, FIG. 9 is a sectional view showing a state of wiring on a semiconductor integrated circuit, and FIG. 10 is an operation waveform diagram at the time of a malfunction in the conventional example. A, B drive circuit, D ₁ to D ₆ are parasitic diodes, E is a direct current power source, L ₀ is the choke, l load, Q _1, Q ₂ are switching elements, R ₁ to R ₁₂ is the resistance, Tr ₁ ~ Tr ₁₄ is a transistor, and Z is a load circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masataka Mitani 1048 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor Masashi Nakano 5-33-1, Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Kazumi Sugai 53-13-1 Shiba, Minato-ku, Tokyo NEC Corporation (58) Field surveyed (Int.Cl. ⁶ , DB name) H02M 7/42-7/98

Claims (1)

(57) [Claims] 1. A series circuit of two main switching elements is connected in parallel with a first DC power supply, and a load circuit including at least an inductance component is connected in parallel with at least one main switching element. The element drive circuit is constructed on a junction-separated type semiconductor integrated circuit that has a withstand voltage with a PN junction, and each drive circuit is an output switching element that supplies a drive current directly to the main switching element, and the output switching element A driving circuit on the high potential side as viewed from the P-type region in the PN junction, the second DC power supply having one end connected to a connection point of the two main switching elements. And a connection point between the output switching element in the high-potential-side drive circuit and the one end of the second DC power supply and the high-potential-side drive circuit. An inverter device comprising a resistor inserted between a front stage and a road.