JP2771704B2 - Automatic gain control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit (AGC circuit) for stabilizing the level of an output signal by changing the gain according to the level of an input signal.

[0002]

2. Description of the Related Art In data transmission using a telephone line, a modem (modem) for connecting the device to the line is used. In the case of data transmission over a general telephone line, the level of a transmission signal varies depending on the state of the line, and therefore, the modem is provided with an AGC circuit that keeps a received signal at a predetermined level. In such an AGC circuit, digitization is desired so as to be compatible with a one-chip integration with a digital signal processing circuit.
It has been proposed in, for example, US Pat.

FIG. 3 is a block diagram showing a configuration of a digitized AGC circuit. The input signal D _IN converted to a digital value is input to the multiplier 1 and is adjusted to a predetermined level by being multiplied by a gain coefficient G that changes according to the level of the input signal D _IN , and the output signal D _OUT Is output to the next circuit. The gain coefficient G is given by a negative feedback circuit 2 that detects a change in the level of the output signal D _OUT ,
It is configured to decrease as the level of the input signal D _IN increases. That is, the input signal D _IN includes an absolute value circuit 3, a low-pass filter 4, an arithmetic circuit 5, and an integrating circuit 6, and the output signal D _OUT is input to the arithmetic circuit 5 via the absolute value circuit 3 and the low-pass filter 4, after the difference between the reference level V _R objectives on the computing circuit 5 is calculated, and the difference is integrated by the integrating circuit 6, applied to the multiplier 1 as a gain factor G receives the integrated value is an appropriate level conversion It is configured to be. Therefore, when the average level of the output signal D _OUT falls below the reference level V _R , the operation result of the operation circuit 5 becomes positive, and the integrated value of the integration circuit 6 increases to increase the gain coefficient G. Works in the direction of amplifying the input signal D _IN , and conversely, when the signal exceeds the reference level V _R , the operation result becomes negative, the integrated value of the integrating circuit 6 decreases, and the gain coefficient G decreases. Is the input signal D _IN
Works in the direction of suppressing.

In such an AGC circuit, since the setting range of the gain coefficient G is restricted, the input signal D _IN
If the fluctuation of the level of the output signal becomes large, sufficient gain control becomes impossible, and the level of the output signal D _OUT cannot be kept uniform. Therefore, as it can be followed large level variation of the input signal D _IN, configured to convert the level shift the digit of the input signal D _IN at the input side of the multiplier 1.

FIG. 4 is a block diagram showing a configuration of an AGC circuit provided with a data shift circuit 7 for shifting the digit of the input signal D _IN . The data shift circuit 7 is provided on the input side of the multiplier 1 and shifts the input signal D _IN to the upper side or the lower side in accordance with the output of the up / down counter 8, thereby doubling the input signal D _IN (+6 dB). ) Or 1/2 times (-6 dB). The up-down counter 8 is configured to count up or down according to the comparison result of the comparison circuit 9 that compares the integrated value or the gain coefficient G of the integration circuit 6 with a predetermined upper limit value _VH and a lower limit value _VL. , for example, up-down when the input signal D _iN to the up-down counter 8 counts up when the integrated value of the integrating circuit 6 exceeds the upper limit value V _H is shifted to the lower side, which falls below the lower limit value V _L The counter 8 is down-counted, the input signal D _IN is shifted to the upper side, and level conversion is performed. At this time, the input signal D _IN is applied to the data shift circuit 7.
, The integration circuit 6 cannot follow a rapid change in the level of the input signal D _IN ′ input to the multiplier 1, so that the integration value of the integration circuit 6 is corrected according to the output of the up / down counter 8. It is composed of

[0006]

However, when the data shift circuit 7 is provided, the integrated value of the integrating circuit 6 is corrected in accordance with the output of the up / down counter 8, and the data is shifted depending on the level of the input signal D _IN . Means that the effect of the data shift circuit 7 appears on the output signal D _OUT . That is, since the level conversion of the input signal D _IN is performed within a range of ± 6 dB, the amount of signal fluctuation increases as the level of the input signal D _IN increases, and the integration value of the integration circuit 6 is reliably corrected. This makes it difficult to convert the level of the input signal D _IN into noise, which is superimposed on the output signal D _OUT .

It is an object of the present invention to provide an AGC circuit capable of obtaining a stable level output signal D _OUT irrespective of fluctuations in the level of an input signal D _IN .

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the feature of the present invention is that an input signal is multiplied stepwise with different gain coefficients and each gain coefficient is multiplied. Multiplication means for simultaneously obtaining signals of corresponding levels, addition means for selectively combining a plurality of signals obtained from the multiplication means to obtain an output signal of a desired level, and an average level of absolute values of the output signals A signal from the multiplying means, comprising: a level judging means for judging whether the value falls within a predetermined range; and an up / down counter for counting up or down according to the judgment of the level judging means. In accordance with the output of the up / down counter.

[0009]

According to the present invention, the gain given to the input signal is set by the output of the up-down counter of the negative feedback circuit, and the gain is gradually increased in small steps in accordance with the counting operation of the up-down counter. Is set. Therefore, it is possible to sufficiently follow a change in the level of the input signal, and an output signal having a stable level can be obtained.

[0010]

An embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of the AGC circuit of the present invention. In this figure, an absolute value circuit 3, a low-pass filter 4, an arithmetic circuit 5, and an integrating circuit 6 are the same as those in FIG.
The output signal D _OUT is an absolute value circuit 3 and a low-pass filter 4
Is input to the arithmetic circuit 5 via a difference between the reference level V _R calculated in the arithmetic circuit 5 are sequentially input to the integration circuit 6.

A feature of the present invention is that the gain of the level conversion circuit 20 is set stepwise in small steps in accordance with the output of the negative feedback circuit 10. The negative feedback circuit 10 adds the integration value of the integration circuit 6 to the two specific levels V _h ,
_Vl ( _Vh > _Vl ) and a comparison circuit 11, and an up / down counter 1 that counts according to the comparison result
The desired gain value is set in the up / down counter 12. Then, the level conversion circuit 20
Are multipliers 21a to 21d for respectively multiplying the input signal D _IN by different gain coefficients G ₁ , G ₂ , G ₃ , and G ₄ , switches 22a to 22d for selectively turning on according to the output of the up / down counter 12, and Switch 22a selectively turned on
22a to 23d that sequentially add the outputs of the multipliers 21a to 21d passing through the switches 22a to 22d. When the switches 22a to 22d are selectively turned on in accordance with the output of the up / down counter 12, the gain of the level conversion circuit 20 is increased. The value is set to the value set in the up / down counter 12. That is, the gain coefficients G ₁ , G ₂ , G ₃ , and G ₄ multiplied by the respective multipliers 21a to 21d are, for example, 1 (0 dB), 1 /
2 (-6 dB), 1/4 (-12 dB), 1/8 (-1
8 dB), and is set in proportion to 2 ⁿ times (n is an integer), and the output of the up / down counter 12 is associated with the switches 22 a to 22 d in order from the upper bit, so that the gain of the level conversion circuit 20 is increased. It changes according to the output of Twelve. In this case, the gain of the level conversion circuit 20 is set in 1/8 steps in a range from 1/8 (-18 dB) to 2 (6 dB).

By the way, the level V _h, V _l is set to the comparison circuit 11 is set so as to sandwich the reference level V _R,
Integrated value level V _h of the integrating circuit 6 configured to compare circuit 11 up or down counts up-down counter 12 when exceeding the range of V _l. For this reason, the integrated value decreases in accordance with the rise of the level of the input signal D _IN , and when the comparator circuit 11 counts down the up / down counter 12, as shown in FIG. Become smaller. Therefore, the gain of the level conversion circuit 20 fluctuates following the change in the level of the input signal D _IN , and the level of the output signal D _OUT falls within a predetermined range.

In this embodiment, the level conversion circuit 20 has a 4-bit configuration. By setting the number of bits to 4 bits or more, the gain of the level conversion circuit 20 can be set over a wider range in finer steps. It is also possible to stabilize the operation. Further, by inputting the output of the level conversion circuit 20 to the multiplier and operating the multiplier in accordance with the integration value of the integration circuit 6, the output of the level conversion circuit 20 is finely adjusted. The level conversion circuit 20 can correct a minute level fluctuation of the output signal D _OUT that has not been sufficiently adjusted. In this case, the feedback loop of the negative feedback circuit 10 is doubled, and operation stability is lacking.
It is necessary to take measures to stop one of the feedback loops in accordance with the operation state of.

[0014]

According to the present invention, the level change of the output signal is detected and the gain of the level conversion circuit is set stepwise in small steps. In addition to the above, the influence of the level conversion circuit hardly appears in the output signal, and an output signal with a stable level can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an AGC circuit according to the present invention.

FIG. 2 is a diagram illustrating a change in gain of a level conversion circuit.

FIG. 3 is a block diagram showing a configuration of a conventional AGC circuit.

FIG. 4 is a block diagram showing a configuration of an AGC circuit provided with a level shift circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplier 2 Negative feedback circuit 3 Absolute value circuit 4 Low-pass filter 5 Operation circuit 6 Integrator circuit 7 Data shift circuit 8 Up / down counter 9 Comparison circuit 10 Negative feedback circuit 11 Comparison circuit 12 Up / down counter 20 Level conversion circuit 21 Multiplier 22 Switch 23 adder

Claims (2)

(57) [Claims] 1. A multiplying means for multiplying an input signal by different gain coefficients in a stepwise manner to simultaneously obtain a signal of a level corresponding to each gain coefficient, and selectively synthesizing a plurality of signals obtained from the multiplying means. Adding means for obtaining an output signal of a desired level; level determining means for determining whether or not the average level of the absolute value of the output signal falls within a predetermined range; and counting up or down according to the determination of the level determining means And an up / down counter that selects the signal from the multiplying means synthesized by the adding means in accordance with the output of the up / down counter. 2. A gain coefficient multiplied by an input signal by said multiplying means is set in proportion to 2 ⁿ times (n is an integer), and selection of a signal multiplied by each gain coefficient and output of said up / down counter are performed. 2. The automatic gain control circuit according to claim 1, wherein each bit of the automatic gain control circuit is associated with the bits.