JP2769760B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as an EPROM or an EEPROM which can make the read characteristics from each memory cell having a memory cell transistor sharing a source potential uniform.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a conventional semiconductor memory device having an EPROM. In FIG. 1, reference numeral 1 denotes a memory cell array, 2 denotes a column address decoder, 3 denotes a sense amplifier, and 4 denotes a row address decoder. I have. Memory cell array 1 is constructed by arranging a plurality of memory cells in a matrix, the drain of the n-channel MOS transistor constituting each memory cell transistor Q _M leading to the same bit line BL by the column address decoder 2, the operation The source is connected to a common source potential supply line 5 made of polysilicon, and both ends of the source potential supply line 5 are made of aluminum . It is connected to a voltage source (not shown) via V _SS lines 6 and 6.

Next, the operation of such a conventional semiconductor memory device will be described. In a memory cell having this type of EPROM, in a state where no data is normally written, a state of “1” where no charge is injected into a floating gate of a transistor constituting the memory cell is held, and data is written. Charge is injected into the floating gate of the transistor constituting the memory cell, and the state becomes "0". The threshold value of the memory cell is modulated, for example, increased by the injected charge, and this change is detected by the sense amplifier. And the data is read.

That is, when a predetermined word line WL is selected by the row address decoder 4, the gate of the memory cell transistor whose gate is connected to the selected word line WL becomes active, and the memory cell transistor whose gate voltage reaches the threshold value is activated. V _SS line 6,6 from the source potential is supplied to the bit line BL via the source potential supply line 5 of the share. The bit line BL is selected by the column address decoder 2, and the data of the selected bit line BL is amplified by the sense amplifier 3 and output.

[0005] Figure 2 is a graph showing the relationship between the threshold value and the power supply voltage V _CC of the memory cell in a memory cell located furthest from the memory cell and V _SS line 6,6 which is located near V _SS line 6,6 The power supply voltage V _CC is shown on the horizontal axis, and the threshold value is shown on the vertical axis. The solid line in the graph of memory cells located near the V _SS line 6,6 and the broken line indicates the threshold values of the memory cells distant position.

As is apparent from this graph, the threshold value of the memory cells located near the V _SS lines 6 and 6 is high, and the threshold value of the memory cells located far away is low. The reason why such a difference occurs is that the threshold value of the memory cell also depends on the data programming time for writing data. However, as described above, when the source of the memory cell transistor is connected to the shared source potential supply line 5, , V
The distance from the _SS line 6,6 is different by people each memory cell husband, be by different Correspondingly also the source resistance, the result V _SS line 6,6
Due to the fact that each of the threshold, the access time becomes different in the distant memory cell from near the memory cell and V _SS line 6, 6 to.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to read data from a memory cell having a memory cell transistor sharing a source potential. , though there is a difference in source potential due to the difference in distance to each memory cell from the V _SS line provided uniform reading characteristics is to provide a semiconductor memory device greatly improve the reliability.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor memory device having memory cells each having a source connected to a common source potential supply line connected to a voltage source via a bit line. In a semiconductor memory device including a transistor and reading data of the memory cell through a sense amplifier based on selection of an address decoder, a distance from a line supplying a source potential to each memory cell is provided.
Signal output from the address decoder corresponding to the separation
Data signal as reference signal with sense amplifier as correction signal
And wherein the correction child to match items.

According to a second aspect of the present invention, there is provided a semiconductor memory device including a transistor constituting a memory cell having a source connected via a bit line to a common source potential supply line connected to a voltage source, and an address decoder. In a semiconductor memory device in which data of the memory cell is read through a sense amplifier based on the selection of
Whether the address decoder selects the bit line to be connected
It is output an address signal et output, a D / A converter for converting the analog signal corresponding thereto, from the D / A converter
Is the gain factor of the current detecting transistor in the sense amplifier based on an analog signal, supplying the source potential
It is characterized in that the adjustment is made according to the distance from the line to the memory cell to each memory cell.

[0010]

According to the first aspect of the present invention, a source potential is supplied.
Address deco according to the distance between the line and each memory cell.
The data signal is referenced by the sense amplifier regardless of the source potential difference , using the signal output from the
It will be corrected to match the signal . According to the second aspect of the present invention, the memory cell from the address decoder is connected.
Address signal for selecting the bit line to be connected is analog
Signal, and based on this analog signal, sense
The source of the gain coefficient of the current detecting transistor definitive in-flops
Fine adjustment can be made in accordance with the distance between the line supplying the potential and each memory cell.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 3 is a schematic diagram of a semiconductor memory device according to the present invention. In the figure, reference numeral 1 denotes a memory cell array, 2 denotes a column address decoder, 3 denotes a sense amplifier, and 4 denotes a row address decoder.

[0012] The memory cell array 1, for example, m rows the number of memory cells having memory cell transistors composed of EPROM, and arranged in a matrix of n columns are configured, the memory cell transistor Q _M of the same line The gate is connected to a row address decoder 4 via a word line WL, and the source is connected to V _SS lines 6, 6 arranged along both sides of the memory cell array 1 via a shared source potential supply line 5 made of polysilicon. are further drain connected to the sense amplifier 3 through the bit line BL is interposed select transistor Q ₁ to Q _n are controlled by the column address decoder 2 on the way. Then, a sense amplifier correction signal for correcting a source potential difference is output from the column address decoder 2 to the sense amplifier 3. This
Here, the sense amplifier correction signal refers to the column address decoder 2
Column address signal output from the bit line BL
Is a select signal for selecting. This select signal is V
Does it correspond to the distance between the _SS line 6, 6 and the memory cell?
When this signal is input to the sense amplifier 3, the sense
The sense amplifier for correcting the source potential difference in the amplifier 3
It can be handled as a pump correction signal.

FIG. 4 is a circuit diagram showing a specific configuration of a source potential correction circuit in the sense amplifier 3. In FIG. 4, reference numeral 11 denotes an operation amplifier constituted by a current mirror circuit,
Reference numeral 12 denotes a threshold value changing circuit. Operation to the amplifier 11 is input a reference signal Ref from the memory cell for reference, not shown, also bit drain which is interposed n-channel MOS transistors 21 to 23 in the middle of the n-channel MOS transistor constituting the memory cell transistor Q _M The line BL is connected to the operational amplifier 11 and the operational amplifier 11
Is connected to a threshold changing circuit 12 and a power supply voltage V _CC via a p-channel MOS transistor 24 in the middle, and the threshold changing circuit 12 includes p-channel MOS transistors 25 and 26 connected in series to the power supply potential V _CC. , The gate of the p-channel MOS transistor 25 is connected to the column address decoder 2, to which a sense amplifier correction signal is input from the column address decoder 2, and the gate of the p-channel MOS transistor 26 is connected to its source side. I have.

The operation amplifier 11 receives a data signal from the n-channel MOS transistor constituting the memory cell transistor Q _M , a threshold correction signal from the threshold changing circuit 12,
Further reference signal Ref from the memory cell transistor for reference are respectively input, and the correction so that the data signal from the memory cell transistor Q _M is equal to the reference signal Ref of the reference transistor adapted to output on the basis of these ing.

The operation of the semiconductor memory device according to the present invention will be specifically described. When the memory cell Q _M located near the V _SS lines 6 and 6 shown in FIG. 3 is selected, the sense amplifier correction signal becomes low level “L” , and the gain coefficient β of the p-channel MOS transistor 25 is increased. 2, a read characteristic equal to the threshold value indicated by the solid line is obtained. The threshold value changing circuit 12 becomes inactive the sense amplifier correction signal becomes the high level "H" when the memory cell located far from the V _SS line 6,6 is selected, p-channel MOS transistor total impedance Is large, that is, the gain coefficient β is small. As a result, the threshold value is higher than the threshold value indicated by the broken line in FIG. 2, and the characteristic is close to the threshold value indicated by the solid line. Whether the sense amplifier correction signal to the high level "H" to the just how far away it was the memory cell from the V _SS line 6,6,
It can be set as needed.

FIG. 5 is a circuit diagram showing another amplifier circuit of the sense amplifier 3 according to the present invention. In this circuit, a digital / analog (D / A) converter 28 is provided at the gate of the p-channel MOS transistor 25 in the threshold value changing circuit 12,
The sense amplifier correction signal from the column address decoder 2 is input to the digital signal input terminal of the D / A converter 28.

When a sense amplifier correction signal is input from the column address decoder 2 to the D / A converter 28, the signal is converted into an analog signal corresponding to each of the signals and is converted into a p-channel MOS transistor.
25 is applied to the gate of p-channel MOS transistor 25
Is finely adjusted in an analog manner so as to decrease the gain coefficient in accordance with the distance from the memory cell located closer to the V _SS lines 6 and 6.

As a result, the output from the operational amplifier 11 becomes V
Regardless of the difference in the distance from the _SS lines 6 and 6 to each memory cell, the source potential difference is corrected substantially uniformly. Other configurations and operations are substantially the same as those of the embodiment shown in FIG. 4, and corresponding portions are denoted by the same reference numerals and description thereof will be omitted.

[0019]

As described above, according to the first aspect of the present invention, the saw
The signal output from the address decoder corresponding to the distance from the line supplying the potential to each memory cell is used as a correction signal.
Coincides with the reference signal a data signal from a memory cell Te
Because they were decided to cormorants correction, by increasing the number of memory cells may not change its threshold, it reads characteristics such as access time, in which excellent effects that can greatly improve the reliability of the read data.

According to a second aspect of the present invention, an address decoder
Select the bit line connected to the memory cell output from
Select the address signal to be converted to an analog signal by the D / A converter.
, And based on this, the current
Supply the gain factor of the output transistor and the source potential
Fine adjustment to enables isosamples corresponds to the distance between the line and the memory cell, and more Hakare the uniformity of the fine reading characteristics, etc. The present invention, which may further increase the reliability are those excellent effects.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional device.

FIG. 2 is a graph showing a relationship between a power supply voltage and a threshold value of a memory cell.

FIG. 3 is a schematic diagram of a semiconductor memory device according to the present invention.

FIG. 4 is an amplifier circuit diagram of a sense amplifier in the semiconductor memory device according to the present invention.

FIG. 5 is another amplifier circuit diagram of the sense amplifier in the semiconductor memory device according to the present invention.

[Explanation of symbols]

1 memory cell array 2 column address decoder 3 sense amplifier 4 row address decoder 5 a source potential supply line 6 V _SS line 11 operation amplifier 12 threshold changing circuit Q _M memory cell transistors 21 to 23 n-channel MOS transistors 24 to 26 p-channel MOS transistor

Claims (2)

(57) [Claims] 1. A transistor comprising a memory cell having a source connected via a bit line to a common source potential supply line connected to a voltage source, and based on selection of an address decoder, data of the memory cell is provided. In a semiconductor memory device that reads data through a sense amplifier, the distance from the line supplying the source potential to each memory cell
Complements the signal output from the corresponding address decoder.
The data signal is used as the positive signal by the sense amplifier as the reference signal.
The semiconductor memory device comprising a correction child to match. 2. A semiconductor device comprising transistors forming memory cells each having a source connected via a bit line to a common source potential supply line connected to a voltage source, and transferring data of the memory cells based on selection of an address decoder. In a semiconductor memory device which reads data through a sense amplifier, the address for selecting a bit line connected to a memory cell is provided.
The address signal output from the Sudekoda, a D / A converter for converting the analog signal corresponding <br/> thereto, the D / A converter
The gain factor of the current detecting transistor in the sense amplifier based on the analog signal output from the vessel, the saw
A semiconductor memory device that adjusts according to a distance from a line supplying a potential to each memory cell.