JP2768730B2 - Hi-Vision receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a multi-channel speech synthesizing apparatus. For example, a 3-1 system (3 front channels, 1 rear channel) 4-channel stereo program in a Hi-Vision receiver is used. The present invention relates to an improvement of a channel mix circuit that combines two channels.

[Conventional technology]

High-definition televisions have twice the number of scanning lines, have a wider screen, and have five times the number of pixels compared to NTSC televisions. be able to. On the other hand, a 3-1 system (3 front channels, 1 rear channel) is considered so that a high sense of reality can be obtained from voice. In this 3-1 system 4-channel stereo broadcast,
Considering the case of viewing by multiple people, three channels are provided in the front so as to provide good viewing in a wide range with little deviation between the video and the sound image, and one independent channel is provided in the rear in order to obtain a sense of spaciousness. I have.

Here, let us consider a method for reproducing a 3-1 system 4-channel program by a normal 2-channel audio receiving apparatus.

"According to JAS Conference '88 Proceedings, audio viewed from HD according p220~225", 3-1 scheme program, the above-mentioned (1), _{i.e., L = L F + 0.7C +} 0.7S R = R _F + 0.7C + 0.7S (where L _F is the front left channel, C is the front center channel, the R _F front channel, S is a rear channel) when synthesized into two channels according to, without much deteriorating the sound quality, It states that it can be synthesized into an acceptable two-channel sound.

FIG. 4 is a block diagram of a conventional high-definition TV for exclusive use of two-channel sound reproduction in which the expression (1) is realized by a simple method. In the figure, 50 is the radio wave transmitted from the satellite (12 GHz)
Parabolic antenna that receives and converts it into a 1 GHz signal, 51
Selects the required channel from the signals sent from the parabolic antenna 50 and outputs the MUSE baseband signal.
Tuner. MUSE here (Multiple Sub
-Nyquist-Sampling Encoding)
This is a band compression technology that enables more than double the amount of Hi-Vision information to be transmitted on one channel of satellite broadcasting. The four audio channels are also compressed and time-multiplexed during the vertical retrace interval of the video signal.

52 is a low-pass filter (hereinafter abbreviated as LPF) for removing out-of-band signals, 53 is an A / D converter, 54 is a time-base expansion, error correction, and decompression method that separates the audio signal from the video signal and sets the audio rate. Performs interleaving, decoding of near instantaneous companding differential PCM, and outputs 4-channel digital audio signal
MUSE audio digital signal processing unit, 71 to 74 are D / A converters that convert audio digital signals to analog signals, and 75 to 78 are L
PF, 79 and 80 are attenuators for multiplying the audio signals of the C and S channels by 0.7, 81 and 82 are analog adders, 83 is the L channel, 84 is the R channel audio output terminal, and 85 is the above-mentioned (1). This is a circuit that realizes the operation of the expression.

Next, the operation will be described. The radio wave from the satellite received by the parabolic antenna 50 is converted into a MUSE baseband signal by the MUSE tuner 51, and is converted into a digital signal by the LPF 52 and the A / D converter 53. An audio signal that is time-division multiplexed in the retrace interval of the video signal is selected, and the MUSE audio digital signal processing unit 54 performs error correction and decodes the quasi-instantaneous companding differential PCM and the like to obtain a 4-channel digital audio signal.
The D / A converters 71 to 74 and the LPFs 75 to 78 produce analog audio signals. The 0.7-times attenuators 79 and 80 and the adders 81 and 82 realize the processing of the expression (1). 84
Get.

As described above, in the configuration of the block diagram of FIG. 4, when a 3-1 system 4-channel program is broadcasted, it is possible to combine and reproduce the 2-channel program according to the equation (1). However, there are the following problems.

[Problems to be solved by the invention]

That is, in the system shown in FIG. 4, despite the production of a two-channel audio output device, four D / A converters 71 to 74 and four LPFs 75 to 78, which are key parts of digital audio, are required. In order to realize the expression (1) by analog signal processing, a large number of analog parts are required.
There is a problem that the cost of the audio output unit increases and it is difficult to reduce the size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. A D / A converter of a channel mix circuit for synthesizing a 3-1 system 4-channel program into two channels and an LPF each of two channels are provided. It is an object of the present invention to provide a multi-channel speech synthesizer which can be constructed in minutes and can minimize other analog parts.

[Means for solving the problem]

Multi-channel speech synthesis apparatus according to the present invention, due to the sampling frequency f _s, the multi-channel PCM audio program, in a multi-channel audio synthesizer for synthesizing and N-channel audio playback N-channel audio programs in accordance with the following equation (1), A (N) = AF (N) + 0.7C + 0.7S (N) (1) (A (N): main channel, AF (N): front channel, C: center channel, S (N): surround Channel, N: 1, 2,..., M, M: an integer of 2 or more) A first storage means for sequentially holding each channel data of AF (N), C, S (N), and an output of the storage means A bit shifter for multiplying data by a power of 2 for each channel in accordance with a predetermined sequence, a second storage means for auxiliary holding an output of the bit shifter, and a second storage means or An adder for selecting necessary data from a bit shifter output or an output of a third storage unit to be described later and performing data addition according to a predetermined sequence; a third storage unit for holding the addition result; , R, and a sequencer for controlling a predetermined data transfer between the respective elements, wherein the addition of the 2- ^k times operation is performed by the bit shifter, and the addition is performed by the adder. The coefficient 0.7 in the above equation (1) is summed to the power of 2 by repeatedly executing The following equation (2) expressed by (n is an integer of 1 or more and b _k is 0 or 1) is executed within 1 / fs per sample.

[Operation] In the present invention, as described above, a digital multiplier having a coefficient of 0.7 and a digital adder are provided,
(1) the calculation _{(L = L F + 0.7C +} 0.7S, R = R F + 0.7C + 0.
7S) is performed as a digital signal.
The D / A converter and the LPF only need two channels each, and the number of other analog components is as small as possible.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First
The figure shows the overall configuration of a high-definition television receiver equipped with a multi-channel speech synthesizer according to one embodiment of the present invention,
In the figure, the same reference numerals as those in FIG. 4 indicate the same parts. Five
5 and 56 are digital multipliers having a coefficient of 0.7, 57 and 58 are digital adders, 59 is a channel mix section for performing arithmetic processing of equation (1) as it is, and 60 and 61 are D / A converters. 6
3 is an LPF, 64 is an L channel, and 65 is an R channel audio output terminal.

Next, the operation will be described. Parabolic antenna 50, MU
The 4-channel digital audio signal obtained through the SE tuner 51, the LPF 52, the A / D 53, and the MUSE audio digital signal processing unit 54 is input to the channel mixing unit 59, and performs the operation of the equation (1). The synthesized two-channel digital signal is converted into an analog signal by D / A converters 60 and 61 and LPFs 62 and 63, and output from audio signal output terminals 64 and 65.

Next, the actual hardware configuration of the channel mix section 59 will be described with reference to FIGS. In Figure 2, 22 is L _F channels, the 23 R _F channel 24 is C-channel, 25 a data input terminal of the S channel. Also, 1-4 input data register, a selector 5 for selecting the input data of the 4 channels, 2 by 7 to shift the bit input data ^0, 2 ^-1, 2 ^-2, 2 ^-3, ... of It is a bit shifter that performs multiplication. FIG. 3 shows the configuration of this bit shifter in detail, and shows an example in which the number of data bits is a 16-bit 2's complement.
Reference numerals 30 to 46 denote 16-input selectors, and reference numeral 47 denotes a control terminal for changing the number of multiplications.

Returning to FIG. 2, reference numeral 8 denotes an auxiliary register for temporarily holding the output of the bit shifter 7, reference numerals 10 and 11 denote selectors for selecting an input signal to the adder 13, and reference numeral 14 denotes that the addition result does not exceed a predetermined number of bits. Overflow limiters to hold the upper limit, 15 to 18 are output data registers that hold the output of the overflow limiter 14, and 19 and 20 are registers 15, 16
Output data register for further holding the contents of the above, 26 is the L channel, 27 is the R channel audio mix output terminal,
28 is a sequencer for controlling the whole.

Next, the operation will be described. L _F input from terminal 22
The channel data register 1, R _F channel data inputted from a terminal 23 to the register 2, the C channel data register 3 input from the terminal 24, S channel data inputted from the terminal 25 to the register 4, respectively It is held.

The-held L _F channel data, C channel data, calculates the L-channel data in accordance with the S channel data to the control by (1) of the sequencer 28,
The process of storing in the register 19 and outputting from the terminal 26 will be described step by step. The R channel data is calculated in exactly the same procedure as the L channel data, and a description thereof will be omitted.

First, as a first step, the calculation of 0.7 times C channel data will be described. First, if 0.7 times is expressed as a power of 2, it becomes 0.72 ^-1 +2 ^-3 +2 ^-4 +2 ^-7 (3). By increasing the number of terms, the approximation accuracy can be increased as much as possible. However, since this is related to the operation processing time of hardware, Expression (2) based on the approximate value of Expression (3) is used.

The selector 3 selects the register 3 (C channel data).

Set to 2 ^-1 by the bit shifter 7 control terminal 47.

The output (2 ^-1 · C) of the bit shifter 7 is stored in the auxiliary register 8.

Setting the bit shifter 7 into two ^-3 from the control terminal 47.

The selector 10 selects the auxiliary register 8, and the selector 11 selects the bit shifter 7.

The adder 13 calculates 2 ⁻¹ · C + 2 ⁻³ and stores the result in the register 17 via the overflow limiter 14.

Setting the bit shifter 7 to 2 ^-4 from the control terminal 47.

The selector 10 selects the bit shifter 7, and the selector 11 selects the register 17.

The adder 13 calculates (2 ^-1 · C + 2 ^-3 · C) +2 ^-4 · C and stores the result in the register 17 via the overflow limiter 14.

Setting the bit shifter 7 to ^2-7 from the control terminal 47.

The selector 10 selects the bit shifter 7, and the selector 11 selects the register 17.

{(2 ^-1 · C + 2 ^-3 · C) + 2 ^-4 · C} + 2
^-7 · C is calculated and stored in the register 17 via the overflow limiter 14.

In order to further increase the calculation accuracy, it is necessary to further increase the term of the expression (3) and to repeat the above-mentioned calculation process. Next, as the second step, the calculation of 0.7 times the S channel data is performed. Since the calculation is performed in the same manner as the calculation process of the 0.7 times C channel data, the description is omitted. The operation result is stored in the register 18.

Next, the calculation of L _F + 0.7C + 0.7S will be described as a third step.

Selecting register 1 (L _F channel data) in selector 5.

2 ⁰ by the control terminal 47 in bit shifter 7 (1 × ×)
Set to.

The selector 10 selects the bit shifter 7, and the selector 11 selects the register 17.

It calculates the L _F + 0.7 C in the adder 13, stored in the register 17 via the overflow limiter 14.

Selector 10 is register 17 and selector 11 is register
Select 18.

The adder 13 calculates (L _F + 0.7C) + 0.7S and stores the result in the register 15 via the overflow limiter 14.

The contents of the register 15 are further stored in the output register 19.

The sampling rate of the 3-1 system audio is 32 KHz even if the above first to third steps are combined and the L channel and the R channel are largely estimated to be 100 sequences.
An operation time of 1/32 KHz ÷ 100 ≒ 313 ns can be taken for one sequence. This is a 1μ rule CMOS LSI
According to this, the operation time can be calculated with a margin, and the realization of a channel mix circuit using digital data is sufficiently possible.

As described above, according to the present embodiment, in the high-vision receiver of two channels of audio, the 3-1 system 4-channel program is synthesized into two channels without changing the digital signal. The LPF and LPF can be used for two channels each, and the number of analog parts is small, the circuit configuration can be tidy, and the digital channel mix circuit can use a multiplier combining bit shift and adder. The circuit size is small, the LSI can be easily formed, reliability and performance can be improved, and the total cost can be reduced.

In the above embodiment, dedicated registers such as an input data register, an auxiliary register, and an output data register are used. However, these registers are combined into one RAM, and a selector, an adder, an overflow limiter, and an input / output are provided on a data bus line of the RAM. A configuration in which lines are connected may be used, and the same effects as in the above embodiment can be obtained.

Further, in the above embodiment, the one incorporated in a high-definition television receiver is shown. However, it is naturally applicable to a VTR or an adapter type channel mixer, and it may be incorporated in an audio device such as a mini component system. Has the effect of

〔The invention's effect〕

As described above, according to the multi-channel sound synthesis device according to the present invention, due to the sampling frequency f _s, the multi-channel PCM audio program, performs N-channel sound reproducing synthesized N-channel audio programs in accordance with the following equation (1) In the multi-channel speech synthesizer, A (N) = AF (N) + 0.7C + 0.7S (N) (1) (A (N): main channel, AF (N): front channel, C: center channel , S (N): surround channel, N: 1, 2,..., M, M: an integer of 2 or more) A first storage means for sequentially holding each channel data of AF (N), C, S (N) A bit shifter for multiplying the output data of the storage means by a power of 2 for each channel in accordance with a predetermined sequence, a second storage means for auxiliary holding the output of the bit shifter, An adder for selecting necessary data from a storage unit or an output of the bit shifter or an output of a third storage unit to be described later and performing data addition according to a predetermined sequence; a third storage unit for holding the addition result; Fourth storage means for storing the combined output of each of the L and R channels, and a sequencer for controlling a predetermined data transfer between the respective elements, wherein an operation of 2- ^k times is added by the bit shifter. Is repeatedly executed by the adder, so that the coefficient 0.7 in the equation (1) is a power-of-two sum. The following equation (2) expressed by (n is an integer of 1 or more and b _k is 0 or 1) is executed within 1 / fs time per sample. When combining two channels, D / A converter, LPF
Is sufficient for each of two channels, and an effect that an analog component can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of the audio section of a two-channel audio HDTV using a multi-channel audio synthesizer according to an embodiment of the present invention, and FIG. 2 is a block diagram of the multi-channel audio synthesizer according to an embodiment of the present invention. Figure, third
FIG. 2 is a detailed block diagram of the bit shifter in FIG. 2, and FIG. 4 is a configuration diagram of a conventional two-channel audio high-vision television using an analog channel mix circuit. In the figure, 1 to 4, 8, 15 to 20 are data registers, 7 is a bit shifter, 13 is an adder, 5, 10, and 11 are selectors, and 28 is a sequencer. In the drawings, the same reference numerals indicate the same or corresponding parts.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-125763 (JP, A) JP-A-1-155707 (JP, A) JP-A-2-299398 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04S 1/00-7/00

Claims (1)

(57) [Claims] 1. A multi-channel PCM audio program with a sampling frequency fs is _converted into N according to the following equation (1).
In a multi-channel audio synthesizer that synthesizes a channel audio program and reproduces N-channel audio, A (N) = AF (N) + 0.7C + 0.7S (N) (1) (A (N): main channel, AF (N): Front channel, C: Center channel, S (N): Surround channel, N: 1,2, ..., M, M: Integer of 2 or more) AF (N), C, S (N) First storage means for sequentially holding each channel data, and storing the output data of the storage means in accordance with a predetermined sequence.
A bit shifter for multiplying the power of 2 by 1 for each channel; a second storage unit for auxiliary holding the output of the bit shifter; an output of the second storage unit or the output of the bit shifter or a third storage unit to be described later An adder for selecting necessary data from the output of the above according to a predetermined sequence and performing data addition; a third storage means for holding the addition result; and a third storage means for storing the sequentially synthesized output of each of the L and R channels. 4) and a sequencer for controlling a predetermined data transfer between the respective elements. The (1) is obtained by repeatedly performing 2- ^k multiplication operation by the bit shifter and addition by the adder. The coefficient 0.7 in the equation is the power sum of 2 A multi-channel speech synthesizer characterized in that the following equation (2) expressed by (n is an integer of 1 or more and b _k is 0 or 1) is executed within 1 / fs per sample.