JP2768383B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to, for example, a PLD (Prototype) having a configuration in which storage cells are provided between bit lines and word lines arranged in a grid.
grammable Logic Device) and RAM (Random Access Memor)
With regard to the improvement of the semiconductor integrated circuit such as y), a large design change is not required even if the scale of the semiconductor integrated circuit changes.

[Conventional technology]

In a conventional semiconductor integrated circuit having a configuration in which a storage cell is provided between a bit line and a word line, when data is stored in the storage cell, a word line at a corresponding address is started up to store a data between the bit line and the storage cell. And the bit line is set to a high potential (logical value "1") according to the data to be stored.
Alternatively, the potential is set to a low potential (logical value “0”). In order to read data stored in the memory cell, a word line at a corresponding address is activated to conduct between the bit line and the word line, and the stored data is recognized according to the potential of the bit line at that time. .

Also, in such a semiconductor integrated circuit, there is no particular problem because only one word line is activated at a time, but it is better to write and read data as many bit lines as possible at the same time. Since there is an advantage that the access time can be shortened, design a bit line driving circuit and a control circuit for controlling the driving circuit in accordance with the number of bit lines to be provided, while considering power consumption at the time of writing and reading. I was

[Problems to be solved by the invention]

However, in the above-described conventional semiconductor integrated circuit, the bit line driving circuit and the control circuit are individually designed according to the number of bit lines. Simply changing the scale of the circuit and the control circuit cannot cope with it, so it is necessary to redesign the control circuit, etc., and as a result, there is an unsolved problem that an increase in design cost and an increase in the design period are inevitable. There were challenges.

The present invention has been made in view of such unresolved problems of the conventional technology, and provides a semiconductor integrated circuit that can respond to PLDs and RAMs of different sizes without major design changes. It is intended to be.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a semiconductor integrated circuit in which a plurality of bit lines and word lines are arranged in a grid and a storage cell is formed between the bit lines and the word lines. A drive circuit control means for controlling a bit line drive circuit for driving the bit line to an arbitrary logic value, for each of the logic blocks; The means are connected in series, and the control end signal of the preceding drive circuit control means is used as the control start signal of the next drive circuit control means.

[Action]

Since the end signal of the control of the drive circuit control means (for example, transmission of a write pulse) for each bit line drive circuit constituting the logic block is the control start signal of the drive circuit control means of the next stage connected in series, The multiple bit lines are
It is driven sequentially for each logical block. Note that the number of bit lines constituting a logical block is determined as appropriate in consideration of power consumption.

When the scale of the integrated circuit is changed, that is, when the number of bit lines is increased or decreased, the number of bit line drive circuits and drive circuit control means is simply increased or decreased according to the increase or decrease.
It can support integrated circuits of different scales.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 to 6 show an embodiment of the present invention.

First, the configuration will be described. In FIG. 1, a plurality of bit lines and word lines (omitted in the figure) are arranged in a grid pattern and, for example, an SRAM (Static) is arranged between the bit lines and the word lines.
Storage unit 1 in which storage cells (omitted in the figure) such as RAM) are formed
A row-side program circuit 2 connected to a word line end extending in the left-right direction in the storage unit 1 and a column-side program circuit 4 connected to a bit line extending in the storage unit 1 in the vertical direction. Is written and read.

The row-side program circuit 2 connects the row-side basic circuits 3 as shown in FIG. 2 in series by the number of word lines between the row-side end bit detection circuit 2a and the row-side first bit detection circuit 2b. A row-side shift register 2c is provided.

Each row side basic circuit 3 is provided with a flip-flop 3a of the two-phase clock CK _1, CK ₂ and the clear signal CLR ₁ is supplied, an output terminal to Q ₁ the flip-flop. 3a, next row side basic It is connected to the input terminal D ₁ of the circuit 3, an inverter 3b, is connected to the word line W through the word line drivers 3c consisting of NOR circuit. The word line driver 3c is supplied with a clock CKW that goes high only when the word line W rises via the inverter 3d.

Therefore, the word line W rises is the case of the output terminal Q ₁ and clock CKW are both H level of the flip-flop 3a (logical value "1").

On the other hand, the column-side program circuit 4 includes a shift register 5 as shown in FIG. 3 between the column-side end bit detection circuit 4a and the column-side leading bit detection circuit 4b and a predetermined number of bit lines B, Are connected in series by the number of the logic blocks 6 grouped into a group.

Each shift register 5 is connected in series by a predetermined number of column-side basic circuits 7 as bit line drive circuits to which bit lines B and are connected, that is, the output terminal of the column-side basic circuit 7.
The Q _2, constitute a shift register connected to the input terminal D ₂ of the next column side basic circuit 7.

Incidentally, among them the column side basic circuit 7, the input terminal D ₂ of the column-side basic circuit 7 located at the top end of the column side constituting the other shift register located in front one of its shift register 5 is connected to the output terminal of the basic circuit, likewise, the output terminal Q ₂ of the column-side basic circuit 7 located on the end,
It is connected to the input terminal D2 of the _first column side basic circuit constituting the shift register 5 located next to its own shift register 5.

Further, each shift register 5, have a write pulse generator 8 as a drive circuit control unit, this write pulse generator 8, a write pulse WR ₁ is supplied.

The write pulse generator 8 is connected in series with the write pulse generator included in the other shift register, and the write end signal of the write pulse generator of the other shift register located immediately before its own shift register 5. As a write start signal WI, one pulse of the write pulse WR ₁ immediately after receiving the write start signal WI is supplied as a write pulse WR ₂ to each column-side basic circuit 7, and the write pulse WR ₂ ends. Immediately after this, the write end signal WO is supplied as a write start signal to the write pulse generator of another shift register located next to its own shift register 5.

As shown in FIG. 4, the column-side basic circuit 7 includes a flip-flop 9 to which two-phase clocks CK ₃ and CK ₄ and a clear signal CLR ₂ are supplied. Connected to bit line B and
One output terminal Q of the flip-flop 9 is the output terminal Q ₂ of the column-side basic circuit 7.

Then, and the bit line B, together with the bit line driver 10a and 10b driven by the write pulse WR ₂ is interposed, the precharge circuit performs bit lines B and precharge according At the time of data reading to a precharge signal PC 11a And 11b are connected to the outside of the position where the bit line drivers 10a and 10b intervene (on the side of the storage unit 1).

Further, the bit line B and the bit line B outside the position where the bit line driver 10 intervenes detect the potential difference between the bit line B and the bit line B, and the data stored in the storage cell of the storage unit 1 has the logical value “1”. A lead terminal RD, which is connected to the input side of the sense amplifier 12 for determining whether the sense amplifier 12 is present or has a logical value "0" and controls the sense amplifier 12, is drawn out.

The input terminal D ₂ of the column-side basic circuit 7 is connected to the NAND circuit 13.
a, and the NAND circuit 13a is supplied with a write control signal SF that goes high when data is written and goes low when data is read.
The output of the NAND circuit 13a is supplied to the NAND circuit 13c.

Further, a read control signal PA which goes high when reading data and goes low when writing data.
And the output of the sense amplifier 12 are supplied to a NAND circuit 13b, and the output of the NAND circuit 13b is supplied to a NAND circuit 13c.

The output of the NAND circuit 13c is output to the flip-flop 9
Is connected to the input terminal D.

 Next, the operation of this embodiment will be described.

FIG. 5 and FIG. 6 are time charts of each signal in the write sequence of this embodiment.

That is, in order to write data to the entire storage unit 1, first, the clear signal CLR ₂ (see FIG. 5A) is supplied to the flip-flop 9 of the column-side basic circuit 7 to clear each flip-flop 9. .

After the flip-flop 9 is cleared, the clock CK ₃ (see FIG. 5B) is supplied to each column-side basic circuit 7 of each shift register 5 constituting the column-side program circuit 4.

Then, in this state, since the write control signal SF is read control signal PA and an H level is L level, the output of the NAND circuit 13a to depend on the state of the output terminal D ₂ of the previous column side basic circuit 7 since the output of the NAND circuit 13b is always H level, the output of the NAND circuit 13c is equal to the state of the output terminal D ₂ of the previous column side basic circuit 7.

Thus, the data in the flip-flop 9, since shifts to the right from FIG. 1 leftward in synchronism with the clock CK _3, the shift register 5 is located in the most end bit detecting circuit 4a side head of The input terminal D ₂ of the column-side basic circuit 7
Sequentially while supplying the data following the first bit of the first bit detector 4b detects, if transmitting a clock CK _3, when the first bit detector 4b detects the leading bit,
Data to be stored in a storage cell corresponding to an arbitrary word line W is stored in each flip-flop 9.

Therefore, when the first bit detector 4b detects the leading bit stops the clock CK _3, and supplies the clock CK ₁ (FIG. 5 (c) refer) to the flip-flop 3a of the row side basic circuit 3, each The data of the flip-flop 3a is shifted.

However, a logical value "1" is stored in only one flip-flop 3a so that a plurality of word lines do not rise at the same time (accordingly, all other flip-flops 3a).
Has a logical value "0" stored therein.)

More specifically, at the start writing, when supplying the clear signal CLR ₁ clears the data in the flip-flops 3a, the input terminal D ₁ of the low-side basic circuit 3 located closest to the row side end bit detecting circuit 2a side Is supplied with only one data of logic value "1" following the first bit detected by the row-side first bit detection circuit 2b, and thereafter, if data of logic value "0" is supplied, the clock CK ₁ Is transmitted, the flip-flop 3a storing the logical value "1" sequentially moves.

Then, after the clock CK ₁ has been transmitted, the clock CKW
(See FIG. 5 (d)).

Then, the output of one inverter 3d in each row side basic circuit 3 is at the L level, the output of the other inverter 3b, output to Q ₁ flip flop 3a is stored in the H level, i.e. flip-flop 3a Therefore, the data stored in the flip-flop 3a is connected to the low-side basic circuit 3 having the logical value "1" because the data stored therein is at the L level only in the low-side basic circuit 3 having the logical value "1". Only the word line W rises.

Then, when the clock CKW rises, the write pulse W
R ₁ (see FIG. 5 (e)) is supplied, and writing of data to the storage unit 1 starts.

First, the shift register 5 is located in the most end bit detecting circuit 4a side, write pulse generator 8 receives a rising edge of the clock CKW as a write start signal WI, one of its immediately write pulse WR _1, write pulse WR ₂ is supplied to each column-side basic circuit 7.

When the write pulse WR ₂ is supplied, in all the column-side basic circuits 7 included in the shift register 5, the bit line B and the bit line drivers 10a and 10b provided thereon are driven, so that the flip-flop Nine data Q is supplied to the bit line B and data is supplied to the bit line.

Therefore, the logic block 6 corresponding to the shift register 5
, All the bit lines B included in the logical block 6 are driven at the same time, so that data writing is performed for each logical block 6, and the power consumption at the time of writing is reduced by the bit line B included in the logical block 6. And a constant value determined by

Then, write pulse generator 8, when finished the sending of write pulse WR _2, toward the write pulse generator 8 of the next stage of the shift register 5 outputs a write end signal WO.

That is, as shown in FIG. 6, the write pulse generator 8 of the shift register 5 at an arbitrary position transmits the write end signal WO transmitted by the write pulse generator 8 of the preceding shift register 5 to its own write start signal WI.
(See FIG. 3 (b)), and _one of the write pulses WR ₁ (see FIG. 3 (a)) immediately thereafter is received as a write pulse WR ₂
Was supplied to the column-side basic circuit 7 as (FIG see (c)), when the transmission of the write pulse WR ₂ is completed, write the write end signal WO (see FIG. (D)) to the next shift register 5 The write pulse signal is supplied to the pulse generator 8, and the next-stage write pulse generator 8 receives the previous-stage write end signal WO as the write start signal WI.

Then, when data is written in the shift register 5 located closest to the first bit detection circuit 4b,
The clock CKW falls in response to the write end signal WO transmitted by the write pulse generator 8 of the shift register 5 (see FIG. 5 (d)), and the clear signal CL
R ₂ is transmitted, the above-described processing is repeated.

Therefore, if the above-described write processing is performed on all the word lines W, the writing of data to all the storage cells included in the storage unit 1 is completed.

As described above, in the above embodiment, data is written for each logical block 6 and the write pulse generator 8 is provided for each shift register 5 corresponding to the logical block 6. 8, the write end signal WO of the next stage is used as the write start signal WI of the next-stage write pulse generator 8. Therefore, the power consumption at the time of writing and the format of the data to be written are constant without providing a special circuit and regardless of the size of the storage unit 1. In addition, the column-side program circuit 4 can be configured only by appropriately increasing or decreasing the shift register 5 in accordance with the scale of the storage unit 1, so that integrated circuits of various scales can be implemented without major design changes. Can respond.

Therefore, there is an advantage that the design cost is reduced and the design period is short.

In the above embodiment, only the sequence of writing data to the storage unit 1 has been described, but the present invention can be applied to, for example, a sequence of reading data.

In other words, if a precharge signal transmission circuit is provided for each shift register 5 and the control end signal of the precharge signal transmission circuit of the preceding stage is used as the control start signal of the precharge signal transmission circuit of the next stage, the size of the storage unit 1 is affected. Therefore, the power consumption at the time of reading and the format of the read data are constant, and it is possible to cope with integrated circuits of various scales without major design changes.

〔The invention's effect〕

As described above, according to the present invention, the bit line drive circuit and the drive circuit control means may be provided in accordance with the number of bit lines constituting the integrated circuit. A large-scale integrated circuit can be accommodated. As a result, manufacturing cost and design time can be reduced, and a plurality of bit lines are driven for each logical block. Various effects can be obtained such that the power consumption at the time of data reading or writing becomes constant without providing and regardless of the scale of the integrated circuit.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a row-side basic circuit, FIG. 3 is a circuit diagram showing an example of a shift register, and FIG. FIG. 5 is a circuit diagram showing an example of a circuit, FIG. 5 is a time chart showing a write sequence, and FIG. 6 is a time chart showing a write sequence in each shift register. 1 ... storage unit, 2 ... row side program circuit, 3 ... row side basic circuit, 4 ... column side program circuit, 6 ...
Logic block 7, column basic circuit (bit line drive circuit), 8 write pulse generator (drive circuit control means), B, bit line, W word line

Claims (1)

(57) [Claims] In a semiconductor integrated circuit in which a plurality of bit lines and word lines are arranged in a grid and a storage cell is formed between the bit lines and word lines, the bit lines are grouped by a predetermined number and logic is provided. A drive circuit control means for forming a block and controlling a bit line drive circuit for driving the bit line to an arbitrary logic value is provided for each of the logic blocks, and further, these drive circuit control means are connected in series and A semiconductor integrated circuit, wherein a control end signal of a preceding drive circuit control means is used as a control start signal of a next drive circuit control means.