JP3540199B2 - Device for reducing power consumption of storage means and method of reducing power consumption of storage means - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a storage unit including a ROM, and more particularly to an apparatus and a method for reducing power consumption in the storage unit.
[0002]
[Prior art]
In general, in a ROM circuit, as in a Random Access Memory (RAM) circuit, reduction in power consumption has not been studied much.
[0003]
However, as the power consumption of RAM circuits and peripheral logic circuits has been reduced, there has been a need to reduce the power consumption of ROM circuits.
[0004]
FIG. 6 shows a configuration example of a conventional ROM circuit. The ROM circuit shown here is a NOR Cell type ROM circuit having a configuration of [(i + 1) * (j + 1) * (h + 1)] words × (n + 1) bits of (h + 1) columns.
[0005]
In this conventional example, (n + 1) sense amplifiers (S / A) 201, a column selector (Column Selector) 203 functioning as a bit line decoder, and (i + 1) * (j + 1) * (h + 1) are arranged. It comprises a ROM cell 205.
[0006]
These are the sense amplifier (S / A) 101, Column Selector 103, (i + 1) * (j + 1) * (h + 1) shown in the first and second embodiments of the storage means according to the present invention described later. It has the same configuration as the arranged ROM cells 105.
[0007]
Next, the operation of the conventional example will be described with reference to the waveform diagram of FIG. However, the waveform diagram of FIG. 7 shows an example in which each signal line of SS [h], BS [j], WL [i] is selected.
[0008]
That is, in response to the transition of the clock signal CLK from "L" to "H" and the read period, the signals SS [h], BS [j], and WL [i] change to "H". Become.
[0009]
Similarly, the ACLK signal changes from "L" to "H". As a result, the sense amplifier S / A 201 starts the sensing operation. On the other hand, when the clock signal CLK changes from “H” to “L”, the signals SS [h], BS [j] and WL [i] become “L”.
[0010]
Similarly, the ACLK signal changes from “H” to “L”. As a result, the sense amplifier S / A 201 ends the sensing operation.
[0011]
As a result, the sense operation time Tsa corresponds to a read period in which the clock signal CLK becomes “H”.
[0012]
As described above, since the sense amplifier S / A continues to operate more than necessary, power consumption required for driving the sense amplifier S / A increases.
[0013]
On the other hand, Japanese Patent Application Laid-Open No. Sho 61-126684 describes a semiconductor integrated circuit having a built-in memory, and particularly discloses a technique for accurately detecting a stop timing of a sense amplifier.
[0014]
However, in the known technique, it is necessary to provide a precharge circuit for each of the bit lines, and therefore, the read operation time is the time obtained by adding the pulse generation delay time to the precharge time.
[0015]
That is, in the known technique, it is configured to sense that the bit line has changed to a potential corresponding to the data of the cell after the bit line has reached a constant precharge potential, and specifically, The dummy cell can detect the timing of the end of the read operation of the sense amplifier by preparing one of ON / OFF data in advance.
[0016]
However, in the known technique, there is a problem that a circuit becomes complicated, which leads to an increase in cost. Further, there is no disclosure about a method capable of detecting the timing of ending the read operation of the sense amplifier without using precharge. .
[0017]
Japanese Patent Application Laid-Open No. 8-36895 also describes a method of adjusting a pulse generation timing for determining a read operation time accompanying a speed-up of a read operation in a semiconductor integrated device. A method for precharging a bit line is disclosed.
[0018]
In the known technique, the read operation time is a time obtained by adding the pulse generation delay time to the precharge time. In order to optimally adjust the margin included in the pulse generation delay time, a plurality of dummy data lines are provided. It is characterized in that it is used individually and utilized as a capacity.
[0019]
Therefore, in the related art, similarly to the above, the dummy cell can detect the timing of the end of the read operation of the sense amplifier by preparing one of the ON / OFF data in advance. In the known art, there is a problem that a circuit becomes complicated, which leads to an increase in cost. Further, there is no disclosure about a method capable of detecting the timing of the end of the read operation of the sense amplifier without using precharge.
[0020]
Japanese Unexamined Patent Publication No. 3-245396 describes a dynamic semiconductor memory device. In order to shorten the time for outputting data to the outside, a timing generation circuit includes a pull-up transistor control signal and a pull-down transistor control signal. And a method of controlling to output the column address decoder control signal and the other of the pull-up transistor control signal and the pull-down transistor control signal in this order. There is no description about a technique for reducing the power consumption of the memory circuit.
[0021]
On the other hand, Japanese Patent Application Laid-Open No. Hei 6-28856 describes a semiconductor memory device capable of reducing power consumption at the time of refreshing. In refreshing, a bit line disconnection signal is changed to Vcc or GND at the end of sensing. Although a technique is disclosed, there is no description about a technique for reducing power consumption of a sense amplifier using a dummy bit line.
[0022]
Further, Japanese Patent Application Laid-Open No. 9-198868 discloses a technique for reducing current consumption in a semiconductor memory, using a plurality of dummy cell arrays connected to one column of dummy bit lines, A method of inactivating a sense amplifier in a normal bit line after a lapse of a read time in the dummy cell array is disclosed. In the known example, a read time in each of the sense amplifiers is disclosed. There is no description about a technique for detecting the worst state of the above without requiring a specific operation and deactivating the sense amplifier.
[0023]
[Problems to be solved by the invention]
Accordingly, an object of the present invention is to improve the above-mentioned disadvantages of the prior art, provide a pair of dummy bit lines and a plurality of dummy cells connected thereto, and provide a dummy sense amplifier connected to the dummy bit lines. By detecting the output, the operation of the sense amplifier can be stopped properly even in the worst case of the expected delay time in the read operation of the sense amplifier, thereby reducing the power consumption. An object of the present invention is to provide a power consumption reduction device and a power consumption reduction method of a storage unit.
[0024]
[Means for Solving the Problems]
The present invention employs the following technical configuration to achieve the above object.
[0025]
That is, as a first aspect according to the present invention, a word line, a bit line orthogonal to the word line, a storage element provided at each intersection of the word line and the bit line, A word line decoder for driving, a bit line decoder for driving the bit line, and data writing / reading means for writing predetermined information to the bit line or reading predetermined information from the bit line via a sense amplifier; In the storage means, the dummy cells are respectively arranged on the two bit lines provided on the word line and farthest from the word line decoder, and based on the signal of the bit line decoder. Connected to other bit lines in response to an output pattern based on the information of each dummy cell read through the dummy sense amplifier. It is composed of the operation of the sense amplifier are as stopping,
On-bit data is written in the dummy cell of one of the two dummy bit lines, in which the dummy cell is arranged, selected by the bit line decoder, and the dummy cell of the other dummy bit line is written in the dummy cell of the other dummy bit line. , Off-bit data is written,
The dummy cell is provided when both the on-bit data of the dummy cell in which the on-bit data is stored in advance and the off-bit data of the dummy cell in which the off-bit data is stored in advance are read out. Is configured to output a sense amplifier operation stop signal that causes all the sense amplifiers connected to the bit lines other than the bit line to stop operating.In a second aspect according to the present invention, there are provided a power consumption reducing device for a memory unit, a word line, a bit line orthogonal to the word line, and an intersection of the word line and the bit line. Via a memory element provided, a word line decoder for driving the word line, a bit line decoder for driving the bit line, and a sense amplifier, predetermined information is written to the bit line, or In a storage means comprising data writing / reading means for reading predetermined information, at least two bit lines of a plurality of bit lines intersecting the word line are connected to dummy bits to which dummy cells are connected. Read the information of the dummy bit lineFinishedThis is a method for reducing the power consumption of the storage means configured to set the timing after the operation of reading the information of all the bit lines other than the dummy bit line is completed.
[0026]
[Embodiment of the present invention]
Since the power consumption reduction device of the storage means and the method of reducing the power consumption of the storage means according to the present invention employ the above-described technical configuration, for example, data reading of on-bit / off-bit depending on the power supply voltage End timing of the sensing operation of both dummy sense amplifiers in at least two dummy bit lines in which a plurality of dummy cells are provided in a ROM circuit or the like in which the magnitude of time may be reversed. Is detected, and in response to the result, the operation of other normal sense amplifiers is efficiently stopped, so that the power consumption in the sense amplifier can be easily reduced, and In addition, a semiconductor memory device capable of setting an appropriate sensing time with a wide power supply voltage can be obtained.
[0027]
That is, the technical feature of the present invention is how to stop the operation of the sense amplifier at an appropriate fast timing and reduce the consumption of the current flowing through the sense amplifier. At least two pairs of dummy bit lines having amplifiers are arranged at the end of the normal bit line group and at the end farthest from the word line decoder, and the bit data of the dummy sense amplifier is read. The configuration is such that the normal operating state of the sense amplifier is stopped after the output.
[0028]
That is, in the storage device according to the present invention, which of the on-bit time and the off-bit time of the transistor constituting each storage cell is shorter depends on various conditions, environment, and the like in the manufacturing process. Inconsistent, uncertain, unknown in many cases.
[0029]
Therefore, if the sense amplifier is stopped at a predetermined timing, there is a risk that a normal sense amplifier may stop the sense amplifier while data is still being read or before data is read.
[0030]
Therefore, in the present invention, it is recognized that it is necessary to wait until all the sense amplifiers provided in all the normal bit lines have completed the data read operation before stopping the operation of the sense amplifiers. Therefore, the worst condition for the state in which the data read operation is completed for all the sense amplifiers provided in all the normal bit lines is set, and if the condition is satisfied, the operation of the sense amplifier is stopped. The configuration is such that it is determined that there is no problem in stopping the sense amplifier and the sense amplifier is stopped.
[0031]
As a specific example, as described above, the farthest end of the bit line group provided along the word line from the word line decoder is described.InThese two bit lines are dummy bit lines, and when the information of the dummy sense amplifier of the dummy bit line is read, it is determined that the above condition is satisfied.
[0032]
Further, in the present invention, two dummy bit lines are provided, on-bit data is stored in advance in a dummy sense amplifier connected to one dummy bit line, and off-state data is stored in the other dummy sense amplifier. Bit data is stored in advance.
[0033]
That is, in the present invention, the on-time and off-time of the cell including the transistor constituting the storage element are undefined, and therefore, when both the on-bit data and the off-bit data are read out, Is to judge that the time under the worst condition has elapsed.
[0034]
That is, in the present invention, the sense amplifier can be stopped at an appropriate timing without regard to the off-bit time or the on-bit time of each memory cell. Will greatly contribute to the reduction of
[0035]
【Example】
Hereinafter, the configuration of a specific example of the power consumption reduction device of the storage unit and the power consumption reduction method of the storage unit according to the present invention will be described in detail with reference to the drawings.
[0036]
That is, FIG. 1 is a block diagram for explaining the outline of the configuration of a specific example of the power consumption reducing device of the storage means according to the present invention. In the drawing, a word line WL and a bit line orthogonal to the word line WL are shown. BL, a storage element 10 provided at each intersection of the word line WL and the bit line BL, a word line decoder WD for driving the word line WL, a bit line decoder BD for driving the bit line BL, Then, via the sense amplifier 101, predetermined information is written to the predetermined storage element 10 connected to the bit line BL, or predetermined information is read from the predetermined storage element 10 connected to the bit line BL. In the storage means 100 constituted by the data write / read means DK, the position on the word line WL and the farthest from the word line decoder WD. The dummy cells 15 are respectively arranged on the two provided bit lines BL (DM), and the information of the respective dummy cells 15 read out via the dummy sense amplifier 102 based on the signal of the bit line decoder BD. The power consumption reduction device 100 of the storage means is configured to stop the operation of the sense amplifier 101 connected to the other bit lines BL in response to the output pattern based on the output pattern.
[0037]
In the power consumption reduction device 100 of the storage means according to the present invention, one of the two dummy bit lines BL (DM), on which the dummy cells 15 are arranged, selected by the bit line decoder BD. On-bit data is desirably written in the dummy cell BL (DM1) of the line, and off-bit data is desirably written in the dummy cell BL (DM2) of the other dummy bit line BL (DM).
[0038]
Further, in the power consumption reduction device 100 of the storage means according to the present invention, the pair of dummy bit lines BL (DM1) and BL (DM2) in which the dummy cells 15 are arranged are connected to the bit lines. It is preferable that the selection is appropriately made via the dummy selection means 104 provided in the decoder BD.
[0039]
Further, in the present invention, the on-bit data of the dummy cell 15-1 in which the on-bit data is stored in advance and the off-bit data of the dummy cell 15-2 in which the off-bit data is stored in advance are stored. When both are read, a sense amplifier operation stop signal that causes all the sense amplifiers 101 connected to the bit lines BL other than the bit line BL (DM) provided with the dummy cells 15 to be in an operation stop state. It is also desirable to provide a sense amplifier operation stop signal output unit 107 that outputs a PD.
[0040]
On the other hand, in the power consumption reduction device 100 of the storage means according to the present invention, the plurality of bit lines BL are divided into a plurality of bit line groups 20-1, 20-2,. The dummy cells 15 are respectively arranged on the two bit lines BL provided farthest from the word line decoder WD in each of the bit line groups 20-1, 20-2,..., 20-n. In addition, it is preferable that the dummy selection unit 104 and the dummy sense amplifier 102 are provided for each of the bit line groups 20-1, 20-2,..., 20-n.
[0041]
Further, in the power consumption reduction device 100 for the storage unit according to the present invention, the sense amplifier operation stop signal PD is used to operate the sense amplifier 101 in synchronization with the clock signal CLK for driving the storage unit 100. It is also preferable that the system is configured to stop the operation.
[0042]
As is clear from the above description, the power consumption reduction device 100 of the storage means according to the present invention can be implemented in a read only memory (ROM) circuit for low power consumption regardless of on-bit or off-bit read data. An object of the present invention is to provide a semiconductor memory device capable of setting an appropriate sense time for a wide range of power supply voltages by detecting the end timing.
[0043]
That is, as shown in FIG. 1, the dummy cell row 106b including the dummy cell 15-1 in which the on-bit data is written and the dummy cell 15-b in which the off-bit data is written are provided in the ROM cell row furthest from the word line decoder WD. Two dummy cell columns 106a are provided.
[0044]
These dummy cell columns are connected to dummy sense amplifiers 102b and 102a via a dummy selector 104, respectively, and two data of an ON bit and an OFF bit are read.
[0045]
The sense amplifier operation stop signal output means (PD Generator) 107 generates a sense amplifier operation stop signal PD from the two read data. The sense amplifier that has received the sense amplifier operation stop signal PD ends the sensing operation.
[0046]
Thus, the operation time of the sense amplifier can be reduced as compared with the conventional case. Therefore, according to the present invention, the effect that the power consumption in the sense amplifier is reduced can be obtained.
[0047]
Next, a more detailed specific example of the power consumption reduction device 100 of the storage means according to the present invention will be described in the form of an embodiment with reference to FIGS.
[0048]
That is, FIG. 1 is a block diagram showing an entire configuration of a specific example of the power consumption reducing device 100 of the storage unit according to the present invention.
[0049]
The memory circuit shown here is a NORCell-type ROM circuit having a configuration of [(i + 1) * (j + 1) * (h + 1)] words × (n + 1) bits in (h + 1) columns.
[0050]
In this specific example, a dummy sense amplifier (DummyS / A) 102a is provided in a (n + 1) sense amplifier (S / A) 101, a column selector 103, and a ROM cell 105 arranged in (i + 1) * (j + 1) * (h + 1). , 102b, a dummy selector (DummySel.) 104, dummy cell columns 106a and 106b, and a sense amplifier operation stopping means 107 which operates as a PD generator.
[0051]
Dummy cell column 106b is composed of memory cells 15-1 in which only on-bit data is written, and dummy cell column 106a is composed of memory cells 15-2 in which off-bit data is written. Types are available.
[0052]
On the other hand, a dummy cell selecting means for selecting a dummy bit line BL (DM1) and a dummy bit line BL (DM2) arranged as a ROMCell column furthest from the word line decoder WD, and constituting a part of the bit line decoder BD (DummySel.) 104 is provided in the dummy bit line, and turns on / off the connection between the bit line on the dummy cell column side and the bit lines on the dummy sense amplifiers (DummyS / A) 102b and 102a side according to the input signal DS. Do.
[0053]
The dummy sense amplifiers (DummyS / A) 102a and 102b read data of the ON bit of the dummy cell column 106b and the OFF bit of the dummy cell column 106a, respectively.
[0054]
On the basis of the two read dummy data, the PD generator 107 serving as the sense amplifier operation stop unit generates the sense amplifier operation stop signal PD. In response to the sense amplifier operation stop signal PD, the ACLK signal ends the operation of each S / A.
[0055]
FIG. 2 shows a detailed configuration example of the dummy cell columns 106a and 106b, the dummy selector (DummySel.) 104, the dummy sense amplifiers (DummyS / A) 102a and 102b, and the PD generator 107 as the sense amplifier operation stopping means.
[0056]
Each of the dummy cell columns 106a and 106b is composed of (i + 1) * (j + 1) ROM cells, and only the ON bit and the OFF bit only data are written in the cell column 106b.
[0057]
The dummy selector (DummySel.) 104 is turned on only during the period of reading data by the DS signal, the dummy cell columns 106a and 106b and the dummy sense amplifiers (DummyS / A) 102a and 102b are connected by bit lines, and is turned off in other periods. Then, the bit line potential on the 102a side is clamped at "L" and the bit line potential on the 102b side is clamped at "H".
[0058]
Dummy sense amplifier (DummyS / A) 102a outputs off-bit data DSO # A from dummy cell column 106a at the time of data reading, and dummy sense amplifier (DummyS / A) 102b outputs on-bit data DSO # from dummy cell column 106b. B is output.
[0059]
In FIG. 2, the configuration of the dummy sense amplifier (DummyS / A) is the same as that of the sense amplifier S / A101 in FIG.
[0060]
On the other hand, the sense amplifier operation stop signal output means (PD Generator) 107 outputs the sense amplifier operation stop signal PD only when the off bit data is output from DSO # A and the on bit data is output from DSO # B. It becomes "H" and is generated as a sense end signal of the sense amplifier using this timing.
[0061]
Hereinafter, the operation of this example will be described with reference to the waveform diagram of FIG.
[0062]
However, the waveform diagram of FIG. 3 shows an example in which each signal line of SS [h], BS [j], WL [i] is selected.
[0063]
In response to the transition of the clock signal CLK from "L" to "H" at the time of reading, the signals DS, SS [h], BS [j], and WL [i] become "H".
[0064]
At this time, the dummy selector (DummySel.) 104 is turned on by the DS signal.
[0065]
At the same time, the column selecting means (Column Sel) 103 constituting the bit line decoder is in the same state only for the bit line selected by SS [h].
[0066]
After WL [i] whose signal transition is slow becomes “H”, the dummy sense amplifiers (DummyS / A) 102 a and 102 b respectively output “L” as off-bit data from DSO # A and on-bit from DSO # B. Is output.
[0067]
At this time, a case is shown in which the timing at which the off-bit data is output to DSO # A is later than the timing at which the on-bit data is output to DSO # B.
[0068]
Of the DSO # A and DSO # B, the data output becomes slower, that is, in this example, after the DSO # A changes to “H”, the PD signal becomes “H” which is the sense end signal.
[0069]
When the PD signal becomes “H”, the ACLK signal is changed from “H” to “L”, and the operation of each S / A 101 ends.
[0070]
In response to the end of the reading period due to the transition of the clock signal CLK from “H” to “L”, each signal of DS, SS [h], BS [j], WL [i] becomes “L”. It becomes. At this time, the dummy selector (DummySel.) 104 is turned off because DS becomes “L”, and the bit lines of the dummy sense amplifiers (DummyS / A) 102a and 102b are clamped to “L” and “H”, respectively. I do.
[0071]
Therefore, the outputs DSO # A of the dummy sense amplifiers (DummyS / A) 102a and 102b are "L" and the output DSO # B is "H".
[0072]
As described above, the PD signal of the PD generator 107 as the sense amplifier operation stop signal output means is "L" when the DSO # A is not a combination of "H" and the DSO # B is "L".
[0073]
As described above, the S / A operation time Tsa is determined by the period when the ACLK signal is at “H”. In order for the ACLK signal to become “H”, the sense amplifier operation stop signal PD becomes “H” at the timing when both on-bit / off-bit data is read from the dummy cell column during the read period when CLK becomes “H”. ".
[0074]
Therefore, in the present embodiment, it is possible to end the sensing operation without waiting for the timing when CLK becomes “L”.
[0075]
Next, the configuration of another specific example of the power consumption reduction device 100 of the storage unit according to the present invention will be described in detail with reference to FIGS.
[0076]
That is, FIG. 4 is a block diagram showing the configuration of a second specific example of the power consumption reduction device 100 of the storage means according to the present invention, and FIG. 4 shows the entire configuration.
[0077]
The memory circuit shown here is a NOR Cell type ROM circuit having a configuration of [(i + 1) * (j + 1) * (h + 1)] words × (n + 1) bits of (h + 1) columns.
[0078]
This specific example is similar to the first specific example in that (n + 1) sense amplifiers (S / A) 101, Column Selector 103, and ROM cells 105 arranged in (i + 1) * (j + 1) * (h + 1) are dummy. The configuration includes sense amplifiers (DummyS / A) 102a and 102b, dummy selectors (DummySel.) 104, dummy cell columns 106a and 106b, and sense amplifier operation stop signal output means (PD Generator) 107.
[0079]
There are two types of dummy cell columns, 106b in which only on-bit data is written, and 106a in which off-bit data is written, and are arranged in each column.
[0080]
A dummy selector (DummySel.) 104 is provided in the dummy bit line, and turns on / off the connection between the bit line on the dummy cell column side and the bit line on the dummy sense amplifier (DummyS / A) side according to the input signal DS. .
[0081]
The dummy sense amplifiers (DummyS / A) 102a and 102b read data of an off bit of the dummy cell column 106a and an on bit of the dummy cell column 106b, respectively.
[0082]
By using two pieces of dummy data read for each column formed by grouping a predetermined number of bit lines, the sense amplifier operation stop signal output means (PD generator) 107 outputs a sense amplifier to each column. An operation stop signal PD (PD [0] to PD [n]) is generated.
[0083]
In response to the sense amplifier operation stop signal PD (PD [0] to PD [n]), the ACLK [0 to n] signals end the operation of each sense amplifier S / A.
[0084]
The detailed configuration example of the dummy cell columns 106a and 106b, the dummy selector (DummySel.) 104, the dummy sense amplifiers (DummyS / A) 102a and 102b, and the sense amplifier operation stop signal generation means (PD Generator) 107 is a first specific example. Is the same as
[0085]
The configuration different from the first specific example is that, as described above, the end of sensing is detected for each column, and the sensing operation time can be set optimally for each column.
[0086]
Next, the operation of this embodiment will be described with reference to the waveform diagram of FIG. However, the waveform diagram of FIG. 5 shows an example in which each signal line of SS [h], BS [j], WL [i] is selected.
[0087]
In response to the transition of the clock signal CLK from "L" to "H" at the time of reading, the signals DS, SS [h], BS [j], and WL [i] become "H".
[0088]
At this time, the dummy selector (DummySel.) 104 is turned on by the DS signal.
[0089]
The Column Sel 103 constituting the bit line decoder is in the same state only for the bit line selected by SS [h]. After WL [i] whose signal transition is slow becomes “H”, the Dummy S / A 102 a and 102 b output “H” on-bit data and “L” off-bit data, respectively.
[0090]
At this time, the timing at which the two dummy data are output differs for each column. The PD [0: n] signal that has become “H” for each column terminates the sensing operation of the sense amplifier S / A 101 in the same column.
[0091]
In response to the end of the reading period due to the transition of the clock signal CLK from “H” to “L”, each signal of DS, SS [h], BS [j], WL [i] becomes “L”. It becomes.
[0092]
At this time, each of the dummy selectors (DummySel.) 104 is turned off because DS is "L", and clamps the bit lines on the DummyS / A 102a and 102b sides to "L" and "H", respectively. Therefore, the dummy sense amplifiers (DummyS / A) 102a and 102b output "L" and "H", respectively.
[0093]
Each sense amplifier operation stop signal generating means PD (PD Generator) 107 generates a PD signal of “L” other than a combination in which the dummy sense amplifiers (DummyS / A) 102 a and 102 b become “H” and “L”, respectively. I do.
[0094]
As described above, the S / A operation time Tsa [0: n] can be set to an appropriate length for each column.
[0095]
That is, the sense operation time Tsa [0] of the column accessed earlier is set shorter than the sense operation time Tsa [n] of the column accessed later.
[0096]
As can be understood from the specific example of the power consumption reducing device for the storage unit according to the present invention described above, the method for reducing the power consumption of the storage unit according to the present invention basically includes a word line, the word line, Orthogonal bit lines, storage elements provided at respective intersections of the word lines and the bit lines, word line decoders for driving the word lines, bit line decoders for driving the bit lines, and sense amplifiers A plurality of bits intersecting with the word line in a storage means including data writing / reading means for writing predetermined information to the bit line or reading predetermined information from the bit line. Of the lines, at least two bit lines are set as dummy bit lines to which dummy cells are connected, and the timing of reading information of the dummy bit line is determined by the dummy bit line. Read operation of information of all the bit lines of the outer is the power consumption reducing method of the configured storage means so as to set after completion.
[0097]
In the power consumption reducing method of the storage means according to the present invention, the information of the dummy cell connected to the dummy bit line is read by a dummy sense amplifier connected to the dummy bit line. Is desirable.
[0098]
Further, in the method of reducing power consumption of the storage means according to the present invention, the memory means is connected to all bit lines other than the dummy bit line in response to a result of reading information of the dummy bit line. The sense amplifier is configured to stop operating.
[0099]
Further, in the method for reducing power consumption of the storage unit according to the present invention, the plurality of bit lines are divided into a plurality of groups, and at least two dummy bit lines having the dummy cells for each group are provided. It is also desirable that the above-described method be performed by providing a dummy sense amplifier connected to the dummy bit line.
[0100]
On the other hand, in the method for reducing power consumption of the storage means according to the present invention, on-bit data is stored in the dummy cell connected to the first dummy bit line among the two dummy bit lines. In addition, it is also desirable that the dummy cells connected to the second dummy bit line store off-bit data.
[0101]
Further, in the method for reducing power consumption of the storage means according to the present invention, when the bit information of the first and second dummy bit lines is read, the bits of the first and second dummy bit lines are read out. It is preferable to generate a sense amplifier operation stop signal for stopping the operation of the sense amplifiers connected to all the bit lines other than the dummy bit lines in response to the information read pattern.
[0102]
Further, in the power consumption reducing method of the storage unit according to the present invention, the sense amplifier operation stop signal is configured to stop the operation of the sense amplifier in synchronization with a clock signal for driving the storage unit. It is also preferable to do so.
[0103]
【The invention's effect】
Since the power consumption reduction device of the storage means and the power consumption reduction method of the storage means according to the present invention employ the technical configuration as described above, in a conventional ROM circuit, depending on the power supply voltage, There is a case where the magnitude of the read time is reversed between the on-bit and the off-bit. Therefore, if the sensing operation is terminated at the timing of the on-bit data read, there is a problem that the off-bit data cannot be read. However, according to the present invention, it is possible to set an appropriate sense time in a wide range of power supply voltages by detecting the sense end timing of both the ON bit and the OFF bit.
[0104]
In the present invention, a dummy cell column in which only on-bit data is written and a dummy cell column in which only off-bit data are written are arranged farthest from the word decoder requiring the longest access, and both data are stored in the dummy sense amplifier. In response to the read timing, a sense amplifier operation stop signal PD, which is a sense amplifier end detection signal, is generated.
[0105]
For this reason, the sensing operation can be completed earlier than before, and the sensing operation can always be completed after the data reading of all bits is completed even if the applied power supply voltage changes and the read time of the on-bit / off-bit is reversed.
[0106]
In other words, with such a configuration, the sensing operation can be completed after reading all the bits of data, regardless of the magnitude of the on / off bit data reading time depending on the power supply voltage, and the sensing operation time can be reduced.
[0107]
As a result, unnecessary sensing operation can be stopped, so that the power consumption required for the sense amplifier S / A can be reduced.
[0108]
Also, the bit lines are divided into a plurality of groups (columns), and a dummy cell column of on-bit data and a dummy cell column of off-bit are arranged for each column, and the same as described above is individually performed for each group (column). By performing the operation, the timing of the end of the sense operation of each S / A can be set for each column, so that the sense operation time can be appropriately set according to the different access time for each column. In a column having a short length, the sensing operation time can be further reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a specific example of an apparatus for reducing power consumption of a storage unit according to the present invention.
FIG. 2 is a block diagram illustrating a dummy cell portion in a specific example of the power consumption reducing device of the storage means according to the present invention.
FIG. 3 is a timing chart illustrating a driving procedure of the power consumption reduction device of the storage unit according to the present invention.
FIG. 4 is a block diagram illustrating a configuration of another specific example of the power consumption reducing device of the storage unit according to the present invention.
FIG. 5 is a timing chart illustrating a driving procedure in another specific example of the device for reducing power consumption of a storage unit according to the present invention.
FIG. 6 is a block diagram illustrating a configuration example of a conventional power consumption reducing device for storage means.
FIG. 7 is a timing chart for explaining a driving procedure of a conventional power consumption reducing device for storage means.
[Explanation of symbols]
10 ... storage element
15, 15-1, 15-2 ... dummy cell
20-1, 20-2, ..., 20-n ... bit line group
100 ... power consumption reduction device for storage means
101 ... Sense amplifier
102 ... Dummy sense amplifier
104 ... Dummy selection means
105 ... cell row
106: dummy cell row
107 ... Sense amplifier operation stop signal output means

Claims (11)

A word line, a bit line orthogonal to the word line, a storage element provided at each intersection of the word line and the bit line, a word line decoder for driving the word line, and a bit for driving the bit line In a storage means including a line decoder and a data write / read means for writing predetermined information to the bit line via a sense amplifier or reading predetermined information from the bit line, In addition, dummy cells are respectively arranged on two bit lines provided farthest from the word line decoder, and each of the dummy cells is read out via a dummy sense amplifier based on a signal of the bit line decoder. Stop operation of sense amplifiers connected to other bit lines in response to an output pattern based on information of the dummy cell Is configured,
On-bit data is written in the dummy cell of one of the two dummy bit lines, in which the dummy cell is arranged, selected by the bit line decoder, and the dummy cell of the other dummy bit line is written in the dummy cell of the other dummy bit line. , Off-bit data is written,
The dummy cell is provided when both the on-bit data of the dummy cell in which the on-bit data is stored in advance and the off-bit data of the dummy cell in which the off-bit data is stored in advance are read out. A sense amplifier operation stop signal for setting all sense amplifiers connected to bit lines other than the bit line to an operation stop state, and outputting a sense amplifier operation stop signal . 2. The storage device according to claim 1, wherein the dummy bit line on which the dummy cell is arranged is configured to be selected via dummy selection means provided in the bit line decoder. Means power reduction device. The plurality of bit lines are divided into a plurality of bit line groups, and dummy cells are respectively arranged on two bit lines provided at positions farthest from the word line decoder in each bit line group. 3. The device according to claim 1, wherein the dummy selection unit and the dummy sense amplifier are provided for each bit line group. 4. The sense amplifier according to claim 1, wherein the sense amplifier operation stop signal is configured to stop the operation of the sense amplifier in synchronization with a clock signal for driving the storage unit. Power consumption reduction device for storage means. A word line, a bit line orthogonal to the word line, a storage element provided at each intersection of the word line and the bit line, a word line decoder for driving the word line, and a bit for driving the bit line In the storage means comprising a line decoder and data writing / reading means for writing predetermined information to the bit line via the sense amplifier or reading predetermined information from the bit line, the word line At least two of the plurality of bit lines intersecting with the dummy bit line are connected to the dummy cell, and the timing of ending the reading of the information of the dummy bit line is set to be equal to all the bits other than the dummy bit line. A method for reducing power consumption of a storage unit, wherein the setting is performed after a line information reading operation is completed. 6. The method according to claim 5, wherein information of the dummy cell connected to the dummy bit line is read by a dummy sense amplifier connected to the dummy bit line. 7. The storage according to claim 5, wherein the operation of the sense amplifier connected to all the bit lines other than the dummy bit line is stopped in response to a read result of the information of the dummy bit line. Means to reduce power consumption. The plurality of bit lines are divided into a plurality of groups, and each group is provided with at least two dummy bit lines having the dummy cells and a dummy sense amplifier connected to the dummy bit lines. The method for reducing power consumption of a storage unit according to any one of claims 5 to 7. Of the two dummy bit lines, the dummy cell connected to the first dummy bit line stores on-bit data, and the dummy cell connected to the second dummy bit line. 9. The method according to claim 5, wherein off-bit data is stored in the connected dummy cells. When reading the bit information of the first and second dummy bit lines, all bit lines other than the dummy bit line respond to the read pattern of the bit information of the first and second dummy bit lines. 10. The method according to claim 5, wherein a sense amplifier operation stop signal for stopping the operation of the connected sense amplifier is generated. 11. The sense amplifier according to claim 5, wherein the sense amplifier operation stop signal is configured to stop the operation of the sense amplifier in synchronization with a clock signal for driving the storage unit. A method for reducing power consumption of storage means.

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