CN105448329A - Static random access memory and data writing-in method and input and output circuits thereof - Google Patents
Static random access memory and data writing-in method and input and output circuits thereof Download PDFInfo
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- CN105448329A CN105448329A CN201410308928.6A CN201410308928A CN105448329A CN 105448329 A CN105448329 A CN 105448329A CN 201410308928 A CN201410308928 A CN 201410308928A CN 105448329 A CN105448329 A CN 105448329A
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Abstract
A static random access memory and a data writing-in method and input and output circuits thereof are disclosed, the method is as follows: detecting that a gating signal line is selected, wherein the gating signal line distinguishes writing-in and reading-out; according to the selected gating signal line, selecting a bit line corresponding to the selected gating signal line; respectively connecting a control circuit connecting line forward direction and a control circuit connecting line reverse direction by the selected bit line; according to the data to be written, changing the voltage of the control circuit connecting line forward direction or the control circuit connecting line reverse direction; amplifying a voltage difference between the control circuit connecting line forward direction and the control circuit connecting line reverse direction to a power source voltage by a sense amplifier; and writing data outputted by the sense amplifier in a destination storage unit of a memory cell array by the selected bit line. The rate of reuse of various components of a circuit is higher in the writing-in and reading-out process of the static random access memory, writing-in and reading-out can be achieved by one same circuit, and the space occupied by input and output circuits can be reduced.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of static RAM and method for writing data, imput output circuit.
Background technology
Random access memory (RandomAccessMemory, RAM) static RAM (StaticRandomAccessMemory can be divided into, and dynamic RAM (DynamicRandomAccessMemory, DRAM) SRAM).Wherein, as long as static RAM keeps energising just can preserve the data of its storage inside, without the need to periodically upgrading, and writing and reading speed is all faster than dynamic RAM.But its integrated level is lower, the storage unit of each dynamic RAM only needs a transistor and a small capacitances, and the storage unit of each static RAM then needs two to ten transistors (main flow is six or eight) more additional interlock circuits.Therefore, when capacity is identical, static RAM can take more space than dynamic RAM usually.The space hold how reducing static RAM is a difficult problem of storer and even integrated circuit fields always.
As shown in Figure 1, static RAM comprises memory cell array, address decoder, overall control circuit and one or more input and output (input/output, IO) circuit.
In static RAM, it is the interface circuit of itself and external signal around the memory cell array lining up matrix form, comprise orthogonal wordline and bit line, for Fig. 1, the line of horizontal direction is wordline, the line of vertical direction is bit line, and the infall of the bit line of each root wordline and every a pair logical complement points to a storage unit in memory cell array.Each storage unit in the memory cell array of each imput output circuit institute management and control is all corresponding to a group address, and each group address can corresponding one or more storage unit (depending on the quantity of imput output circuit in this static RAM).
Can comprise the imput output circuit of multi-set parallel in a static RAM, a part for each group imput output circuit management and control memory cell array, the capacity of its management and control is determined by the multiplexing way of number of word lines and this imput output circuit.For Fig. 1, comprise 8 parallel wordline (WL0 to WL7), the bit line (namely multiplexing way is 4) of each group imput output circuit management and control 4 pairs of logical complements, then the capacity of each group imput output circuit management and control is 32 bits (bit).
In prior art, imput output circuit generally includes three parts: multiplexer, write control circuit and read-out control circuit.The major function of three parts is as follows:
By the multiplexer of management and control, for selecting and cut off the connection of bit line to write control circuit/read-out control circuit of the logical complement in memory cell array, determine and should carry out write/read operation to which array storage unit in memory cell array;
Write control circuit, for management and control data input pin (Data-in, DI), and provides driving to write data into memory cell array;
Read-out control circuit, mainly comprises sense amplifier, and the voltage difference for the bit line by logical complement is amplified and exported data.
As shown in Figure 2, be the mainstay framework of the imput output circuit of static RAM in prior art.In figure, each port implication is as follows:
YSL---gating signal logic low level, YSH---gating signal logic high,
BLL/BLBL---bit line logic low level, BLH/BLBH---bit line logic high,
WBL/WBLB---write circuit connecting line, RBL/RBLB---sensing circuit connecting line,
DI---data input pin, DO---data output end,
PRCH---precharging signal, IN_EN---input enable signal,
WEN---write enable signal, SA_EN---sense amplifier enable signal.
It should be noted that, the bit line of multipair logical complement can be comprised between bit line logic low level BLL/BLBL and bit line logic high BLH/BLBH, bit line coordinates the storage unit corresponded in memory cell array with each root wordline, the logarithm of bit line depends on the multiplexing way (simultaneously also equaling the multiplexing way of this imput output circuit) of multiplexer, such as four path multiplexers (MUX4) employed in figure 1, then comprise the bit line of 4 pairs of logical complements, for eight path multiplexers (MUX8), then comprise the bit line of 8 pairs of logical complements, for 16 path multiplexers (MUX16), then comprise the bit line of 16 pairs of logical complements, by that analogy.
Correspondingly, between gating signal logic low level YSL and gating signal logic high YSH, also can comprise many gating signal lines, and each root gating signal line corresponds to the bit line of a pair logical complement.
Wherein:
Multiplexer passes through gating signal logic low level YSL in gating signal logic high YSH, the bit line of a pair logical complement is chosen from bit line logic low level BLL/BLBL to bit line logic high BLH/BLBH, be connected to write circuit connecting line WBL/WBLB, or sensing circuit connecting line RBL/RBLB;
In write cycle time, write effectively enable, data to be written are received from data input pin DI, and write to write circuit connecting line WBL/WBLB, the voltage of the single line in write circuit connecting line WBL/WBLB changes, and by multiplexer, the voltage of in the bit line of a pair logical complement bit line is also changed thereupon, and storage unit selected in final upset memory cell array, thus realize write operation;
In the read cycle, the bit line of a pair logical complement corresponding with Destination Storage Unit is selected, and be connected with sensing circuit connecting line RBL/RBLB, the logical zero that Destination Storage Unit stores or logical one can make the voltage of the single line in sensing circuit connecting line RBL/RBLB change, SA_EN is effective for sense amplifier enable signal, voltage difference between sensing circuit connecting line two lines is amplified, and data are exported by data output end DO the most at last.
In the imput output circuit framework of above-mentioned static RAM, the write control circuit of imput output circuit and read-out control circuit are independently two parts.And this imput output circuit realizes the principle of write-in functions, distinct with the principle realizing read out function, especially the signal that sense amplifier exports in the read cycle is directly exported by data output end, in write cycle time, then not the signal that sense amplifier exports directly is delivered to bit line realize write, even in write control circuit, not comprise sense amplifier.As previously mentioned, because this imput output circuit realizes the principle of write-in functions, and the principle realizing read out function is distinct, therefore, is also just difficult to an entirety that write control circuit and read-out control circuit permeated.
In addition, correspond on domain by the structure of static RAM, as can be seen from Figure 1, imput output circuit can be subject to the restriction of the size of memory cell array own on width.Particularly, in order to avoid taking the wiring space of the imput output circuit of periphery, therefore, imput output circuit can not exceed the width of the memory cell array of its management and control on width.
Specific to each ingredient in imput output circuit, as previously mentioned, in prior art, imput output circuit generally includes: multiplexer, write control circuit and read-out control circuit three part.Wherein, the width of multiplexer can change along with the change of its multiplexing way, and particularly, the multiplexing way of multiplexer is more, then the memory cell array of its management and control is also wider, and vice versa.That is, the width of multiplexer can increase with the width synchronization of the memory cell array of its management and control, synchronously reduce.Therefore, the restriction on above-mentioned width meets than being easier to for multiplexer.
But the size of write control circuit and read-out control circuit can't change along with the change of multiplexing way.No matter the multiplexing way of this imput output circuit is how many, and the width of the memory cell array of no matter its management and control is how many, and the size of write control circuit and read-out control circuit does not have significant change.
For these reasons, for the imput output circuit that multiplexing way is less, such as, when multiplexing way is 2 or even 1, only has two storage unit or even only have the width of a storage unit to hold write control circuit and read-out control circuit.Now, in order to avoid taking the wiring space of the imput output circuit of periphery, the height increasing circuit can only be forced to, finally cause the height of whole static RAM to increase.
Summary of the invention
The technical matters that the present invention solves is: how the write control circuit of imput output circuit in prior art and the function of read-out control circuit to be realized by same circuit.
In order to solve the problem, the embodiment of the present invention provides a kind of static RAM method for writing data, comprising:
Detect that a certain gating signal line is selected, described gating signal line corresponds to the bit line of a pair logical complement, and writing and reading distinguished by described gating signal line;
According to selected gating signal line, choose the bit line corresponding with it;
Selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line reverse;
Receive data to be written from data input pin, and change described control circuit connecting line forward or the reverse voltage of control circuit connecting line according to described data to be written;
By sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage;
Via described selected bit line, the data that described sense amplifier exports are write to the Destination Storage Unit in memory cell array.
Optionally, described gating signal line distinguishes writing and reading specifically: the gating signal line for writing is connected with described bit line by a nmos pass transistor, and is connected with described bit line by a PMOS transistor for the gating signal line read.
Optionally, described sense amplifier is by the management and control of sense amplifier enable signal, and described sense amplifier enable signal is connected with the reverse enable signal of sense amplifier by a phase inverter; Described to change described control circuit connecting line forward or the reverse voltage of control circuit connecting line according to described data to be written after, the signal that the reverse enable signal of sense amplifier exports is after phase inverter negate, make described sense amplifier enable signal effective, described sense amplifier is started working.
Optionally, described sense amplifier enable signal is effective when high level, and the reverse enable signal of described sense amplifier is effective when low level, or described sense amplifier enable signal is effective when low level, and the reverse enable signal of described sense amplifier is effective when high level.
Optionally, described selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line oppositely before, by precharging signal and the reverse enable signal management and control of sense amplifier, turn off control circuit connecting line forward and the reverse precharge of control circuit connecting line.
Optionally, the address that address decoder receives according to it, chooses a certain gating signal line.
Optionally, described data input pin is by the management and control of input enable signal, described selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line oppositely after, described input enable signal is effective, and receives data to be written from data input pin.
In order to solve the problems of the technologies described above, the embodiment of the present invention also provides a kind of imput output circuit of static RAM, comprising: multiplexer and write read-out controller; Wherein,
Described multiplexer connects the storage unit in the memory cell array of its management and control by the bit line of one or more pairs of logical complement, bit line described in every a pair connects the gating signal line corresponding with it respectively, and writing and reading distinguished by described gating signal line;
Said write read-out controller comprises sense amplifier, data input pin and data output end; Described data input pin connection control circuit connecting wire forward and control circuit connecting line reverse; Described sense amplifier be used for by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage;
Oppositely be connected with control circuit connecting line by control circuit connecting line forward between described multiplexer with said write read-out controller.
Optionally, described gating signal line distinguishes writing and reading specifically: the gating signal line for writing is connected with described bit line by a nmos pass transistor, and is connected with described bit line by a PMOS transistor for the gating signal line read.
Optionally, described sense amplifier is by the management and control of sense amplifier enable signal, and described sense amplifier enable signal is connected with the reverse enable signal of sense amplifier by a phase inverter; Described sense amplifier enable signal is effective when high level, and the reverse enable signal of described sense amplifier is effective when low level, or described sense amplifier enable signal is effective when low level, and the reverse enable signal of described sense amplifier is effective when high level.
Optionally, said write read-out control unit also comprises: for being reversed the precharge unit of precharge to described control circuit connecting line forward and control circuit connecting line, and described precharge unit is by precharging signal and the reverse enable signal management and control of sense amplifier.
Optionally, described gating signal line link address code translator.
Optionally, described data input pin, by the management and control of input enable signal, when described input enable signal is effective, receives data to be written from data receiver.
In order to solve the problems of the technologies described above, the embodiment of the present invention also provides a kind of static RAM, comprising: memory cell array and address decoder, also comprises above-mentioned imput output circuit.
Compared with prior art, technical scheme of the present invention has following beneficial effect:
The present invention is in write cycle time, first data are write to control circuit connecting line forward and control circuit connecting line is reverse, then by sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage, finally carry out write by the output of sense amplifier or read, make the reusability of each components and parts in circuit in writing and reading process higher, thus writing and reading can adopt same circuit to realize, reduce the space hold of imput output circuit.
Further, correspond on domain, especially for the less imput output circuit of multiplexing way, can effectively avoid it to be forced to increasing circuit height not because width.
Further, write enable signal of the prior art is no longer needed in write cycle time, the output signal of sense amplifier is write direct Destination Storage Unit, data input pin is then by the management and control of input enable signal, namely eliminate write enable signal by input the multiplexing of enable signal, thus further reduce the space hold of circuit.
Further, be connected with described bit line by a nmos pass transistor for the gating signal line write, and be connected with described bit line by a PMOS transistor for the gating signal line read, thus achieve and distinguish writing and reading by gating signal line.
Further, described sense amplifier enable signal is connected with the reverse enable signal of sense amplifier by a phase inverter, strengthens the driving force to sense amplifier, and achieves multiplexing in writing and reading process of sense amplifier.
Accompanying drawing explanation
Fig. 1 is static RAM structured flowchart;
Fig. 2 is the inputting and outputting circuit structure block diagram of static RAM in prior art;
Fig. 3 is the inputting and outputting circuit structure block diagram of static RAM in the embodiment of the present invention;
Fig. 4 is static RAM method for writing data process flow diagram in the embodiment of the present invention;
Fig. 5 is the circuit structure diagram of the imput output circuit of static RAM in the embodiment of the present invention;
Fig. 6 is static RAM data read method process flow diagram in the embodiment of the present invention;
Fig. 7 is that the imput output circuit of static RAM in the embodiment of the present invention is at write cycle time and the signal waveforms in the read cycle;
Fig. 8 is the circuit structure diagram of another embodiment of imput output circuit of static RAM in the embodiment of the present invention.
Embodiment
According to the analysis of background technology part, in prior art static RAM imput output circuit in, write control circuit and read-out control circuit are independently two parts.And this imput output circuit realizes the principle of write-in functions, and the principle realizing read out function is distinct.Therefore, an entirety that write control circuit and read-out control circuit permeated also just is difficult to.
Because the size of write control circuit and read-out control circuit can't change along with the change of the multiplexing way of this static RAM, therefore, for the imput output circuit that multiplexing way is less, correspond on domain, only have two storage unit or even only have the width of a storage unit to hold write control circuit and read-out control circuit.Now, in order to avoid taking the wiring space of the imput output circuit of periphery, the height increasing circuit can only be forced to, finally cause the height of whole static RAM to increase.
For the above-mentioned defect of prior art, inventor improves the structure of the imput output circuit of static RAM and method for writing data thereof, makes the function of write control circuit and read-out control circuit that same circuit can be adopted.Also significantly reduce the space shared by write control circuit and read-out control circuit simultaneously, on width, be especially not easy the width of the memory cell array exceeding its management and control.
For making those skilled in the art understand better and realize the present invention, referring to accompanying drawing, be described in detail by specific embodiment.
As described below, the embodiment of the present invention provides a kind of static RAM method for writing data.
First, the realization of this method for writing data, needs to be assisted to distinguish writing and reading by multiplexer.
With reference to the inputting and outputting circuit structure block diagram of the static RAM shown in Fig. 3, in figure, each port implication is as follows:
YSRL---gating signal logic low level reads,
YSRH---gating signal logic high reads,
YSWL---gating signal logic low level writes,
YSWH---gating signal logic high writes,
BLL/BLBL---bit line logic low level, BLH/BLBH---bit line logic high,
DL---control circuit connecting line forward, DLB---control circuit connecting line is reverse,
DI---data input pin, DO---data output end,
PRCH---precharging signal, IN_EN---input enable signal, SA_EN---sense amplifier enable signal.
It should be noted that, the bit line of multipair logical complement can be comprised between bit line logic low level BLL/BLBL and bit line logic high BLH/BLBH, gating signal logic low level reading YSRL and gating signal logic high read between YSRH and can comprise many gating signal lines, and gating signal logic low level write YSWL and gating signal logic high write between YSWH and can comprise many gating signal lines.
As seen from Figure 3, writing and reading distinguished by the multiplexer in the present embodiment in gating signal.Thus, gating signal not only determines should carry out write/read operation to which array storage unit in memory cell array, also serves the effect assisting to distinguish writing and reading simultaneously.
In concrete enforcement, as shown in Figure 5, gating signal line for writing is connected with bit line by a nmos pass transistor, is then connected with bit line by a PMOS transistor for the gating signal line read, thus realizes the function that writing and reading are distinguished in above-mentioned assistance.
Be understandable that, the present invention is not limited only to above-described embodiment, if be connected with bit line by a PMOS transistor for the gating signal line write, and be connected with bit line by a nmos pass transistor for the gating signal line read, can realize equally distinguishing writing and reading.
With reference to the static RAM method for writing data process flow diagram shown in Fig. 4, be described in detail below by way of concrete steps:
S401, detects that a certain gating signal line is selected.
The address that usually can be exported according to central processing unit (CentralProcessingUnit, CPU) by address decoder, chooses a certain gating signal line.
Address decoder also can choose a wordline according to described address.The bit line of a wordline and a pair logical complement coordinates, corresponding to storage unit one or more in memory cell array.Number of memory cells corresponding to each address depends in this static RAM the imput output circuit having how many group parallel, for the static RAM that 4 groups of imput output circuits in Fig. 1 are parallel, one group address chooses the bit line of a wordline and a pair logical complement, corresponding to 4 storage unit.
Because writing and reading distinguished by the gating signal line in the present embodiment.Therefore, after detecting that a gating signal line is selected, the bit line of a pair logical complement can be corresponded on the one hand, (coordinate with wordline, jointly) determine and which storage unit in memory cell array should be write or read, also specify that the required operation performed is write or reads on the other hand.
S402, according to selected gating signal line, chooses the bit line corresponding with it.
Because each root gating signal line corresponds to the bit line of a pair logical complement.Therefore, after step S401, according to selected gating signal line, the bit line of a pair logical complement corresponding with it just and then can be chosen.
S403, turns off control circuit connecting line forward and the reverse precharge of control circuit connecting line.
In concrete enforcement, as shown in Figure 5 and Figure 8, in figure, the 7th PMOS P7, the 8th PMOS P8, these three PMOS transistor of the 9th PMOS P9 are used for carrying out precharge to control circuit connecting line forward DL and the reverse DLB of control circuit connecting line.
Above-mentioned three are subject to precharging signal PRCH and sense amplifier reverse enable signal SA_ENB management and control for PMOS transistor control circuit connecting line forward and control circuit connecting line being reversed to precharge.
S404, selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line reverse.
In write cycle time, gating signal logic low level write YSWL can be selected in abovementioned steps S401 to a certain in gating signal logic high write YSWH, and then in step S402, choose bit line logic low position BLL/BLBL to certain a pair in bit line logic high BLL/BLBL.
As shown in figure 5 and figure 7, selected gating signal write has a logical one pulse, nmos pass transistor between itself and the bit line of corresponding logical complement is opened, this is connected with the reverse DLB of control circuit connecting line with control circuit connecting line forward DL respectively to selected bit line.
For selected gating signal line for gating signal logic high write YSWH, the bit line of its correspondence is bit line logic high BLH/BLBH, 3rd NOS pipe N3 and the 4th NMOS tube N4 opens, thus bit line logic high forward BLH is connected with control circuit connecting line forward DL, the reverse BLBH of bit line logic high is connected with the reverse DLB of control circuit connecting line.
S405, receives data to be written from data input pin, and changes described control circuit connecting line forward or the reverse voltage of control circuit connecting line according to described data to be written.
As shown in figure 5 and figure 7, in write cycle time, input enable signal has a logical one pulse, 8th NMOS tube N8 and the 9th NMOS tube N9 is opened momently, voltage by the data input pin DI of its management and control can make the voltage of control circuit connecting line forward DL or the reverse DLB of control circuit connecting line change, thus realizes data to be written to write to control circuit connecting line forward DL and the reverse DLB of control circuit connecting line.
In concrete enforcement, as shown in Figure 5, after receiving data to be written, the voltage of data input pin DI can make the voltage of the single line in control circuit connecting line forward DL and the reverse DLB of control circuit connecting line change.Suppose using data input pin DI as logical zero, then data input pin DI can make the voltage of the single line in control circuit connecting line forward DL and the reverse DLB of control circuit connecting line drop-down.
It should be noted that, in this step, do not need control circuit connecting line forward DL or the reverse DLB of control circuit connecting line to pulled down to logical zero, only need the voltage difference between control circuit connecting line forward DL and the reverse DLB of control circuit connecting line can ensure sense amplifier work.
S406, by sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage.
It should be noted that: under extreme case, if write driver is enough strong, may occur that voltage difference between control circuit connecting line forward and control circuit connecting line are oppositely is without the situation before amplifying being supply voltage, now, sense amplifier keeps this voltage difference to be supply voltage.
As shown in Figure 5, typical sense amplifier composition structure comprises the 5th PMOS P5, the 6th PMOS P6, the 5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7 and relevant connecting line.Certainly, the present invention does not limit the concrete unitized construction of sense amplifier, as long as be subject to the management and control of sense amplifier enable signal, and functionally can after the voltage difference between control circuit connecting line forward DL and the reverse DLB of control circuit connecting line reaches certain threshold value, realize the voltage difference between control circuit connecting line forward DL and the reverse DLB of control circuit connecting line to be amplified to supply voltage.
Described sense amplifier is by sense amplifier enable signal SA_EN management and control, and described sense amplifier SA_EN enable signal is connected with the reverse enable signal SA_ENB of sense amplifier by a phase inverter.
If when high level effectively, then described sense amplifier reverse enable signal SA_ENB is effective when low level for described sense amplifier enable signal SA_EN; Otherwise if described sense amplifier enable signal SA_EN is effective when low level, then described sense amplifier reverse enable signal SA_ENB is effective when high level.
The signal that the reverse enable signal SA_ENB of sense amplifier exports is after phase inverter negate, and make described sense amplifier enable signal SA_EN effective, thus open the 7th NMOS tube N7, described sense amplifier is started working.
Be understandable that, in the read cycle, sense amplifier (adopt sense amplifier realize digital independent belong to prior art) can be used equally, therefore, above embodiments enable multiplexing in writing and reading process of sense amplifier.
In concrete enforcement, sense amplifier enable signal can be connected with the reverse enable signal of sense amplifier by a phase inverter, thus strengthens the driving force to sense amplifier.
The data that described sense amplifier exports, via described selected bit line, are write to the Destination Storage Unit in memory cell array by S407.
In the present embodiment, the signal that sense amplifier exports directly delivers to bit line, thus realizes the write of data.
In the above-described embodiments, the principle that imput output circuit realizes data write realizes data reading principle with it is similar.Below briefly introduce this imput output circuit and realize the flow process of reading for contrast: as shown in Figure 6, comprising:
S601, detects that a certain gating signal line is selected.
S602, according to selected gating signal line, chooses the bit line corresponding with it.
S603, turns off control circuit connecting line forward and the reverse precharge of control circuit connecting line.
S604, selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line reverse.
S605, selected storage unit changes described control circuit connecting line forward or the reverse voltage of control circuit connecting line via bit line.
S606, by sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage.
The data that described sense amplifier exports are exported by data output end by S607.
For write-then-read, assuming that choose bit line logic high BLH/BLBH during write cycle time, choose bit line logic low position BLL/BLBL during the read cycle, then write cycle time and the signal waveforms in the read cycle are as shown in Figure 7 (wherein, CK represents clock signal).
Can see, this imput output circuit is at write cycle time with in the read cycle, all first data are write to control circuit connecting line forward and control circuit connecting line is reverse, then by sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage, finally carried out write by the output of sense amplifier or read.That is, it is at write cycle time with in the read cycle, and in circuit, the reusability of each components and parts is very high, and thus both can adopt same circuit to realize.
And in the prior art, analyze as background technology part, not comprise sense amplifier in the write control circuit of prior art.And its write control circuit realizes the principle of write-in functions, and the principle that read-out control circuit realizes read out function is distinct, is thus difficult to be realized by same circuit.Even if combined artificially by this two parts circuit, they still just realize itself function separately, and in circuit, the reusability of each components and parts is low.
The above embodiment of the present invention is by the improvement to static RAM method for writing data, and make writing and reading can adopt same circuit to realize, in circuit, the reusability of each components and parts is higher, also reduces the space hold of imput output circuit simultaneously.Correspond on domain, especially for the less imput output circuit of multiplexing way, can effectively avoid it to be forced to increasing circuit height not because width.
In addition, in the above-described embodiments, write enable signal of the prior art is no longer needed in write cycle time, the output signal of sense amplifier is write direct Destination Storage Unit, data input pin is then by the management and control of input enable signal, namely eliminate write enable signal by input the multiplexing of enable signal, thus further reduce the space hold of circuit.
As described below, the embodiment of the present invention provides a kind of imput output circuit of static RAM.
With reference to the circuit structure diagram of the imput output circuit of the static RAM shown in Fig. 5, this imput output circuit comprises multiplexer and write read-out controller.
Wherein, described multiplexer connects the storage unit in the memory cell array of its management and control by the bit line of one or more pairs of logical complement, and bit line described in every a pair connects the gating signal line corresponding with it respectively, and writing and reading distinguished by described gating signal line;
Said write read-out controller comprises sense amplifier, data input pin DI and data output end DO; Described data input pin DI connection control circuit connecting wire forward DL and the reverse DLB of control circuit connecting line; Described sense amplifier is used for the voltage difference between control circuit connecting line forward DL and the reverse DLB of control circuit connecting line to be amplified to supply voltage;
Be connected with the reverse DLB of control circuit connecting line by control circuit connecting line forward DL between described multiplexer with said write read-out controller.
As shown in Figure 5, wherein, typical sense amplifier composition structure comprises the 5th PMOS P5, the 6th PMOS P6, the 5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7 and relevant connecting line.Certainly, the present invention does not limit the concrete unitized construction of sense amplifier, as long as be subject to the management and control of sense amplifier enable signal, and functionally can after the voltage difference between control circuit connecting line forward DL and the reverse DLB of control circuit connecting line reaches certain threshold value, realize the voltage difference between control circuit connecting line forward DL and the reverse DLB of control circuit connecting line to be amplified to supply voltage.
Can be found out by the above-mentioned description to technical scheme, this imput output circuit is in write cycle time, first data are write to control circuit connecting line forward and control circuit connecting line is reverse, then by sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage, finally carry out write by the output of sense amplifier or read, make the reusability of each components and parts in circuit in writing and reading process higher, thus writing and reading can adopt same circuit to realize, reduce the space hold of imput output circuit.
Correspond on domain, especially for the less imput output circuit of multiplexing way, can effectively avoid it to be forced to increasing circuit height not because width.
Simultaneously, write enable signal of the prior art is no longer needed in write cycle time, the output signal of sense amplifier is write direct Destination Storage Unit, data input pin is then by the management and control of input enable signal, namely eliminate write enable signal by input the multiplexing of enable signal, thus further reduce the space hold of circuit.
In concrete enforcement, described gating signal line distinguishes writing and reading specifically: the gating signal line for writing is connected with described bit line by a nmos pass transistor, and be connected with described bit line by a PMOS transistor for the gating signal line read, and be connected with described bit line by a nmos pass transistor for the gating signal line read.
Can be found out by the above-mentioned description to technical scheme, writing and reading distinguished by the multiplexer in the present embodiment in gating signal.Thus, gating signal not only determines should carry out write/read operation to which array storage unit in memory cell array, also serves the effect assisting to distinguish writing and reading simultaneously.
In concrete enforcement, described sense amplifier is by the management and control of sense amplifier enable signal, and described sense amplifier enable signal is connected with the reverse enable signal of sense amplifier by a phase inverter; Described sense amplifier enable signal is effective when high level, and the reverse enable signal of described sense amplifier is effective when low level, or described sense amplifier enable signal is effective when low level, and the reverse enable signal of described sense amplifier is effective when high level.
In above-described embodiment, sense amplifier enable signal is connected with the reverse enable signal of sense amplifier by a phase inverter, the driving force to sense amplifier can be strengthened.
In concrete enforcement, said write read-out control unit also comprises: for being reversed the precharge unit of precharge to described control circuit connecting line forward and control circuit connecting line, and described precharge unit is by precharging signal and the reverse enable signal management and control of sense amplifier.
In concrete enforcement, described gating signal line link address code translator.
In concrete enforcement, described data input pin, by the management and control of input enable signal, when described input enable signal is effective, receives data to be written from data receiver.
As described below, the embodiment of the present invention provides a kind of static RAM.
Described static RAM comprises: memory cell array, address decoder, overall control circuit and one or more imput output circuit.
Be with the difference of prior art, imput output circuit in this static RAM adopt as in previous embodiment of the present invention the imput output circuit of static RAM that provides.This static RAM is in write cycle time, first data are write to control circuit connecting line forward and control circuit connecting line is reverse, then by sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage, finally carry out write by the output of sense amplifier or read, make the reusability of each components and parts in circuit in writing and reading process higher, thus writing and reading can adopt same circuit to realize, therefore, the shared in terms of existing technologies space of its imput output circuit and even whole static RAM is less.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a static RAM method for writing data, is characterized in that, comprising:
Detect that a certain gating signal line is selected, described gating signal line corresponds to the bit line of a pair logical complement, and writing and reading distinguished by described gating signal line;
According to selected gating signal line, choose the bit line corresponding with it;
Selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line reverse;
Receive data to be written from data input pin, and change described control circuit connecting line forward or the reverse voltage of control circuit connecting line according to described data to be written;
By sense amplifier by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage;
Via described selected bit line, the data that described sense amplifier exports are write to the Destination Storage Unit in memory cell array.
2. static RAM method for writing data as claimed in claim 1, it is characterized in that, described gating signal line distinguishes writing and reading specifically: the gating signal line for writing is connected with described bit line by a nmos pass transistor, and is connected with described bit line by a PMOS transistor for the gating signal line read.
3. static RAM method for writing data as claimed in claim 1, it is characterized in that, described sense amplifier is by the management and control of sense amplifier enable signal, and described sense amplifier enable signal is connected with the reverse enable signal of sense amplifier by a phase inverter; Described to change described control circuit connecting line forward or the reverse voltage of control circuit connecting line according to described data to be written after, the signal that the reverse enable signal of sense amplifier exports is after phase inverter negate, make described sense amplifier enable signal effective, described sense amplifier is started working.
4. static RAM method for writing data as claimed in claim 3, it is characterized in that, described sense amplifier enable signal is effective when high level, and the reverse enable signal of described sense amplifier is effective when low level, or described sense amplifier enable signal is effective when low level, and the reverse enable signal of described sense amplifier is effective when high level.
5. static RAM method for writing data as claimed in claim 1, it is characterized in that, described selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line oppositely before, by precharging signal and the reverse enable signal management and control of sense amplifier, turn off control circuit connecting line forward and the reverse precharge of control circuit connecting line.
6. static RAM method for writing data as claimed in claim 1, is characterized in that, the address that address decoder receives according to it, chooses a certain gating signal line.
7. static RAM method for writing data as claimed in claim 1, it is characterized in that, described data input pin is by the management and control of input enable signal, described selected bit line respectively connection control circuit connecting wire forward and control circuit connecting line oppositely after, described input enable signal is effective, and receives data to be written from data input pin.
8. an imput output circuit for static RAM, is characterized in that, comprising: multiplexer and write read-out controller; Wherein,
Described multiplexer connects the storage unit in the memory cell array of its management and control by the bit line of one or more pairs of logical complement, bit line described in every a pair connects the gating signal line corresponding with it respectively, and writing and reading distinguished by described gating signal line;
Said write read-out controller comprises sense amplifier, data input pin and data output end; Described data input pin connection control circuit connecting wire forward and control circuit connecting line reverse; Described sense amplifier be used for by control circuit connecting line forward and control circuit connecting line oppositely between voltage difference be amplified to supply voltage;
Oppositely be connected with control circuit connecting line by control circuit connecting line forward between described multiplexer with said write read-out controller.
9. the imput output circuit of a kind of static RAM as claimed in claim 8, it is characterized in that, described gating signal line distinguishes writing and reading specifically: the gating signal line for writing is connected with described bit line by a nmos pass transistor, and is connected with described bit line by a PMOS transistor for the gating signal line read.
10. the imput output circuit of a kind of static RAM as claimed in claim 8, it is characterized in that, described sense amplifier is by the management and control of sense amplifier enable signal, and described sense amplifier enable signal is connected with the reverse enable signal of sense amplifier by a phase inverter; Described sense amplifier enable signal is effective when high level, and the reverse enable signal of described sense amplifier is effective when low level, or described sense amplifier enable signal is effective when low level, and the reverse enable signal of described sense amplifier is effective when high level.
The imput output circuit of 11. a kind of static RAM as claimed in claim 8, it is characterized in that, said write read-out control unit also comprises: for being reversed the precharge unit of precharge to described control circuit connecting line forward and control circuit connecting line, and described precharge unit is by precharging signal and the reverse enable signal management and control of sense amplifier.
The imput output circuit of 12. a kind of static RAM as claimed in claim 8, is characterized in that, described gating signal line link address code translator.
The imput output circuit of 13. a kind of static RAM as claimed in claim 8, is characterized in that, described data input pin, by the management and control of input enable signal, when described input enable signal is effective, receives data to be written from data receiver.
14. 1 kinds of static RAM, comprising: memory cell array and address decoder, is characterized in that, also comprise the imput output circuit of one or more static RAM according to any one of claim 8 to 13.
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| CN105448329B (en) | 2018-08-21 |
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