CN105448329B - Static RAM and its method for writing data, imput output circuit - Google Patents
Static RAM and its method for writing data, imput output circuit Download PDFInfo
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- CN105448329B CN105448329B CN201410308928.6A CN201410308928A CN105448329B CN 105448329 B CN105448329 B CN 105448329B CN 201410308928 A CN201410308928 A CN 201410308928A CN 105448329 B CN105448329 B CN 105448329B
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Abstract
A kind of Static RAM and its method for writing data, imput output circuit, the method includes：Detect that a certain gating signal line is selected, the gating signal line is distinguished write-in and read；According to selected gating signal line, corresponding bit line is chosen；Selected bit line is separately connected control circuit connecting line forward direction and control circuit connecting line is reversed；Change the voltage that the control circuit connecting line is positive or control circuit connecting line is reversed according to data to be written；The voltage difference of control circuit connecting line forward direction and control circuit connecting line between reversed is amplified to supply voltage by sense amplifier；Via the selected bit line, the data that the sense amplifier exports are written to the Destination Storage Unit into memory cell array.The reusability higher with each component in circuit in readout is being written in the present invention, to which same circuit may be used to realize in write-in and reading, reduces the space hold of imput output circuit.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of Static RAM and its data write-in side
Method, imput output circuit.
Background technology
Random access memory (Random Access Memory, RAM) can be divided into Static RAM (Static
Random Access Memory, SRAM) and dynamic RAM (Dynamic Random Access Memory,
DRAM).Wherein, as long as Static RAM remains powered on the data for preserving its storage inside, without carrying out the period
Property update, and be written and reading speed it is more faster than dynamic RAM.But its integrated level is relatively low, each dynamic
The storage unit of random access memory only needs a transistor and a small capacitances, and the storage list of each Static RAM
It is first then need two to ten transistors (mainstream is six or eight) some additional interlock circuits.Therefore, in the identical feelings of capacity
Under condition, Static RAM would generally occupy more spaces than dynamic RAM.How static random storage is reduced
The space hold of device is always a problem of memory or even integrated circuit fields.
As shown in Figure 1, Static RAM include memory cell array, address decoder, global control circuit and
One or more input and output (input/output, IO) circuits.
In Static RAM, line up around the memory cell array of matrix form be itself and external signal interface
Circuit, including orthogonal wordline and bit line, by taking Fig. 1 as an example, the line of horizontal direction is wordline, and the line of vertical direction is
It is single that the infall of bit line, each wordline and the bit line per a pair of of logical complement is directed toward a storage in memory cell array
Member.Each storage unit in the memory cell array of each imput output circuit institute management and control both corresponds to a group address, and
Each group address can correspond to one or more storage units and (depend on the number of imput output circuit in the Static RAM
Amount).
May include the imput output circuit of multi-set parallel, each group of imput output circuit in one Static RAM
The capacity of a part for management and control memory cell array, management and control is determined by number of word lines and the multiplexing way of the imput output circuit
It is fixed.By taking Fig. 1 as an example, including 8 parallel wordline (WL0 to WL7), each group of imput output circuit management and control 4 is to logical complement
Bit line (it is 4 to be multiplexed way), then the capacity of each group of imput output circuit management and control is 32 bits (bit).
In the prior art, imput output circuit generally includes three parts：Multiplexer, write control circuit and reading control
Circuit processed.The major function of three parts is as follows：
By the multiplexer of management and control, for selecting and cutting off the bit line of the logical complement in memory cell array to write-in
The connection of control circuit/read-out control circuit, determining should be to the array storage unit of which in memory cell array into row write
Enter/read operation；
Write control circuit is used for management and control data input pin (Data-in, DI), and provides driving and write data into and deposit
Storage unit array；
Read-out control circuit includes mainly sense amplifier, is used to amplify the voltage difference of the bit line of logical complement and defeated
Go out data.
As shown in Fig. 2, for the mainstay framework of the imput output circuit of Static RAM in the prior art.In figure
Each port meaning is as follows：
YSL --- gating signal logic low level, YSH --- gating signal logic high,
BLL/BLBL --- bit line logic low level, BLH/BLBH --- bit line logic high,
WBL/WBLB --- write circuit connecting line, RBL/RBLB --- reading circuit connecting line,
DI --- data input pin, DO --- data output end,
PRCH --- precharging signal, IN_EN --- input enable signal,
WEN --- write enable signal, SA_EN --- sense amplifier enable signal.
It should be noted that can include more between bit line logic low level BLL/BLBL and bit line logic high BLH/BLBH
To the bit line of logical complement, bit line corresponds to a storage unit in memory cell array, bit line with each wordline cooperation
Logarithm depend on multiplexer multiplexing way (while being also equal to the multiplexing way of the imput output circuit), such as
Four path multiplexer (MUX4) employed in figure 1, then include the bit line of 4 pairs of logical complements, for eight path multiplexers (MUX8), then
The bit line for including 8 pairs of logical complements then includes the bit line of 16 pairs of logical complements, with such for 16 path multiplexers (MUX16)
It pushes away.
Correspondingly, can also include more gatings between gating signal logic low level YSL and gating signal logic high YSH
Signal wire, and each gating signal line corresponds to the bit line of a pair of of logical complement.
Wherein：
Multiplexer is by one in gating signal logic low level YSL to gating signal logic high YSH, from bit line
The bit line that a pair of of logical complement is chosen in logic low level BLL/BLBL to bit line logic high BLH/BLBH, is connected to write circuit
Connecting line WBL/WBLB or reading circuit connecting line RBL/RBLB；
It in write cycle time, writes and enables effectively, data to be written are received from data input pin DI, and be written into write-in electricity
The voltage of single line in road connecting line WBL/WBLB, write circuit connecting line WBL/WBLB changes, and by multiplexer, makes
The voltage for obtaining a bit line in the bit line of a pair of of logical complement also changes correspondingly, and finally overturns in memory cell array and be chosen
In storage unit, to realize write operation；
In the read cycle, the bit line of a pair of logical complement corresponding with Destination Storage Unit is selected, and and reading circuit
Connecting line RBL/RBLB is connected, and the logical zero or logic 1 that Destination Storage Unit is stored can make reading circuit connecting line RBL/
The voltage of single line in RBLB changes, and sense amplifier enable signal SA_EN is effective, by reading circuit connecting line both threads it
Between voltage difference amplification, and finally data are exported by data output end DO.
In the imput output circuit framework of above-mentioned Static RAM, the write control circuit of imput output circuit and
Read-out control circuit is independent two parts.And the imput output circuit realizes the principle of write-in functions, and realizes and read work(
The principle of energy is completely different, and the signal that sense amplifier exports especially in the read cycle is directly defeated by data output end
Go out, and the signal that sense amplifier exports not then is directly sent to bit line in write cycle time and realizes write-in, or even is controlled in write-in
It not include sense amplifier in circuit processed.As previously described, because the imput output circuit realizes the principle of write-in functions,
Principle with realization read out function is completely different, therefore, is also just difficult to melt write control circuit and read-out control circuit
It is combined into an entirety.
In addition, the structure of Static RAM is corresponded on domain, from figure 1 it appears that imput output circuit
It can be limited on the width by memory cell array size itself.Specifically, in order to avoid the input and output for occupying periphery are electric
The wiring space on road, therefore, imput output circuit is on the width no more than the width of the memory cell array of its management and control.
Specific to each component part in imput output circuit, as previously mentioned, imput output circuit is usual in the prior art
Including：Multiplexer, write control circuit and read-out control circuit three parts.Wherein, the width of multiplexer can be with
It is multiplexed the variation of way and changes, and specifically, the multiplexing way of multiplexer is more, then the memory cell array of its management and control
Also wider, vice versa.That is, the width of multiplexer can be with the width synchronization of the memory cell array of its management and control
Increase, synchronous reduction.Therefore, the limitation on above-mentioned width is easier to meet for multiplexer.
But the size of write control circuit and read-out control circuit can't change with the variation of multiplexing way.
No matter the multiplexing way of the imput output circuit is how many, and no matter the width of the memory cell array of its management and control is how many, write-in
Control circuit and the size of read-out control circuit do not have significant change.
For these reasons, for the less imput output circuit of multiplexing way, such as multiplexing way is 2 even
When 1, even only there are one the width of storage unit to accommodate write control circuit and reading control for storage unit there are two
Circuit.At this point, the wiring space of the imput output circuit in order to avoid occupying periphery, can only be forced to increase the height of circuit, most
The height of entire Static RAM is caused to increase eventually.
Invention content
Present invention solves the technical problem that being：How by the write control circuit of imput output circuit in the prior art and reading
The function of going out control circuit is realized by same circuit.
To solve the above-mentioned problems, the embodiment of the present invention provides a kind of Static RAM method for writing data, including：
Detecting that a certain gating signal line is selected, the gating signal line corresponds to the bit line of a pair of of logical complement,
The gating signal line is distinguished write-in and is read；
According to selected gating signal line, corresponding bit line is chosen；
Selected bit line is separately connected control circuit connecting line forward direction and control circuit connecting line is reversed；
Data to be written are received from data input pin, and change the control circuit connecting line according to the data to be written
Positive or reversed control circuit connecting line voltage；
The voltage difference of control circuit connecting line forward direction and control circuit connecting line between reversed is put by sense amplifier
Greatly to supply voltage；
Via the selected bit line, the data that the sense amplifier exports are written into memory cell array
Destination Storage Unit.
Optionally, the gating signal line distinguishes write-in and reading is specifically：Gating signal line for write-in passes through one
A NMOS transistor is connected with the bit line, and the gating signal line for reading passes through a PMOS transistor and the bit line
It is connected.
Optionally, the sense amplifier is by sense amplifier enable signal management and control, the sense amplifier enable signal
It is connected with the reversed enable signal of sense amplifier by a phase inverter；Change the control according to the data to be written described
After the voltage that circuit connecting wire processed is positive or control circuit connecting line is reversed, the letter of the reversed enable signal output of sense amplifier
After number negating by phase inverter so that the sense amplifier enable signal is effective, and the sense amplifier is started to work.
Optionally, the sense amplifier enable signal is effective in high level, and the sense amplifier reversely enables
Signal is effective in low level or the sense amplifier enable signal is effective in low level, and the sensitive amplification
The reversed enable signal of device is effective in high level.
Optionally, it is separately connected control circuit connecting line forward direction in the selected bit line and control circuit connecting line is anti-
To before, by precharging signal and the reversed enable signal management and control of sense amplifier, shutdown is positive to control circuit connecting line and controls
The reversed precharge of circuit connecting wire processed.
Optionally, address decoder is according to received address, to choose a certain gating signal line.
Optionally, the data input pin is separately connected control by input enable signal management and control in the selected bit line
After circuit connecting wire forward direction processed and control circuit connecting line are reversed, the input enable signal is effective, and from data input pin
Receive data to be written.
In order to solve the above-mentioned technical problem, the embodiment of the present invention also provides a kind of input and output electricity of Static RAM
Road, including：Multiplexer and write-in read-out controller；Wherein,
The multiplexer is connected by the bit line of one or more pairs of logical complements in the memory cell array of its management and control
Storage unit, be separately connected corresponding gating signal line per a pair of bit line, the gating signal line distinguishes write-in
And reading；
Said write read-out controller includes sense amplifier, data input pin and data output end；The data input
End connection control circuit connecting line forward direction and control circuit connecting line are reversed；The sense amplifier is for connecting control circuit
Voltage difference between line forward direction and control circuit connecting line are reversed is amplified to supply voltage；
Pass through control circuit connecting line forward direction and control electricity between the multiplexer and said write read-out controller
Road connecting line is reversely connected.
Optionally, the gating signal line distinguishes write-in and reading is specifically：Gating signal line for write-in passes through one
A NMOS transistor is connected with the bit line, and the gating signal line for reading passes through a PMOS transistor and the bit line
It is connected.
Optionally, the sense amplifier is by sense amplifier enable signal management and control, the sense amplifier enable signal
It is connected with the reversed enable signal of sense amplifier by a phase inverter；The sense amplifier enable signal has in high level
Effect, and the reversed enable signal of the sense amplifier is effective in low level or the sense amplifier enable signal exists
It is effective when low level, and the reversed enable signal of the sense amplifier is effective in high level.
Optionally, said write read-out control unit further includes：For to control circuit connecting line forward direction and control
Circuit connecting wire is reversed the precharge unit of precharge, and the precharge unit is anti-by precharging signal and sense amplifier
To enable signal management and control.
Optionally, the gating signal line link address decoder.
Optionally, the data input pin is by input enable signal management and control, when the input enable signal is effective, from number
Data to be written are received according to receiving terminal.
In order to solve the above-mentioned technical problem, the embodiment of the present invention also provides a kind of Static RAM, including：Storage is single
Element array and address decoder further include above-mentioned imput output circuit.
Compared with prior art, technical scheme of the present invention has the advantages that：
The present invention first writes data into anti-to control circuit connecting line forward direction and control circuit connecting line in write cycle time
To the then voltage difference amplification by sense amplifier by control circuit connecting line forward direction and control circuit connecting line between reversed
To supply voltage, is finally completed to be written or be read by the output of sense amplifier so that in write-in and readout in circuit
The reusability higher of each component reduces imput output circuit to which same circuit may be used to realize in write-in and reading
Space hold.
Further, it corresponds on domain, for the less imput output circuit of multiplexing way, Neng Gouyou
Effect avoids it from being forced increasing circuit height because width is inadequate.
Further, write enable signal in the prior art, the output signal of sense amplifier are no longer needed in write cycle time
Write direct Destination Storage Unit, and data input pin is then by input enable signal management and control, i.e., by inputting answering for enable signal
With write enable signal is eliminated, to further reduce the space hold of circuit.
Further, the gating signal line for being used for write-in is connected by a NMOS transistor with the bit line, and is used for
The gating signal line of reading is connected by a PMOS transistor with the bit line, to realize through the areas gating signal Xian Lai
Divide write-in and reads.
Further, the sense amplifier enable signal passes through a phase inverter and the reversed enable signal of sense amplifier
It is connected, strengthens the driving capability to sense amplifier, and realizes sense amplifier and be written and the multiplexing in readout.
Description of the drawings
Fig. 1 is Static RAM structure diagram；
Fig. 2 is the inputting and outputting circuit structure block diagram of Static RAM in the prior art；
Fig. 3 is the inputting and outputting circuit structure block diagram of Static RAM in the embodiment of the present invention；
Fig. 4 is Static RAM method for writing data flow chart in the embodiment of the present invention；
Fig. 5 is the circuit structure diagram of the imput output circuit of Static RAM in the embodiment of the present invention；
Fig. 6 is Static RAM data read method flow chart in the embodiment of the present invention；
Fig. 7 is letter of the imput output circuit of Static RAM in the embodiment of the present invention in write cycle time and read cycle
Number oscillogram；
Fig. 8 is the circuit structure of another embodiment of imput output circuit of Static RAM in the embodiment of the present invention
Figure.
Specific implementation mode
According to the analysis of background technology part it is found that in the prior art in the imput output circuit of Static RAM,
Write control circuit and read-out control circuit are independent two parts.And the imput output circuit realizes the original of write-in functions
Reason, and realize that the principle of read out function is completely different.Therefore, it is also just difficult to write control circuit and read-out control circuit
Permeate entirety.
Since the size of write control circuit and read-out control circuit can't be multiplexed road with the Static RAM
Several variation and change, therefore, for the less imput output circuit of multiplexing way, correspond on domain, only there are two
Even only there are one the width of storage unit to accommodate write control circuit and read-out control circuit for storage unit.At this point, being
The wiring space for avoiding occupying the imput output circuit on periphery can only be forced to increase the height of circuit, eventually lead to entire quiet
The height of state random access memory increases.
For the drawbacks described above of the prior art, inventor to the structure of the imput output circuit of Static RAM and its
Method for writing data is improved so that same circuit may be used in the function of write control circuit and read-out control circuit
It completes.Write control circuit and the occupied space of read-out control circuit are also significantly reduced simultaneously, especially on the width not
It is easy the width of the memory cell array beyond its management and control.
To make those skilled in the art more fully understand and realizing the present invention, referring to the drawings, pass through specific embodiment
It is described in detail.
As described below, the embodiment of the present invention provides a kind of Static RAM method for writing data.
First, the realization of the method for writing data needs to be written and read to assist to distinguish by multiplexer.
With reference to the inputting and outputting circuit structure block diagram of Static RAM shown in Fig. 3, each port meaning is as follows in figure：
YSRL --- gating signal logic low level is read,
YSRH --- gating signal logic high is read,
YSWL --- gating signal logic low level is written,
YSWH --- gating signal logic high is written,
BLL/BLBL --- bit line logic low level, BLH/BLBH --- bit line logic high,
DL --- control circuit connecting line is positive, and DLB --- control circuit connecting line is reversed,
DI --- data input pin, DO --- data output end,
PRCH --- precharging signal, IN_EN --- input enable signal, SA_EN --- sense amplifier enable signal.
It should be noted that can include more between bit line logic low level BLL/BLBL and bit line logic high BLH/BLBH
To the bit line of logical complement, gating signal logic low level reads and can be wrapped between YSRL and gating signal logic high reading YSRH
More gating signal lines are included, can be wrapped between gating signal logic low level write-in YSWL and gating signal logic high write-in YSWH
Include more gating signal lines.
As seen from Figure 3, the multiplexer in the present embodiment has been distinguished write-in and has been read in gating signal.By
This, gating signal, which not only determines, to carry out write/read operation to the array storage unit of which in memory cell array,
The effect for assisting to distinguish write-in and read is also acted simultaneously.
In specific implementation, as shown in figure 5, the gating signal line for write-in passes through a NMOS transistor and bit line phase
Even, the gating signal line for being used to read then is connected by a PMOS transistor with bit line, to realize that above-mentioned assistance is distinguished
Write-in and the function of reading.
It is understood that the present invention is not limited only to above-described embodiment, if the gating signal line for write-in is logical
A PMOS transistor is crossed with bit line to be connected, and the gating signal line for being used to read passes through a NMOS transistor and bit line phase
Even, it equally may be implemented to distinguish write-in and read.
With reference to Static RAM method for writing data flow chart shown in Fig. 4, carried out below by way of specific steps detailed
It describes in detail bright：
S401 detects that a certain gating signal line is selected.
It can usually be exported according to central processing unit (Central Processing Unit, CPU) by address decoder
Address, to choose a certain gating signal line.
Address decoder can also choose a wordline according to described address.The bit line of a piece wordline and a pair of of logical complement
Cooperation corresponds to one or more storage units in memory cell array.The corresponding number of memory cells in each address depends on
How many organizes parallel imput output circuit in the Static RAM, with the parallel static state of 4 groups of imput output circuits in Fig. 1
For random access memory, a group address chooses the bit line of a wordline and a pair of of logical complement, corresponds to 4 storage units.
Write-in is distinguished by gating signal line in this present embodiment and is read.Therefore, a gating signal line is being detected
After selected, the bit line of a pair of of logical complement is on the one hand can correspond to, (coordinating with wordline, common) determines should be to storage
Which of cell array storage unit is written or is read, and on the other hand also specifies that the required operation executed is that write-in is gone back
It is to read.
S402 chooses corresponding bit line according to selected gating signal line.
Since each gating signal line corresponds to the bit line of a pair of of logical complement.Therefore, after step S401, according to
Selected gating signal line, so that it may to choose the bit line of corresponding a pair of of logical complement in turn.
S403 turns off the precharge reversed to control circuit connecting line forward direction and control circuit connecting line.
In specific implementation, as shown in Figure 5 and Figure 8, the 7th PMOS tube P7, the 8th PMOS tube P8, the 9th PMOS tube in figure
These three PMOS transistors of P9 are used to carry out preliminary filling to control circuit connecting line forward direction DL and the reversed DLB of control circuit connecting line
Electricity.
Above three is used for the PMOS that and control circuit connecting line positive to control circuit connecting line is reversed precharge
Transistor is by precharging signal PRCH and the reversed enable signal SA_ENB management and control of sense amplifier.
S404, selected bit line is separately connected control circuit connecting line forward direction and control circuit connecting line is reversed.
In write cycle time, gating signal logic low level is written a certain in YSWL to gating signal logic high write-in YSWH
Root can be selected in abovementioned steps S401, and then choose bit line logic low position BLL/BLBL to bit line logic in step S402
Certain in high-order BLL/BLBL is a pair of.
As shown in figure 5 and figure 7, the write-in of selected gating signal can there are one 1 pulses of logic, by itself and corresponding logic
NMOS transistor between complementary bit line is opened so that this to selected bit line respectively with control circuit connecting line forward direction DL
It is connected with the reversed DLB of control circuit connecting line.
It is for YSWH is written in gating signal logic high by selected gating signal line, corresponding bit line is patrolled for bit line
It collects a high position BLH/BLBH, the 3rd NOS pipes N3 and the 4th NMOS tube N4 is opened, to which bit line logic high forward direction BLH is electric with control
Road connecting line forward direction DL is connected, and the reversed BLBH of bit line logic high is connected with the reversed DLB of control circuit connecting line.
S405 receives data to be written from data input pin, and changes the control circuit according to the data to be written
The voltage that connecting line is positive or control circuit connecting line is reversed.
As shown in figure 5 and figure 7, in write cycle time, there are one 1 pulses of logic for input enable signal so that the 8th NMOS tube
N8 and the 9th NMOS tube N9 are briefly opened, and can made control circuit connecting line just by the voltage of the data input pin DI of its management and control
It changes to the voltage of DL or the reversed DLB of control circuit connecting line, to realize that being written into data is written to control circuit
The connecting line forward direction DL and reversed DLB of control circuit connecting line.
In specific implementation, as shown in figure 5, after receiving data to be written, the voltage of data input pin DI can make
The voltage for obtaining control circuit connecting line forward direction DL and the single line in the reversed DLB of control circuit connecting line changes.Assuming that with data
Input terminal DI can make control circuit connecting line forward direction DL and control circuit connecting line anti-as logical zero, then data input pin DI
The voltage of single line into DLB is pulled down.
It should be noted that in the step, does not need to control circuit connecting line forward direction DL or control circuit connecting line is anti-
It pulled down to logical zero to DLB, it is only necessary to the electricity between control circuit connecting line forward direction DL and the reversed DLB of control circuit connecting line
Pressure difference can ensure that sense amplifier works.
S406, the voltage by sense amplifier by control circuit connecting line forward direction and control circuit connecting line between reversed
Difference is amplified to supply voltage.
It should be noted that：Under extreme case, if write driver is sufficiently strong, it is possible that control circuit connecting line is just
To and control circuit connecting line it is reversed between voltage difference without amplification before be supply voltage the case where, at this point, sensitive
It is supply voltage that amplifier, which keeps the voltage difference,.
As shown in figure 5, typical sense amplifier composed structure includes the 5th PMOS tube P5, the 6th PMOS tube P6, the 5th
NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7 and relevant connecting line.Certainly, the present invention does not limit sensitive amplification
The specific composite structure of device, as long as by sense amplifier enable signal management and control, and can functionally connect in control circuit
After voltage difference between wiring forward direction DL and the reversed DLB of control circuit connecting line reaches certain threshold value, realization connects control circuit
Voltage difference between wiring forward direction DL and the reversed DLB of control circuit connecting line is amplified to supply voltage.
The sense amplifier is by sense amplifier enable signal SA_EN management and control, the enabled letters of the sense amplifier SA_EN
Number it is connected with the reversed enable signal SA_ENB of sense amplifier by a phase inverter.
If the sense amplifier enable signal SA_EN is effective in high level, then the sense amplifier reversely makes
Energy signal SA_ENB is effective in low level；If conversely, the sense amplifier enable signal SA_EN has in low level
Effect, then the reversed enable signal SA_ENB of the sense amplifier is effective in high level.
After the signal of the reversed enable signal SA_ENB outputs of sense amplifier is negated by phase inverter so that described sensitive
Amplifier enable signal SA_EN is effective, and to open the 7th NMOS tube N7, the sense amplifier is started to work.
It is understood that can equally use sense amplifier in the read cycle (realizes that data are read using sense amplifier
Take and belong to the prior art), therefore, above example implements sense amplifiers to be written and the multiplexing in readout.
In specific implementation, sense amplifier enable signal can reversely be enabled by a phase inverter with sense amplifier
Signal is connected, to reinforce the driving capability to sense amplifier.
The data that the sense amplifier exports are written to storage unit battle array via the selected bit line by S407
Destination Storage Unit in row.
In the present embodiment, the signal of sense amplifier output is directly sent to bit line, to realize the write-in of data.
In the above-described embodiments, imput output circuit realizes that the principle of data write-in realizes that the principle that data are read is with it
Similar.Introducing the imput output circuit briefly below realizes the flow read for control：As shown in fig. 6, including：
S601 detects that a certain gating signal line is selected.
S602 chooses corresponding bit line according to selected gating signal line.
S603 turns off the precharge reversed to control circuit connecting line forward direction and control circuit connecting line.
S604, selected bit line is separately connected control circuit connecting line forward direction and control circuit connecting line is reversed.
S605, selected storage unit changes the control circuit connecting line forward direction via bit line or control circuit connects
The reversed voltage of line.
S606, the voltage by sense amplifier by control circuit connecting line forward direction and control circuit connecting line between reversed
Difference is amplified to supply voltage.
S607 exports the data that the sense amplifier exports by data output end.
By taking write-then-read as an example, it is assumed that choose bit line logic high BLH/BLBH when write cycle time, when read cycle chooses bit line
Logic low level BLL/BLBL, then (wherein, CK indicates clock letter to the signal waveforms in write cycle time and read cycle as shown in Figure 7
Number).
It can be seen that the imput output circuit in write cycle time and read cycle, is first write data into control circuit
Connecting line forward direction and control circuit connecting line are reversed, then by sense amplifier that control circuit connecting line forward direction and control is electric
Voltage difference between road connecting line is reversed is amplified to supply voltage, is finally completed to be written or be read by the output of sense amplifier
Go out.That is, it in write cycle time and read cycle, the reusability of each component is very high in circuit, thus the two may be used
Same circuit is realized.
And in the prior art, it is basic in the write control circuit of the prior art as background technology part is analyzed
It does not include just sense amplifier.And its write control circuit is realized that the principle of write-in functions and read-out control circuit are realized and is read
The principle for going out function is completely different, thus is difficult to realize by same circuit.It is even that this two parts circuit is artificial
Ground merges, they are still respectively to realize the function of itself, and the reusability of each component is low in circuit.
The above embodiment of the present invention passes through the improvement to Static RAM method for writing data so that write-in and reading
Same circuit may be used to realize, the reusability higher of each component in circuit, while also reducing imput output circuit
Space hold.It corresponds on domain, for the less imput output circuit of multiplexing way, can effectively avoid it
It is forced increasing circuit height because width is inadequate.
In addition, in the above-described embodiments, write enable signal in the prior art, sense amplifier are no longer needed in write cycle time
Output signal write direct Destination Storage Unit, and data input pin is made then by input enable signal management and control by input
The multiplexing of energy signal eliminates write enable signal, to further reduce the space hold of circuit.
As described below, the embodiment of the present invention provides a kind of imput output circuit of Static RAM.
The circuit structure diagram of the imput output circuit of Static RAM referring to Figure 5, the imput output circuit
Including multiplexer and write-in read-out controller.
Wherein, the multiplexer connects the storage unit battle array of its management and control by the bit line of one or more pairs of logical complements
Storage unit in row is separately connected corresponding gating signal line per a pair of bit line, and the gating signal line is distinguished
Write-in and reading；
Said write read-out controller includes sense amplifier, data input pin DI and data output end DO；The data
Input terminal DI connection control circuit connecting line forward direction DL and the reversed DLB of control circuit connecting line；The sense amplifier is used for will
Voltage difference between control circuit connecting line forward direction DL and the reversed DLB of control circuit connecting line is amplified to supply voltage；
Pass through control circuit connecting line forward direction DL and control between the multiplexer and said write read-out controller
The reversed DLB of circuit connecting wire is connected.
As shown in Figure 5, wherein typical sense amplifier composed structure include the 5th PMOS tube P5, the 6th PMOS tube P6,
5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7 and relevant connecting line.Certainly, the present invention does not limit sensitive
The specific composite structure of amplifier, as long as by sense amplifier enable signal management and control, and functionally can be in control electricity
After voltage difference between road connecting line forward direction DL and the reversed DLB of control circuit connecting line reaches certain threshold value, realizing will control electricity
Voltage difference between road connecting line forward direction DL and the reversed DLB of control circuit connecting line is amplified to supply voltage.
The imput output circuit is can be seen that in write cycle time by the above-mentioned description to technical solution, first writes data
Enter it is reversed to control circuit connecting line forward direction and control circuit connecting line, then by sense amplifier by control circuit connecting line
Voltage difference between positive and control circuit connecting line is reversed is amplified to supply voltage, finally by the output of sense amplifier Lai complete
At write-in or reading so that the reusability higher of write-in and each component in circuit in readout, to which write-in and reading can
To be realized using same circuit, the space hold of imput output circuit is reduced.
It corresponds on domain, for the less imput output circuit of multiplexing way, can effectively avoid it
It is forced increasing circuit height because width is inadequate.
Meanwhile write enable signal in the prior art is no longer needed in write cycle time, the output signal of sense amplifier is direct
Destination Storage Unit is written, and data input pin is saved then by input enable signal management and control by inputting the multiplexing of enable signal
Write enable signal is removed, to further reduce the space hold of circuit.
In specific implementation, the gating signal line distinguishes write-in and reading is specifically：Gating signal line for write-in
It is connected with the bit line by a NMOS transistor, and the gating signal line for reading passes through a PMOS transistor and institute
Rheme line is connected, and the gating signal line for reading is connected by a NMOS transistor with the bit line.
By the above-mentioned description to technical solution as can be seen that the area in gating signal of the multiplexer in the present embodiment
Write-in is divided and has read.Not only determine should be to the array storage unit of which in memory cell array for gating signal as a result,
Write/read operation is carried out, while also acting the effect for assisting to distinguish write-in and read.
In specific implementation, the sense amplifier is made by sense amplifier enable signal management and control, the sense amplifier
Energy signal is connected by a phase inverter with the reversed enable signal of sense amplifier；The sense amplifier enable signal is in high electricity
Usually effectively, and the reversed enable signal of the sense amplifier is effective in low level or the sense amplifier is enabled
Signal is effective in low level, and the reversed enable signal of the sense amplifier is effective in high level.
Sense amplifier enable signal is reversely enabled into letter by a phase inverter and sense amplifier in above-described embodiment
Number be connected, the driving capability to sense amplifier can be reinforced.
In specific implementation, said write read-out control unit further includes：For to control circuit connecting line forward direction
It is reversed the precharge unit of precharge with control circuit connecting line, the precharge unit is by precharging signal and sensitive puts
The reversed enable signal management and control of big device.
In specific implementation, the gating signal line link address decoder.
In specific implementation, the data input pin is by input enable signal management and control, when the input enable signal is effective
When, receive data to be written from data receiver.
As described below, the embodiment of the present invention provides a kind of Static RAM.
The Static RAM includes：Memory cell array, address decoder, global control circuit and one or
Multiple input output circuit.
The difference is that, the imput output circuit in the Static RAM is used such as the present invention with the prior art
The imput output circuit of Static RAM provided in previous embodiment.The Static RAM in write cycle time,
First write data into it is reversed to control circuit connecting line forward direction and control circuit connecting line, then by sense amplifier will control
Voltage difference between circuit connecting wire forward direction and control circuit connecting line are reversed is amplified to supply voltage, finally by sense amplifier
Output complete to be written or read so that in write-in and readout in circuit each component reusability higher, to write
Enter and same circuit may be used to realize in reading, therefore, imput output circuit or even entire Static RAM are opposite
Occupied space is less for the prior art.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (14)
1. a kind of Static RAM method for writing data, which is characterized in that including：
Detect that a certain gating signal line is selected, the gating signal line corresponds to the bit line of a pair of of logical complement, write-in
It is different with gating signal line used in reading；
According to selected gating signal line, corresponding bit line is chosen；
Selected bit line is separately connected control circuit connecting line forward direction and control circuit connecting line is reversed；
Data to be written are received from data input pin, and change the control circuit connecting line forward direction according to the data to be written
Or the voltage that control circuit connecting line is reversed, wherein write-in and reading use same control circuit, according to quilt on multiplexer
The gating signal line chosen is written or reads to determine；
The voltage difference of control circuit connecting line forward direction and control circuit connecting line between reversed is amplified to by sense amplifier
Supply voltage；
Via the selected bit line, the data that the sense amplifier exports are written to the target into memory cell array
Storage unit.
2. Static RAM method for writing data as described in claim 1, which is characterized in that gating signal line area
Point write-in and reading be specifically：Gating signal line for write-in is connected by a NMOS transistor with the bit line, and is used
It is connected with the bit line by a PMOS transistor in the gating signal line of reading.
3. Static RAM method for writing data as described in claim 1, which is characterized in that the sense amplifier by
Sense amplifier enable signal management and control, the sense amplifier enable signal are reversely made by a phase inverter with sense amplifier
Energy signal is connected；Change the control circuit connecting line forward direction or control circuit connecting line according to the data to be written described
After reversed voltage, after the signal of sense amplifier reversed enable signal output is negated by phase inverter so that the spirit
Quick amplifier enable signal is effective, and the sense amplifier is started to work.
4. Static RAM method for writing data as claimed in claim 3, which is characterized in that the sense amplifier makes
Can signal it is effective in high level, and the reversed enable signal of the sense amplifier is effective in low level or the spirit
Quick amplifier enable signal is effective in low level, and the reversed enable signal of the sense amplifier is effective in high level.
5. Static RAM method for writing data as described in claim 1, which is characterized in that in the selected position
Line be separately connected control circuit connecting line forward direction and control circuit connecting line it is reversed before, by precharging signal and sense amplifier
Reversed enable signal management and control turns off the precharge reversed to control circuit connecting line forward direction and control circuit connecting line.
6. Static RAM method for writing data as described in claim 1, which is characterized in that address decoder is according to it
The address received, to choose a certain gating signal line.
7. Static RAM method for writing data as described in claim 1, which is characterized in that the data input pin by
Enable signal management and control is inputted, control circuit connecting line forward direction and control circuit connecting line are separately connected in the selected bit line
After reversed, the input enable signal is effective, and receives data to be written from data input pin.
8. a kind of imput output circuit of Static RAM, which is characterized in that including：Multiplexer and write-in read control
Device processed；Wherein,
The multiplexer connects depositing in the memory cell array of its management and control by the bit line of one or more pairs of logical complements
Storage unit is separately connected corresponding gating signal line, write-in and the used gating signal of reading per a pair of bit line
Line is different；
Said write read-out controller includes sense amplifier, data input pin and data output end；The data input pin connects
Connection control circuit connecting line forward direction and control circuit connecting line are reversed；The sense amplifier is used for control circuit connecting line just
To and control circuit connecting line it is reversed between voltage difference be amplified to supply voltage, wherein write-in and read use same control
Circuit determines write-in according to the gating signal line being selected on multiplexer or reads；
Connected by control circuit connecting line forward direction and control circuit between the multiplexer and said write read-out controller
Wiring is reversely connected.
9. a kind of imput output circuit of Static RAM as claimed in claim 8, which is characterized in that the gating letter
Number line distinguishes write-in and reading is specifically：Gating signal line for write-in passes through a NMOS transistor and the bit line phase
Even, and the gating signal line for reading is connected by a PMOS transistor with the bit line.
10. a kind of imput output circuit of Static RAM as claimed in claim 8, which is characterized in that described sensitive
Amplifier is passed through a phase inverter and sensitive amplification by sense amplifier enable signal management and control, the sense amplifier enable signal
The reversed enable signal of device is connected；The sense amplifier enable signal is effective in high level, and the sense amplifier is reversed
Enable signal is effective in low level or the sense amplifier enable signal is effective in low level and described sensitive
The reversed enable signal of amplifier is effective in high level.
11. a kind of imput output circuit of Static RAM as claimed in claim 8, which is characterized in that said write
Read-out control unit further includes：For being reversed precharge to control circuit connecting line forward direction and control circuit connecting line
Precharge unit, the precharge unit is by precharging signal and the reversed enable signal management and control of sense amplifier.
12. a kind of imput output circuit of Static RAM as claimed in claim 8, which is characterized in that the gating
Signal wire link address decoder.
13. a kind of imput output circuit of Static RAM as claimed in claim 8, which is characterized in that the data
Input terminal is by input enable signal management and control, and when the input enable signal is effective, data to be written are received from data receiver.
14. a kind of Static RAM, including：Memory cell array and address decoder, which is characterized in that further include one
Or the imput output circuit of multiple Static RAM as described in any one of claim 8 to 13.
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| CN111161785A (en) * | 2019-12-31 | 2020-05-15 | 展讯通信（上海）有限公司 | Static random access memory and fault detection circuit thereof |
| CN112542195B (en) * | 2020-12-30 | 2021-09-14 | 芯天下技术股份有限公司 | Circuit for reducing area of nonvolatile flash memory chip and nonvolatile flash memory chip |
| CN116486881A (en) * | 2022-01-17 | 2023-07-25 | 长鑫存储技术有限公司 | Method and device for detecting memory and analog detection method |
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| US5936909A (en) * | 1997-01-29 | 1999-08-10 | Hitachi, Ltd. | Static random access memory |
| CN102332296A (en) * | 2011-07-15 | 2012-01-25 | 北京兆易创新科技有限公司 | Data reading method and data writing method of memory circuit |
| CN103187093A (en) * | 2013-03-18 | 2013-07-03 | 西安华芯半导体有限公司 | Static random access memory and access control method and bit line pre-charging circuit thereof |
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| US4935901A (en) * | 1987-02-23 | 1990-06-19 | Hitachi, Ltd. | Semiconductor memory with divided bit load and data bus lines |
| US5936909A (en) * | 1997-01-29 | 1999-08-10 | Hitachi, Ltd. | Static random access memory |
| CN102332296A (en) * | 2011-07-15 | 2012-01-25 | 北京兆易创新科技有限公司 | Data reading method and data writing method of memory circuit |
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