CN105448329B - Static RAM and its method for writing data, imput output circuit - Google Patents
Static RAM and its method for writing data, imput output circuit Download PDFInfo
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Abstract
A kind of Static RAM and its method for writing data, imput output circuit, the method includes：Detect that a certain gating signal line is selected, the gating signal line is distinguished write-in and read；According to selected gating signal line, corresponding bit line is chosen；Selected bit line is separately connected control circuit connecting line forward direction and control circuit connecting line is reversed；Change the voltage that the control circuit connecting line is positive or control circuit connecting line is reversed according to data to be written；The voltage difference of control circuit connecting line forward direction and control circuit connecting line between reversed is amplified to supply voltage by sense amplifier；Via the selected bit line, the data that the sense amplifier exports are written to the Destination Storage Unit into memory cell array.The reusability higher with each component in circuit in readout is being written in the present invention, to which same circuit may be used to realize in write-in and reading, reduces the space hold of imput output circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and in particular, to a static random access memory, a data writing method thereof, and an input/output circuit thereof.
Background
Random Access Memories (RAMs) can be classified into Static Random Access Memories (SRAMs) and Dynamic Random Access Memories (DRAMs). The static random access memory can store data stored in the static random access memory as long as the static random access memory is powered on, periodic updating is not needed, and the writing speed and the reading speed are much higher than those of the dynamic random access memory. But its integration level is low, and each dynamic random access memory cell only needs one transistor and one small capacitor, and each static random access memory cell needs two to ten transistors (six or eight are the mainstream) and some related circuits. Therefore, static ram usually takes up more space than dynamic ram with the same capacity. How to reduce the space occupation of the static random access memory is a difficult problem in the field of memories and even integrated circuits.
As shown in fig. 1, the sram includes a memory cell array, an address decoder, a global control circuit, and one or more input/output (IO) circuits.
In the static random access memory, around the memory cell array arranged in a matrix form, there is an interface circuit for external signals, including word lines and bit lines perpendicular to each other, taking fig. 1 as an example, the horizontal connecting lines are word lines, the vertical connecting lines are bit lines, and the intersection of each word line and each pair of logically complementary bit lines points to one memory cell in the memory cell array. Each memory cell in the memory cell array managed by each input/output circuit corresponds to a set of addresses, and each set of addresses may correspond to one or more memory cells (depending on the number of input/output circuits in the sram).
A static random access memory may include a plurality of parallel input/output circuits, each managing a portion of the memory cell array, the capacity of the managing being determined by the number of word lines and the number of multiplexing paths of the input/output circuits. Taking fig. 1 as an example, comprising 8 parallel word lines (WL 0-WL 7), each set of i/o circuits manages 4 pairs of complementary bit lines (i.e. the number of multiplexing paths is 4), and the capacity managed by each set of i/o circuits is 32 bits (bit).
In the prior art, an input-output circuit generally comprises three parts: a multiplexer, a write control circuit and a read control circuit. The main functions of the three parts are as follows:
a controlled multiplexer for selecting and disconnecting the bit lines of the logic complement in the memory cell array from the write control circuit/read control circuit, and determining which column of memory cells in the memory cell array should be written/read;
a write control circuit for managing Data input terminals (Data-in, DI) and providing a drive to write Data into the memory cell array;
and the read control circuit mainly comprises a sensitive amplifier which is used for amplifying the voltage difference of the bit lines with complementary logic and outputting data.
Fig. 2 shows a mainstream design structure of an input/output circuit of a static random access memory in the prior art. The meaning of each port in the figure is as follows:
YSL-strobe signal logic low, YSH-strobe signal logic high,
BLL/BLBL-bitline logic low, BLH/BLBH-bitline logic high,
WBL/WBLB-write circuit connection line, RBL/RBLB-read circuit connection line,
a DI-data input terminal, a DO-data output terminal,
PRCH-precharge signal, IN _ EN-input enable signal,
WEN-write enable signal, SA _ EN-sense Amp enable signal.
It should be noted that, a plurality of pairs of complementary bitlines may be included between the logic low bit BLL/BLBL and the logic high bit BLH/BLBH, the bitline and each wordline are matched to correspond to a memory cell in the memory cell array, the number of pairs of bitlines depends on the number of multiplexing paths of the multiplexer (and is also equal to the number of multiplexing paths of the input/output circuit), for example, for the four-multiplexer (MUX4) used in fig. 1, 4 pairs of complementary bitlines are included, for the eight-multiplexer (MUX8), 8 pairs of complementary bitlines are included, for the sixteen-multiplexer (MUX16), 16 pairs of complementary bitlines are included, and so on.
Accordingly, multiple strobe signal lines may be included between the strobe signal logic low YSL and the strobe signal logic high YSH, and each strobe signal line corresponds to a pair of logically complementary bit lines.
Wherein:
the multiplexer is connected to a write circuit connecting line WBL/WBLB or a read circuit connecting line RBL/RBLB through one of a gating signal logic low bit YSL to a gating signal logic high bit YSH and a pair of logic complementary bit lines selected from a bit line logic low bit BLL/BLBL to a bit line logic high bit BLH/BLBH;
in a write cycle, enabling write, receiving data to be written from a data input terminal DI, and writing the data to the write circuit connection lines WBL/WBLB, wherein the voltage of one of the write circuit connection lines WBL/WBLB is changed, so that the voltage of one of a pair of logic complementary bit lines is changed along with the change of the voltage of the one of the pair of logic complementary bit lines through the multiplexer, and finally, a selected memory cell in the memory cell array is inverted, thereby realizing write operation;
in a read cycle, a pair of logically complementary bit lines corresponding to a target memory cell is selected and connected to the sensing circuit connection line RBL/RBLB, and a logic 0 or a logic 1 stored in the target memory cell changes a voltage of one of the sensing circuit connection lines RBL/RBLB, and the sense amplifier enable signal SA _ EN is asserted to amplify a voltage difference between two lines of the sensing circuit connection line and finally output data through the data output terminal DO.
In the input/output circuit architecture of the static random access memory, the write control circuit and the read control circuit of the input/output circuit are independent. The input and output circuit realizes the principle of writing function and the principle of reading function, especially the signal output by the sensitive amplifier is directly output through the data output end in the reading period, the signal output by the sensitive amplifier is not directly sent to the bit line to realize writing in the writing period, even the sensitive amplifier is not included in the writing control circuit at all. As described above, since the principle of the input/output circuit for implementing the write function and the principle of the input/output circuit for implementing the read function are quite different from each other, it is difficult to integrate the write control circuit and the read control circuit into a single unit.
In addition, by corresponding the structure of the sram to the layout, it can be seen from fig. 1 that the width of the input/output circuit is limited by the size of the memory cell array itself. Specifically, in order to avoid occupying the wiring space of the peripheral input-output circuits, therefore, the input-output circuits cannot exceed the width of the memory cell array they manage in width.
As mentioned above, the input/output circuit in the prior art generally includes: the circuit comprises a multiplexer, a write control circuit and a read control circuit. The width of the multiplexer varies with the number of multiplexing paths, and specifically, the larger the number of multiplexing paths of the multiplexer is, the wider the memory cell array it manages, and vice versa. That is, the width of the multiplexer increases and decreases synchronously with the width of the memory cell array it manages. Therefore, the above-mentioned limitation in width is relatively easy to satisfy for a multiplexer.
However, the sizes of the write control circuit and the read control circuit do not change with the number of multiplexing paths. The sizes of the write control circuit and the read control circuit are not obviously changed no matter how many multiplexing paths of the input-output circuit are and no matter how wide the memory cell array is controlled by the input-output circuit.
For the above reasons, for an input/output circuit with a small number of multiplexing paths, for example, when the number of multiplexing paths is 2 or even 1, only two memory cells or even only one memory cell has a width to accommodate the write control circuit and the read control circuit. In this case, in order to avoid occupying the wiring space of the peripheral input/output circuits, the height of the circuits is only increased, and the height of the whole sram is finally increased.
Disclosure of Invention
The technical problem solved by the invention is as follows: how to realize the functions of the write control circuit and the read control circuit of the input-output circuit in the prior art by the same circuit.
In order to solve the above problem, an embodiment of the present invention provides a method for writing data into a static random access memory, including:
detecting that a certain gating signal line is selected, wherein the gating signal line corresponds to a pair of logic complementary bit lines and the gating signal line distinguishes writing and reading;
selecting the corresponding bit line according to the selected gating signal line;
the selected bit lines are respectively connected with the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line;
receiving data to be written from a data input end, and changing the forward voltage of the control circuit connecting wire or the reverse voltage of the control circuit connecting wire according to the data to be written;
amplifying the voltage difference between the forward direction of the control circuit connecting wire and the reverse direction of the control circuit connecting wire to a power supply voltage through a sensitive amplifier;
and writing the data output by the sensitive amplifier into a target memory cell in the memory cell array through the selected bit line.
Optionally, the specific steps of the gate signal line distinguishing writing and reading include: the gate signal line for writing is connected to the bit line through an NMOS transistor, and the gate signal line for reading is connected to the bit line through a PMOS transistor.
Optionally, the sense amplifier is controlled by a sense amplifier enable signal, and the sense amplifier enable signal is connected to a sense amplifier reverse enable signal through an inverter; and after the forward direction of the control circuit connecting wire or the reverse voltage of the control circuit connecting wire is changed according to the data to be written, inverting the signal output by the sense amplifier reverse enabling signal through the inverter, enabling the sense amplifier enabling signal to be effective, and enabling the sense amplifier to start working.
Optionally, the sense amplifier enable signal is active at a high level and the sense amplifier reverse enable signal is active at a low level, or the sense amplifier enable signal is active at a low level and the sense amplifier reverse enable signal is active at a high level.
Optionally, before the selected bit line is respectively connected with the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line, the selected bit line is controlled by a pre-charging signal and a sense amplifier reverse enable signal, and pre-charging of the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line is cut off.
Optionally, the address decoder selects a certain strobe signal line according to the address received by the address decoder.
Optionally, the data input end is controlled by an input enable signal, and after the selected bit line is respectively connected to the control circuit connecting line in the forward direction and the control circuit connecting line in the reverse direction, the input enable signal is valid and receives data to be written from the data input end.
In order to solve the above technical problem, an embodiment of the present invention further provides an input/output circuit of a static random access memory, including: a multiplexer and a write read controller; wherein,
the multiplexer is connected with the storage units in the storage unit array managed and controlled by the multiplexer through one or more pairs of logic complementary bit lines, each pair of the bit lines is respectively connected with a gating signal line corresponding to the bit line, and the gating signal lines are used for distinguishing writing and reading;
the write-in and read-out controller comprises a sensitive amplifier, a data input end and a data output end; the data input end is connected with the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line; the sensitive amplifier is used for amplifying the voltage difference between the forward direction of the control circuit connecting wire and the reverse direction of the control circuit connecting wire to a power supply voltage;
the multiplexer is connected with the write-in read-out controller in a forward direction through a control circuit connecting wire and in a reverse direction through a control circuit connecting wire.
Optionally, the specific steps of the gate signal line distinguishing writing and reading include: the gate signal line for writing is connected to the bit line through an NMOS transistor, and the gate signal line for reading is connected to the bit line through a PMOS transistor.
Optionally, the sense amplifier is controlled by a sense amplifier enable signal, and the sense amplifier enable signal is connected to a sense amplifier reverse enable signal through an inverter; the sense amplifier enable signal is active at a high level and the sense amplifier reverse enable signal is active at a low level, or the sense amplifier enable signal is active at a low level and the sense amplifier reverse enable signal is active at a high level.
Optionally, the write/read control unit further includes: and the pre-charging unit is used for pre-charging the control circuit connecting line forward direction and the control circuit connecting line in a reverse direction and is controlled by a pre-charging signal and a sense amplifier reverse enabling signal.
Optionally, the gating signal line is connected to an address decoder.
Optionally, the data input end is controlled by an input enable signal, and when the input enable signal is valid, the data to be written is received from the data receiving end.
In order to solve the above technical problem, an embodiment of the present invention further provides a static random access memory, including: the memory cell array and the address decoder further comprise the input-output circuit.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the writing period, data is written into the forward direction of the control circuit connecting wire and the reverse direction of the control circuit connecting wire, then the voltage difference between the forward direction of the control circuit connecting wire and the reverse direction of the control circuit connecting wire is amplified to the power voltage through the sensitive amplifier, and finally writing or reading is finished through the output of the sensitive amplifier, so that the multiplexing rate of each component in the circuit in the writing and reading processes is higher, the writing and reading can be realized by adopting the same circuit, and the space occupation of an input and output circuit is reduced.
Furthermore, the input/output circuit corresponding to the layout, especially for the input/output circuit with less multiplexing paths, can effectively avoid the situation that the circuit height is forced to be increased due to insufficient width.
Furthermore, a write enable signal in the prior art is not needed in a write cycle, an output signal of the sense amplifier is directly written into the target memory cell, and the data input end is controlled by the input enable signal, that is, the write enable signal is omitted through multiplexing of the input enable signal, so that the space occupation of the circuit is further reduced.
Further, a gate signal line for writing is connected to the bit line through an NMOS transistor, and a gate signal line for reading is connected to the bit line through a PMOS transistor, thereby achieving distinguishing between writing and reading through the gate signal lines.
Furthermore, the sense amplifier enabling signal is connected with the sense amplifier reverse enabling signal through an inverter, so that the driving capability of the sense amplifier is enhanced, and the multiplexing of the sense amplifier in the writing and reading processes is realized.
Drawings
FIG. 1 is a block diagram of a static random access memory architecture;
FIG. 2 is a block diagram of an input/output circuit of a prior art SRAM;
FIG. 3 is a block diagram of an input/output circuit of the SRAM according to the embodiment of the present invention;
FIG. 4 is a flow chart of a method for writing SRAM data according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of an input/output circuit of the SRAM in the embodiment of the present invention;
FIG. 6 is a flow chart of a method for reading data from an SRAM according to an embodiment of the present invention;
FIG. 7 is a signal waveform diagram of the input-output circuit of the SRAM in the embodiment of the present invention in the write cycle and the read cycle;
fig. 8 is a circuit configuration diagram of another embodiment of an input/output circuit of a static random access memory according to an embodiment of the present invention.
Detailed Description
As can be seen from the analysis of the background art, in the input/output circuit of the sram in the prior art, the write control circuit and the read control circuit are independent two parts. And the principle of the input-output circuit for realizing the writing function and the principle of the input-output circuit for realizing the reading function are quite different. Therefore, it is difficult to integrate the write control circuit and the read control circuit.
Because the sizes of the write control circuit and the read control circuit do not change along with the change of the multiplexing number of the static random access memory, for the input and output circuit with less multiplexing number, only two memory cells or even only one memory cell is wide to accommodate the write control circuit and the read control circuit corresponding to the layout. In this case, in order to avoid occupying the wiring space of the peripheral input/output circuits, the height of the circuits is only increased, and the height of the whole sram is finally increased.
In view of the above-mentioned drawbacks of the prior art, the inventor has improved the structure of the input/output circuit of the sram and the data writing method thereof, so that the functions of the write control circuit and the read control circuit can be performed by using the same circuit. Meanwhile, the space occupied by the writing control circuit and the reading control circuit is also obviously reduced, and especially the width of the memory cell array which is not easily beyond the width of the memory cell array controlled by the writing control circuit and the reading control circuit is not easy to exceed.
In order that those skilled in the art will better understand and realize the present invention, the following detailed description is given by way of specific embodiments with reference to the accompanying drawings.
As described below, embodiments of the present invention provide a method for writing data into a static random access memory.
First, the data writing method is implemented by requiring a multiplexer to assist in distinguishing between writing and reading.
Referring to the block diagram of the input/output circuit structure of the static random access memory shown in fig. 3, the meaning of each port in the diagram is as follows:
YSRL — a logic low read of a strobe signal,
YSRH-strobe signal logic high read out,
YSWL-strobe signal logic low write,
YSWH-strobe signal logic high write,
BLL/BLBL-bitline logic low, BLH/BLBH-bitline logic high,
the connection line of the DL control circuit is positive, the connection line of the DLB control circuit is reverse,
a DI-data input terminal, a DO-data output terminal,
PRCH-precharge signal, IN _ EN-input enable signal, SA _ EN-sense amplifier enable signal.
It should be noted that a plurality of pairs of complementary bit lines may be included between the bit line logic low BLL/BLBL and the bit line logic high BLH/BLBH, a plurality of strobe signal lines may be included between the strobe signal logic low reading YSRL and the strobe signal logic high reading YSRH, and a plurality of strobe signal lines may be included between the strobe signal logic low writing YSWL and the strobe signal logic high writing YSWH.
As can be seen from fig. 3, the multiplexer in this embodiment distinguishes between writing and reading on the strobe signal. Thus, the strobe signal not only determines which column of memory cells in the memory cell array should be written/read, but also serves to assist in distinguishing between writing and reading.
In one embodiment, as shown in FIG. 5, the strobe signal line for writing is connected to the bit line through an NMOS transistor, and the strobe signal line for reading is connected to the bit line through a PMOS transistor, thereby achieving the above-described function of assisting in distinguishing between writing and reading.
It will be appreciated that the present invention is not limited to the above-described embodiment, and that it is equally possible to distinguish between writing and reading if the strobe signal line for writing is connected to the bit line via a PMOS transistor, and the strobe signal line for reading is connected to the bit line via an NMOS transistor.
Referring to the flowchart of the sram data writing method shown in fig. 4, the following detailed description is made by specific steps:
s401, detecting that a certain gating signal line is selected.
A strobe signal line can be selected by an address decoder according to an address output from a Central Processing Unit (CPU).
The address decoder also selects a word line based on the address. A word line is coupled to a pair of logically complementary bit lines corresponding to one or more memory cells in the memory cell array. The number of memory cells corresponding to each address depends on how many sets of parallel input/output circuits are in the static random access memory, and taking the static random access memory with 4 sets of parallel input/output circuits in fig. 1 as an example, one set of addresses selects a word line and a pair of logic complementary bit lines, which correspond to 4 memory cells.
Since the strobe signal line in this embodiment distinguishes writing and reading. Thus, upon detecting that a strobe signal line has been selected, it is possible to determine (in cooperation with the word lines, in common) which memory cells of the memory cell array should be written to or read from, corresponding to a pair of logically complementary bit lines, and to specify whether the operation to be performed is to be written to or read from.
S402, according to the selected strobe signal line, the corresponding bit line is selected.
Since each strobe signal line corresponds to a pair of logically complementary bit lines. Therefore, after step S401, according to the selected strobe signal line, a pair of complementary bit lines corresponding thereto can be further selected.
And S403, turning off the pre-charging of the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line.
In a specific implementation, as shown in fig. 5 and 8, three PMOS transistors, i.e., a seventh PMOS transistor P7, an eighth PMOS transistor P8, and a ninth PMOS transistor P9, are used to precharge the control circuit connection line forward direction DL and the control circuit connection line reverse direction DLB.
The three aforementioned PMOS transistors for precharging the control circuit connection line in the forward direction and the control circuit connection line in the reverse direction are controlled by a precharge signal PRCH and a sense amplifier reverse enable signal SA _ ENB.
S404, the selected bit lines are respectively connected with the control circuit connecting line forward direction and the control circuit connecting line reverse direction.
In the write cycle, one of the gate signal logic low write YSWL to the gate signal logic high write YSWH is selected in step S401, and then one of the pair of the bit line logic low BLL/BLBL to the bit line logic high BLL/BLBL is selected in step S402.
As shown in fig. 5 and 7, the selected strobe signal write will have a logic 1 pulse that turns on the NMOS transistor between its corresponding logic complementary bit line, causing the pair of selected bit lines to be connected to the control circuit connection line forward DL and the control circuit connection line reverse DLB, respectively.
Taking the selected gating signal line as the gating signal logic high bit to write into YSWH as an example, the corresponding bit line is the bit line logic high bit BLH/BLBH, the third NOS tube N3 and the fourth NMOS tube N4 are opened, so that the bit line logic high bit forward direction BLH is connected with the control circuit connecting line forward direction DL, and the bit line logic high bit reverse direction BLBH is connected with the control circuit connecting line reverse direction DLB.
S405, receiving data to be written from a data input end, and changing the forward voltage of the control circuit connecting line or the reverse voltage of the control circuit connecting line according to the data to be written.
As shown in fig. 5 and 7, in the write cycle, the input enable signal has a logic 1 pulse, so that the eighth NMOS transistor N8 and the ninth NMOS transistor N9 are turned on briefly, and the voltage of the data input terminal DI controlled by the input enable signal changes the voltage of the forward DL of the control circuit connection line or the reverse DLB of the control circuit connection line, thereby writing the data to be written into the forward DL of the control circuit connection line and the reverse DLB of the control circuit connection line.
In a specific implementation, as shown in fig. 5, after receiving the data to be written, the voltage at the data input DI may cause the voltage at one of the control circuit connection line forward direction DL and the control circuit connection line reverse direction DLB to change. Assuming that the data input terminal DI is a logic 0, the data input terminal DI will cause the voltage of one of the control circuit connection line forward direction DL and the control circuit connection line backward direction DLB to be pulled down.
It should be noted that, in this step, it is not necessary for the forward DL of the control circuit connection line or the backward DLB of the control circuit connection line to be pulled down to logic 0, and it is only necessary for the voltage difference between the forward DL of the control circuit connection line and the backward DLB of the control circuit connection line to ensure the operation of the sense amplifier.
And S406, amplifying the voltage difference between the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line to a power supply voltage through a sensitive amplifier.
It should be noted that: in the extreme case, if the write drive is strong enough, it may happen that the voltage difference between the forward direction of the control circuit connection line and the reverse direction of the control circuit connection line is already the supply voltage before amplification, at which time the sense amplifier keeps the voltage difference at the supply voltage.
As shown in fig. 5, the typical sense amplifier structure includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7 and the related connecting wires. Of course, the specific combination structure of the sense amplifier is not limited in the present invention, as long as the sense amplifier is controlled by the sense amplifier enable signal, and the voltage difference between the control circuit connection line forward DL and the control circuit connection line backward DLB can be amplified to the power supply voltage after the voltage difference between the control circuit connection line forward DL and the control circuit connection line backward DLB reaches a certain threshold in function.
The sense amplifier is controlled by a sense amplifier enable signal SA _ EN, and the sense amplifier enable signal SA _ EN is connected with a sense amplifier reverse enable signal SA _ ENB through an inverter.
If the sense amplifier enable signal SA _ EN is active at a high level, the sense amplifier reverse enable signal SA _ ENB is active at a low level; conversely, if the sense amplifier enable signal SA _ EN is active at a low level, the sense amplifier reverse enable signal SA _ ENB is active at a high level.
After the signal output by the sense amplifier reverse enable signal SA _ ENB is inverted by the inverter, the sense amplifier enable signal SA _ EN is enabled, so that the seventh NMOS transistor N7 is opened, and the sense amplifier starts to work.
It will be appreciated that sense amplifiers are also used in the read cycle (it is known in the art to use sense amplifiers to read data), and thus the above embodiments enable multiplexing of sense amplifiers during writing and reading.
In one embodiment, the sense amplifier enable signal may be coupled to the sense amplifier reverse enable signal via an inverter to enhance the driving capability of the sense amplifier.
S407, writing the data output by the sense amplifier to a target memory cell in the memory cell array via the selected bit line.
In this embodiment, the signal output by the sense amplifier is directly sent to the bit line, thereby implementing data writing.
In the above-described embodiments, the principle in which the input-output circuit implements data writing is similar to the principle in which it implements data reading. The flow of the input-output circuit to realize the readout is briefly described below for comparison: as shown in fig. 6, includes:
s601, detecting that a certain gating signal line is selected.
S602, according to the selected strobe signal line, the corresponding bit line is selected.
S603, turning off the pre-charging to the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line.
And S604, connecting the selected bit lines with the control circuit connecting line forward direction and the control circuit connecting line reverse direction respectively.
S605, the selected memory cell changes the voltage of the control circuit connecting line forward or the control circuit connecting line reverse through the bit line.
And S606, amplifying the voltage difference between the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line to the power voltage through the sensitive amplifier.
And S607, outputting the data output by the sensitive amplifier through a data output end.
For example, assuming that BLH/BLBH is selected as a logic high bit in the write cycle and BLL/BLBL is selected as a logic low bit in the read cycle, waveforms of signals in the write cycle and the read cycle are shown in fig. 7 (where CK represents a clock signal).
It can be seen that in both the write cycle and the read cycle, the input/output circuit writes data into the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line, amplifies the voltage difference between the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line to the power supply voltage through the sense amplifier, and finally completes the write or read by the output of the sense amplifier. That is, in the write cycle and the read cycle, the multiplexing rate of each component in the circuit is high, so that both can be realized by using the same circuit.
Whereas in the prior art, as analyzed in the background section, the sense amplifier is not included at all in the prior art write control circuit. And the principle that the writing control circuit realizes the writing function and the principle that the reading control circuit realizes the reading function are different, so the writing control circuit and the reading control circuit are difficult to realize by the same circuit. Even if the two parts of circuits are artificially combined together, the two parts of circuits still only respectively realize the functions of the two parts of circuits, and the multiplexing rate of each component in the circuits is low.
According to the embodiment of the invention, through the improvement of the data writing method of the static random access memory, the writing and reading can be realized by adopting the same circuit, the multiplexing rate of each component in the circuit is higher, and the space occupation of the input and output circuit is reduced. The input and output circuit with less multiplexing paths can effectively avoid the situation that the circuit height is forced to be increased due to insufficient width.
In addition, in the above embodiment, the write enable signal in the prior art is not needed in the write cycle, the output signal of the sense amplifier is directly written into the target memory cell, and the data input terminal is controlled by the input enable signal, that is, the write enable signal is omitted by multiplexing the input enable signal, thereby further reducing the space occupation of the circuit.
As described below, embodiments of the present invention provide an input/output circuit of a static random access memory.
Referring to fig. 5, a circuit diagram of an input/output circuit of a static random access memory, which includes a multiplexer and a write/read controller, is shown.
The multiplexer is connected with the storage units in the storage unit array managed and controlled by the multiplexer through one or more pairs of logic complementary bit lines, each pair of the bit lines is respectively connected with a gating signal line corresponding to the bit line, and the gating signal lines are used for distinguishing writing and reading;
the write-read controller comprises a sense amplifier, a data input end DI and a data output end DO; the data input end DI is connected with a control circuit connecting wire forward DL and a control circuit connecting wire reverse DLB; the sensitive amplifier is used for amplifying the voltage difference between the forward DL of the control circuit connecting line and the reverse DLB of the control circuit connecting line to power supply voltage;
the multiplexer is connected with the write-read controller through a control circuit connecting wire in a forward direction DL and a control circuit connecting wire in a reverse direction DLB.
As shown in fig. 5, a typical sense amplifier structure includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and related connection lines. Of course, the specific combination structure of the sense amplifier is not limited in the present invention, as long as the sense amplifier is controlled by the sense amplifier enable signal, and the voltage difference between the control circuit connection line forward DL and the control circuit connection line backward DLB can be amplified to the power supply voltage after the voltage difference between the control circuit connection line forward DL and the control circuit connection line backward DLB reaches a certain threshold in function.
According to the technical scheme, in the writing period, data are written into the control circuit connecting line in the forward direction and the control circuit connecting line in the reverse direction, the voltage difference between the control circuit connecting line in the forward direction and the control circuit connecting line in the reverse direction is amplified to the power supply voltage through the sensitive amplifier, and finally writing or reading is completed through the output of the sensitive amplifier, so that the multiplexing rate of each component in the circuit in the writing and reading processes is higher, writing and reading can be realized by adopting the same circuit, and the space occupation of the input and output circuit is reduced.
The input and output circuit with less multiplexing paths can effectively avoid the situation that the circuit height is forced to be increased due to insufficient width.
Meanwhile, a write enable signal in the prior art is not needed in a write period, the output signal of the sense amplifier is directly written into the target storage unit, and the data input end is controlled by the input enable signal, namely the write enable signal is saved through multiplexing of the input enable signal, so that the space occupation of the circuit is further reduced.
In a specific implementation, the step of separately writing and reading the strobe signal line specifically includes: the gate signal line for writing is connected to the bit line through an NMOS transistor, and the gate signal line for reading is connected to the bit line through a PMOS transistor, and the gate signal line for reading is connected to the bit line through an NMOS transistor.
As can be seen from the above description of the technical solutions, the multiplexer in the present embodiment distinguishes between writing and reading on the strobe signal. Thus, the strobe signal not only determines which column of memory cells in the memory cell array should be written/read, but also serves to assist in distinguishing between writing and reading.
In specific implementation, the sense amplifier is controlled by a sense amplifier enable signal, and the sense amplifier enable signal is connected with a sense amplifier reverse enable signal through an inverter; the sense amplifier enable signal is active at a high level and the sense amplifier reverse enable signal is active at a low level, or the sense amplifier enable signal is active at a low level and the sense amplifier reverse enable signal is active at a high level.
In the above embodiment, the sense amplifier enable signal is connected to the sense amplifier reverse enable signal through an inverter, so that the driving capability of the sense amplifier can be enhanced.
In a specific implementation, the write/read control unit further includes: and the pre-charging unit is used for pre-charging the control circuit connecting line forward direction and the control circuit connecting line in a reverse direction and is controlled by a pre-charging signal and a sense amplifier reverse enabling signal.
In a specific implementation, the gating signal line is connected with an address decoder.
In a specific implementation, the data input terminal is controlled by an input enable signal, and when the input enable signal is valid, the data to be written is received from the data receiving terminal.
As described below, embodiments of the present invention provide a static random access memory.
The static random access memory includes: the memory comprises a memory cell array, an address decoder, a global control circuit and one or more input and output circuits.
The difference from the prior art is that the input-output circuit in the static random access memory adopts the input-output circuit of the static random access memory provided in the foregoing embodiment of the present invention. In a writing period of the static random access memory, data is written into a control circuit connecting line in a forward direction and the control circuit connecting line in a reverse direction, then a voltage difference between the control circuit connecting line in the forward direction and the control circuit connecting line in the reverse direction is amplified to a power supply voltage through a sensitive amplifier, and finally writing or reading is completed through the output of the sensitive amplifier, so that the multiplexing rate of each component in the circuit in the writing and reading process is higher, and the writing and reading can be realized by adopting the same circuit, therefore, the space occupied by an input and output circuit and even the whole static random access memory is smaller than that occupied by the prior art.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A method for writing data into a Static Random Access Memory (SRAM), comprising:
detecting that a certain strobe signal line is selected, the strobe signal line corresponding to a pair of logically complementary bit lines, the strobe signal lines used for writing and reading being different;
selecting the corresponding bit line according to the selected gating signal line;
the selected bit lines are respectively connected with the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line;
receiving data to be written from a data input end, and changing the forward voltage of a connecting wire of the control circuit or the reverse voltage of the connecting wire of the control circuit according to the data to be written, wherein the writing and the reading adopt the same control circuit, and the writing or the reading is determined according to a selected gating signal wire on the multiplexer;
amplifying the voltage difference between the forward direction of the control circuit connecting wire and the reverse direction of the control circuit connecting wire to a power supply voltage through a sensitive amplifier;
and writing the data output by the sensitive amplifier into a target memory cell in the memory cell array through the selected bit line.
2. The method for writing data into the static random access memory according to claim 1, wherein the step of writing and reading the data by the strobe signal line in a differentiated manner is specifically as follows: the gate signal line for writing is connected to the bit line through an NMOS transistor, and the gate signal line for reading is connected to the bit line through a PMOS transistor.
3. The method of claim 1, wherein the sense amplifier is controlled by a sense amplifier enable signal, the sense amplifier enable signal being coupled to a sense amplifier reverse enable signal through an inverter; and after the forward direction of the control circuit connecting wire or the reverse voltage of the control circuit connecting wire is changed according to the data to be written, inverting the signal output by the sense amplifier reverse enabling signal through the inverter, enabling the sense amplifier enabling signal to be effective, and enabling the sense amplifier to start working.
4. The method of claim 3, wherein the sense amplifier enable signal is active at a high level and the sense amplifier reverse enable signal is active at a low level, or wherein the sense amplifier enable signal is active at a low level and the sense amplifier reverse enable signal is active at a high level.
5. The method of claim 1, wherein the precharging of the control circuit connection line forward direction and the control circuit connection line reverse direction is turned off by the precharging signal and the sense amplifier reverse enable signal before the selected bit line is connected to the control circuit connection line forward direction and the control circuit connection line reverse direction, respectively.
6. The method of claim 1, wherein the address decoder selects one of the strobe signal lines based on an address received by the address decoder.
7. The method of claim 1, wherein the data input terminal is controlled by an input enable signal, and the input enable signal is asserted and receives data to be written from the data input terminal after the selected bit line is connected to the control circuit connection line in a forward direction and the control circuit connection line in an inverted direction, respectively.
8. An input-output circuit of a static random access memory, comprising: a multiplexer and a write read controller; wherein,
the multiplexer is connected with the storage units in the storage unit array managed and controlled by the multiplexer through one or more pairs of logic complementary bit lines, each pair of the bit lines is respectively connected with the corresponding strobe signal line, and the strobe signal lines used for writing and reading are different;
the write-in and read-out controller comprises a sensitive amplifier, a data input end and a data output end; the data input end is connected with the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line; the sensitive amplifier is used for amplifying the voltage difference between the forward direction of the control circuit connecting line and the reverse direction of the control circuit connecting line to power voltage, wherein the same control circuit is adopted for writing and reading, and whether the writing or the reading is determined according to the selected gating signal line on the multiplexer;
the multiplexer is connected with the write-in read-out controller in a forward direction through a control circuit connecting wire and in a reverse direction through a control circuit connecting wire.
9. The input-output circuit of a static random access memory according to claim 8, wherein said strobe signal line to distinguish between writing and reading is specifically: the gate signal line for writing is connected to the bit line through an NMOS transistor, and the gate signal line for reading is connected to the bit line through a PMOS transistor.
10. The input-output circuit of claim 8, wherein the sense amplifier is controlled by a sense amplifier enable signal, the sense amplifier enable signal being coupled to a sense amplifier reverse enable signal through an inverter; the sense amplifier enable signal is active at a high level and the sense amplifier reverse enable signal is active at a low level, or the sense amplifier enable signal is active at a low level and the sense amplifier reverse enable signal is active at a high level.
11. The input-output circuit of a static random access memory according to claim 8, wherein said write-read control unit further comprises: and the pre-charging unit is used for pre-charging the control circuit connecting line forward direction and the control circuit connecting line in a reverse direction and is controlled by a pre-charging signal and a sense amplifier reverse enabling signal.
12. The input-output circuit of a static random access memory according to claim 8, wherein said strobe signal line is connected to an address decoder.
13. The input-output circuit of claim 8, wherein the data input terminal is controlled by an input enable signal, and when the input enable signal is asserted, the data to be written is received from a data receiving terminal.
14. A static random access memory comprising: memory cell array and address decoder, characterized in that it further comprises one or more input-output circuits of the static random access memory according to any of claims 8 to 13.
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| CN111161785A (en) * | 2019-12-31 | 2020-05-15 | 展讯通信（上海）有限公司 | Static random access memory and fault detection circuit thereof |
| CN112542195B (en) * | 2020-12-30 | 2021-09-14 | 芯天下技术股份有限公司 | Circuit for reducing area of nonvolatile flash memory chip and nonvolatile flash memory chip |
| CN116486881A (en) * | 2022-01-17 | 2023-07-25 | 长鑫存储技术有限公司 | Method and device for detecting memory and analog detection method |
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