JP2766277B2 - Multiprocessor synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a multiprocessor synchronization system used when synchronizing each processor element.

(Prior Art) As a general-purpose multiprocessor synchronization method, the present applicant has already applied for a method of synchronizing using a message (Japanese Patent Application No. 63-068135).

In this system, as shown in FIG. 21, a plurality of lower synchronous processors 101 are arranged above each processor element 100, and an upper synchronous processor 101 is arranged above each lower synchronous processor 101. When it becomes necessary to synchronize these processor elements 100 during the execution of the same program, a synchronization message having a certain synchronization number is output from each of these processor elements 100, and this is output to each lower-level synchronous processor. When the same synchronization message is output from each of the processor elements 100 under the control of each of the lower synchronization processors 101, the same synchronization message is output from the lower synchronization processor 101.

When the synchronization message is output from all of the lower synchronization processors 101 under the control of the upper synchronization processor 102, the synchronization message indicating completion of synchronization is broadcast from the upper synchronization processor 102 to each processor element 100, and the entire system is broadcasted. Are synchronized.

(Problems to be Solved by the Invention) In such a multiprocessor synchronization system, there is room for improvement in the following points.

(1) If any of the processor elements 100 or the lower-level synchronization processor 101 fails or is removed, some of the synchronization messages to be input to the upper-level synchronization processor 102 are lost, and synchronization is lost. Would. For this reason, a certain processor element 10
Even if 0 failed, it was not possible to operate without removing it, which was not preferable from the viewpoint of system fault tolerance.

(2) When each of the synchronous processors 101 and 102 is formed into an LSI, the number of lower ports of each of the synchronous processors 101 and 102 is fixed, so that each of the processor elements 100 connected below each of the synchronous processors 101 and 102 is fixed. Must be a power of the number of lower ports of each of the synchronous processors 101 and 102. Therefore, when these synchronous processors 101 and 102 are used, the system configuration is extremely limited.

(3) When the operation is performed using a part of the processor element 100 to reduce the communication overhead, the processor element 100 to which no substantial processing is given is provided.
, A dummy synchronization message must be output and received by the lower-level synchronization processor 101, so that the overhead of the synchronization processing is the same as when all the processor elements 100 are used.

In view of the above circumstances, the present invention can operate the system even when a lower processor breaks down or is removed, improve fault tolerance, and can freely set the number of lower processors. A multiprocessor that can eliminate restrictions on the number of processors and, if there is a processor that does not perform substantial processing, reduce the overhead of synchronous processing by that much and achieve high-speed processing It aims to provide a synchronization scheme.

[Configuration of the invention]

(Means for Solving the Problems) In order to achieve the above object, a multiprocessor synchronization system according to the present invention comprises: a message classification unit for classifying synchronization messages sent from a plurality of processor elements according to their types; Is set to check whether the information about the number of synchronous messages or the transmission source for each type classified by the message classification means satisfies the synchronization condition set in the condition setting means. The detecting means and the coincidence detecting means have detected that the information on the number of synchronous messages or the transmission source for each type classified by the message classifying means satisfies the synchronization condition set in the condition setting means. When a synchronization message is generated, the processor elements are synchronized. Message generating means.

(Operation) In the above configuration, when a synchronization message is sent from a plurality of processor elements, the synchronization message is classified according to its type, and information on the number of synchronization messages or transmission source for each type satisfies a predetermined condition. At this time, a synchronization message is generated to synchronize the processor elements.

(Embodiment) FIG. 1 is a block diagram showing an example of a synchronous processor to which a first embodiment of a multiprocessor synchronous system according to the present invention is applied.

The synchronous processor 11 shown in the figure includes eight synchronous discriminators 1 (i, 0) (i = 0 to 7) for processing synchronous messages from each processor element, respectively, and these synchronous discriminators 1 (i, 0). A) a synchronization message generator 2 that determines whether or not the respective processor elements are synchronized based on the processing result of (i) and generates a synchronization message when the respective processor elements are synchronized.

The synchronous discriminator 1 (0,0) includes a reception port 3 (0,0), a decoder 4 (0,0), an enable information setting unit 5 (0,0),
16 cells 6 (0, j) (j = 0 to f),
When a synchronization message is output from the corresponding processor element, the type is determined in response to the output, and the determination result is supplied to the synchronization message generator 2.

Receiving port 3 (0,0) receives the synchronization message output from the corresponding processor element and receives a 4-bit identification number N indicating the type of the synchronization message.
(0,0) and a synchronization message arrival pulse A (0,0) indicating that the synchronization message has arrived, and supplies these to the decoder 4.

When the synchronous message arrival pulse A (0,0) is output from the receiving port 3 (0,0), the decoder 4 (0,0) outputs the identification number N ( 0,
0), and decodes this to selectively generate one of the write signals WR (0, j) and supplies it to the corresponding cell among the cells 6 (0, j).

For example, if the value of the identification number N (0,0) output from the reception port 3 (0,0) is “1” in hexadecimal, the decoder 4 (0,0) outputs the write signal WR (0,1). ) Is generated and this is used for cell 6
To (0,1). If the value of the identification number N (0,0) output from the reception port 3 (0,0) is “f” in hexadecimal, the decoder 4 (0,0) outputs the write signal WR (0, f). ) And supplies it to cell 6 (0, f).

The enable information setting device 5 (0,0) has a 1-bit setting device, and when this setting device is set, it schematically indicates that a synchronization message has been output from the corresponding processor element. 1-bit enable information E (0,0) is generated and supplied to each cell 6 (0, j).

Each of the cells 6 (0, j) is set when the corresponding write signal of the write signal WR (0, j) is supplied as shown in FIG. A JK-type flip-flop 7 which is reset when a corresponding clear signal is supplied, when the flip-flop 7 is set and outputs a synchronization message arrival signal BS (0, j), 5 when the enable information E (0,0) is output
OR gate 8 for generating (0, j).

When the enable information setter 5 (0,0) outputs the enable information E (0,0), while the enable information E (0,0) is supplied, each of the cells 6 (0, j) outputs the synchronization completion signal OK. (0, j) is generated and supplied to the synchronization message generator 2. The enable information setting device 5 (0,0)
When the enable information E (0,0) is not output from the cell, each cell 6 (0, j) receives the synchronization completion signal when the corresponding write signal of the write signal WR (0, j) is supplied.
OK (0, j) is generated and supplied to the synchronization message generator 2. After that, when the corresponding clear signal among the clear signals CL (0, j) is supplied, the synchronization completion signal OK (0, j) is generated. Prevent occurrence.

The other synchronous discriminators 1 (1,0) to 1 (7,0) are each configured similarly to the synchronous discriminator 1 (0,0).

Further, the synchronous message generating unit 2 is provided with the synchronous discriminating units 1
16 AND gates 9 (0, j) receiving the output of (i, 0)
And a synchronizing message generating circuit 10 for generating a synchronizing message M and a clear signal CL (0, j) based on the output of each of these AND gates 9 (0, j). A synchronization message M is output each time a synchronization completion signal OK (i, j) (“i = 0 to 7”) is completely output from each of the synchronization discrimination units 1 (i, 0). And generates a clear signal CL (0, j) corresponding to "j" and supplies the signal to each of the synchronous discriminators 1 (i, 0).

Next, the operation of this embodiment will be described with reference to FIGS.

First, using the synchronous processor 11 according to the present embodiment, as shown in FIG.
When synchronizing 12 (6), one of the synchronization discriminators 1 (i, 0) of the synchronization processor 11, for example, the synchronization discriminator 1 (7,0)
Are disconnected, the enable information setting unit 5 (7, 0) of the synchronous discriminator 1 (7, 0) is set, and each cell 6 (7, 0) is set.
The synchronization complete signal OK (7, j) is output from j).

In this state, each processor element 12 (0) to 12 (12)
If at the timing shown by (6) in FIG. 4 the synchronization message is output, synchronization discriminator between times t ₀ to time t ₁ 1
(I, 0) (i = 0 to 6) operates and the synchronization completion signal OK is sent from the cell 6 (i, 0) (i = 0 to 6) corresponding to the synchronization factor MO.
(I, 0) (i = 0 to 6) is output.

Thus, synchronization input of the message generation unit 2 AND gate 9 (0,0) are all set to "1", synchronization message is generated for synchronization factor MO at time t ₂ by the synchronization message generating circuit 10 each processor element 12 (0)
~ 12 (6), each of these processor elements
Synchronization of 12 (0) to 12 (6) is performed, and then clear signal
CL (0,0) is output to clear cell 6 (i, 0) (i = 0 to 6).

Further, when the same conditions as the above-described operation, the processor element 12 (0) 12 if the timing shown by (6) in FIG. 5 synchronization message is output, synchronization between the time t ₀ to time t ₁ From the cell 6 (i, 1) (i = 0 to 2) of the discrimination unit 1 (i, 0) (i = 0 to 2), the synchronization completion signal OK (i, 1) (i = 0) corresponding to the synchronization factor M1 2) is output and the cell 6 of the synchronous discriminator 1 (i, 0) (i = 3 to 6) is output.
From (i, 2) (i = 3 to 6), a synchronization completion signal OK (i, 2) (i = 3 to 6) corresponding to the synchronization factor M2 is output.

Thereafter, time t ₁ to time t sync discriminating unit 1 between the ₂ (i,
0) Synchronization completion signal OK (i, 2) (i = 3) corresponding to synchronization factor M2 from cell 6 (i, 2) (i = 0-2) of (i = 0-2)
6) is output, and the synchronous discriminator 1 (i, 0) is output.
From the cell 6 (i, 1) (i = 3 to 6) of (i = 3 to 6), a synchronization completion signal OK (i, 1) corresponding to the synchronization factor M1 (i = 3 to 6)
6) is output.

As a result, the inputs of the AND gates 9 (0, 1) and 9 (0, 2) of the synchronous message generator 2 all become "1", and the synchronous
(0,1), together with the broadcast 9 (0,2) output is synchronous message to a synchronous factor M1 is arbitrated at time t ₂ is generated of each processor element 12 (0) -12 (6),
Synchronization message for synchronizing factor M2 at time t ₃ is broadcast is generated in each processor element 12 (0) -12 (6). Thereafter, the synchronization message generation circuit 10 outputs the clear signals CL (0,1) and CL (0,2) to output the cells 6 (i, 1).
(I = 0 to 6) and cell 6 (i, 2) (i = 0 to 6) are cleared.

Thus, in this embodiment, each synchronous discriminating unit 1
The enable information setting unit 5 (0, 0, 0)
0) to 5 (7,0) are provided, and when the number of connected processor elements is less than 8, an enable signal E is output from the enable information setter 5 of the synchronous discriminator 1 to be disconnected, and the synchronization is performed. Synchronization completion signal from each cell 6 of the discriminator 1
Since OK is always output, the system can be operated even when the processor element breaks down or is removed, thereby improving the fault tolerance of the system.

In addition, since the number of processor elements can be set freely and restrictions on the number of processor elements can be eliminated, if there is a processor element that does not perform substantial processing, the synchronous processing is performed accordingly. , The processing speed can be increased by reducing the overhead.

FIG. 6 is a block diagram showing an example of a synchronous processor to which the second embodiment of the multiprocessor synchronous system according to the present invention is applied. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

The difference between the synchronous processor 29 shown in this figure and that shown in FIG. 1 is that the D-type flip-flops 21 (0, 0) to 21 (21) are provided for each of the cells 6 (0, 0) to 6 (7, f). 7, f).

As a result, clock signals are supplied to the flip-flops 21 (0,0) to 21 (7, f) while sequentially supplying enable information E (0,0) to E (7, f) via the enable information input terminal 22. Are sequentially supplied and sequentially shifted, whereby enable information E (0,0) to E (7, f) are individually set for each of the flip-flops 21 (0,0) to 21 (7, f). can do.

Thus, in this embodiment, each cell 6 (0,0) to
Since enable information E (0,0) to E (7, f) can be individually supplied to 6 (7, f), the number of connected processor elements is less than eight as in the first embodiment. At this time, the enable information E is stored in each cell 6 of the synchronous discrimination unit 23 that is not connected.
To output a synchronization completion signal OK from these cells 6 at all times, so that the system can be operated even when the processor element fails or is removed, and the fault tolerance of the system is improved. Can be improved.

In this embodiment, the synchronization of the processor element to which a plurality of programs are mapped can be achieved.

For example, as shown in FIG. 7, the processor elements 12 (0) to 12 (6) are connected to the respective synchronous discriminators 23 (0,0) to 23 (6,0) of the synchronous processor 29, and Processing X and Y are performed in the processor elements 12 (0) to 12 (2), and processing X and Y are performed in the processor elements 12 (3) to 12 (6).
When Z is mapped, these processors 12 (1) to 12 (6) are synchronized in the following procedure.

First, the synchronization factor MO is assigned to the process X, and the synchronization factor is assigned to the process Y.
If the synchronization factors M2 and M3 are present in the process Z and the process Z, respectively, the enable information E (0,0) to E (7, f) is scanned in via the enable information input terminal 22 to scan each flip-flop. The values are set in the cells 21 (0,0) to 21 (7, f), and the cells 6 (i, j) (i = 0 to 2, j = 2,3), 6 as shown in FIG.
From (i, 1) (i = 3 to 6) and 6 (7, j) (j = 0 to f), a synchronization completion signal OK (i, j) (i = 0 to 2, j = 2, 3), O
K (i, 1) (i = 3 to 6) and OK (7, j) (j = 0 to f) are output.

In this state, if the ninth time t the processor elements 12 (0) ₀ as shown in FIG. 12 (6) synchronization message for synchronizing factors MO from the output, the synchronization judgment unit 23 (0,
A synchronization completion signal OK (i, 0) (i = 0 to 6) is output from each cell 6 (i, 0) (i = 0 to 6) of the cells 0 to 23 (6, 0), and the synchronization message generation unit The inputs of the AND gates 9 (0, 0) of all 2 are "1". Thus, the time t ₁ in the synchronization message generating circuit 10 which each processor element 12 generates a synchronization message for synchronizing factors MO (0) to 12
Broadcast to (6).

Further, 10 each processor element 12 at time t ₀ as shown in FIG. (0), 12 synchronization messages for the (2) synchronization factor M1 is also synchronous message to the synchronous factor M2 from each processor element 12 (4), When a synchronization message for the synchronization factor M3 is output from the processor elements 12 (5) and 12 (6), the synchronization determination units 23 (0,0), 23 (2,0) and 23 (2 4,0) to 23 (6,0) cells 6 (0,1), 6 (2,1), 6 (4,2), 6 (5,3),
6 (6, 3) is the synchronization completion signal OK (0, 1), OK (2, 1), OK
(4,2), OK (5,3), OK (6,3) are output.

Thereafter, the time t ₁ synchronization messages for synchronizing factors M1 from the processor element 12 (1) in is also the processor element 12 (3), 12 (5), the synchronization factor from 12 (6)
When a synchronization message for M2 and a synchronization message for synchronization factor M3 are output from the processor element 12 (4), the synchronization determination units 23 (1, 0), 2
3 (3,0) to 23 (6,0) cells 6 (1,1), 6 (3,2),
6 (4, 3), 6 (5, 2), 6 (6, 2) are synchronization completion signals OK
(1,1), OK (3,2), OK (4,3), OK (5,2), OK (6,
2) is output.

As a result, the inputs of the AND gates 9 (1, 0) and 9 (2, 0) of the synchronous message generator 2 all become “1”, and the time
t ₂ in the synchronization message generating circuit 10 is sequentially broadcast to each processor element 12 arbitrates these (0) -12 (6) to generate a synchronization message for synchronizing factors M1, M2. At this time, since the synchronization message for the synchronization factor M3 has not been output from the processor 12 (3),
A synchronization message for this synchronization factor M3 is not broadcast.

FIG. 11 is a block diagram showing an example of a synchronous processor to which a third embodiment of the multiprocessor synchronous system according to the present invention is applied.

A synchronization processor 30 shown in this figure is a receiving unit that receives a synchronization message output from each processor element.
32 and a decoder 33 for decoding the output of the receiving unit 32
A counting unit 34 for counting the output of the decoder 33;
An active port number setting unit 35 in which the active port number A is set, and a comparing unit that compares the active port number A set in the active port number setting unit 35 with each count value of each of the counting units 34. 36 and this comparison section
A synchronization message generation circuit 37 for generating a synchronization message based on the comparison result of 36.

Upon receiving the synchronization message from each processor element, the receiving unit 32 receives the synchronization message registration requests R (0) to R (7) of one bit and the identification numbers N (0) to N (7) of four bits. And eight receiving ports respectively generating
38 (0) to 38 (7) and each of these receiving ports 38 (0) to
From 38 (7), synchronous message registration request R (0) to R
When (7) is output, the arbitration circuit 39 arbitrates this to generate a capture selection signal V and an enable signal P, and based on the capture selection signal V output from the arbitration unit 39, the reception port 38 ( And a multiplexer 40 for selectively taking in the identification numbers N (0) to N (7) output from 0) to 38 (7). The multiplexer 40 arbitrates the synchronization messages when they are output from the respective processor elements. While being fetched sequentially, it is supplied to the decoder 33 together with the enable signal P.

When the enable signal P is supplied from the arbitration circuit 39, the decoder 33 captures and decodes the identification number output from the multiplexer 40 and generates any one of the count pulses C (0) to C (f). This is supplied to the counting unit 34.

The counting section 34 includes 16 counters 41 (0) to 41 (f) for counting the count pulses C (0) to C (f) output from the decoder 33, respectively. When (0) to C (f) are supplied, they are counted, and the respective counting results are supplied to the comparing unit 36. When the clear signals CL (0) to CL (f) are supplied, the counters 41 (0) to 41 (f) clear the counting results of the corresponding ones.

The comparing unit 36 determines the number of active ports A set in the number-of-active-ports setting unit 35 and the respective counters 41.
16 comparators 42 (0) to 42 (f) for comparing the count values of the counters 41 (0) to 41 (f) with the counters 41 (0) to 41 (f). When any of the numerical values is equal to or greater than the number of active ports A, a comparator corresponding to this counter generates a synchronization message generation request signal GR and supplies it to the synchronization message generation circuit 37.

When any of the synchronization message generation request signals GR (0) to GR (f) is supplied from the comparison unit 36, the synchronization message generation circuit 37 generates a synchronization message corresponding to the synchronization message generation request signal GR. This is supplied to each processor element, and the clear signals CL (0) to CL (f) corresponding to the synchronous message generation request signal GR are provided.
Is generated and supplied to the counting unit 34.

Next, the operation of this embodiment will be described with reference to FIGS.

First, using the synchronization processor 30 according to this embodiment,
As shown in FIG. 12, seven processor elements 12 (0)-
When synchronizing 12 (6), any one of the reception ports 38 (0) to 38 (7) of the synchronization processor 30, for example, the reception port 38 (7) is disconnected, and the remaining reception is performed. The number equal to the number of the ports 38 (0) to (6) (in this case, the value “7”) is set in the number-of-active-ports setting device 35, and this is set as the number A of the active ports, and each of the comparators 42 (0) to 42
Enter it in (f).

In this state, each processor element 12 (0) to 12 (12)
If the synchronization message for the synchronization factor MO is output from (6) at the timing shown in FIG.
(0) to 38 (7) detect this and output synchronous message registration requests R (0) to R (7), respectively.

As a result, the arbitration circuit 39 arbitrates these, and fetches one of them, for example, the synchronization message registration request R (0), and generates the fetch selection signal V corresponding to the synchronization message registration request R (0). Multiplexer 40
Receives the identification number N (0) which is the output of the reception port 38 (0), generates an enable signal P at this time, and captures the identification number N (0) captured by the multiplexer 40 into the decoder 33. Let

The decoder 33 decodes the identification number N (0) to generate a count palace C (0), and outputs it to a counter 41 (0).
And the count value of the counter 41 (0) is incremented.

Next, when this operation is completed, the arbitration circuit 39 arbitrates the remaining synchronous message registration requests R (1) to R (6),
One of them, for example, the synchronous message registration request R (1) is taken in, and the synchronous message registration request R (1)
Is generated, and the multiplexer 40 outputs the identification number N, which is the output of the reception port 38 (1), to the multiplexer 40.
(1) is taken in. At this time, the arbitration circuit 39 also generates an enable signal P to cause the decoder 33 to take in the identification number N (1) taken in by the multiplexer 40, and the count pulse C (0) obtained by the decoding operation. The count value of the counter 41 (0) is incremented.

Hereinafter, similarly, the arbitration circuit 39 sets the reception port 38 (2)
ID numbers N (2) to N (6) output from .about.38 (6)
Are sequentially taken in by the multiplexer 40 and supplied to the decoder 33, and the count value of the counter 41 (0) is incremented by the count pulse C (0) obtained by the decoding operation.

When the count value of the counter 41 (0) is incremented by the decoding operation of the identification number N (6) output from the receiving port 38 (6) to become “7”, the counter 41 (0) The comparator 42 (0), which compares the count value of the above with the output of the active port number setting unit 35, detects that these values have become equal, and outputs a synchronization message generation request signal GR (0).

As a result, the synchronization message generation circuit 37 generates a synchronization message for the synchronization factor M (0), broadcasts it to each of the processor elements 12 (0) to 12 (6), and simultaneously generates the synchronization message generation request signal GR (0). ), And generates a clear signal CL (0) corresponding to the counter 42.
Clear (0).

Further, if the synchronization message is output from each of the processor elements 12 (0) to 12 (6) at the timing shown in FIG. 14 under the same conditions as the above-described operation, the time t ₀ to t each receiving port 38 (0) between _1-38
The output of (6) is arbitrated by the arbitration circuit 39 and is sequentially selected and supplied to the decoder 40.

Here, if the outputs of the receiving ports 38 (0) to 38 (6) are sequentially selected in the illustrated order, the decoder 40 generates the count pulses C (2) and C (1) alternately to generate the counter 41.
(2) The count values of (1) are alternately incremented.

Then if the process is terminated, between times t ₁ ~t _2, similar arbitration processing be executed according counter 41 (1), the count value of 41 (2) is incremented alternately.

When the count value of the counter 41 (2) by the decoding operation of the identification number N output from the receiving port 38 (5) (5) is incremented by the value becomes "7" (time t _2), this Comparator 42 (2) comparing the count value of counter 41 (2) with the output of active port number setting device 35
Detects that these values have become equal, and outputs a synchronous message generation request signal GR (2).

As a result, the synchronization message generation circuit 37
A synchronization message for M2 is generated and broadcast to each processor element 12 (0) to 12 (6).
A clear signal CL (2) corresponding to the synchronous message generation request signal GR (2) is generated and this is output to the counter 41.
Clear (2).

Thereafter, if the count value of the counter 41 (1) is incremented by the decoding operation of the identification number N (6) output from the reception port 38 (6) to become "7" (time
t ₃ ), the comparator 42 (1) detects this and outputs a synchronization message generation request signal GR (1).

As a result, the synchronous message generation circuit 37
A synchronization message for M1 is generated and broadcast to each processor element 12 (0) to 12 (6),
A clear signal CL (1) corresponding to the synchronous message generation request signal GR (1) is generated, and this is output to the counter 41.
Clear (1).

As described above, in this embodiment, the number of synchronous messages output from each processor element for the same synchronous factor is counted, and the count value for each synchronous factor is set to the number of active ports set in the active port number setting unit 35. When the value coincides with A, a synchronization message for each synchronization factor is generated and broadcast to each processor element, so that the processor element breaks down or is removed as in the first embodiment. In such a case, the system can be operated, and thereby the fault tolerance of the system can be improved.

In addition, since the number of processor elements can be freely set to eliminate restrictions on the number of processors, if there is a processor element that does not perform substantial processing, the overhead of synchronous processing is reduced accordingly. Higher processing speed can be achieved.

Further, in this embodiment, since the synchronous message is processed serially, there is a demerit that the processing speed is slightly lower than in the first and second embodiments described above, but a large amount of hardware can be greatly reduced. Benefits can be obtained.

FIG. 15 is a block diagram showing an example of a synchronous processor to which a fourth embodiment of the multiprocessor synchronous system according to the present invention is applied. In this figure, parts corresponding to the respective parts in FIG. 11 are denoted by the same reference numerals.

The synchronous processor 50 shown in this figure differs from that shown in FIG. 11 in that active port number setting registers 52 (0) to 52 (f) are provided for each of the comparators 42 (0) to 42 (f). It is.

Then, while sequentially supplying the active port numbers A (0) to A (f) via the active port number input terminal 53, each of the active port number setting registers 52 (0) to 52 (f).
Clock pulse to the active port number A
By sequentially shifting (0) to A (f), the active port numbers A (0) to A (f) are individually set for the respective active port number setting registers 52 (0) to 52 (f). I have to.

Thus, in this embodiment, each of the comparators 42 (0) to 42 (0) to
Since the number of active ports A (0) to A (f) can be supplied to 42 (f), the system operates even when the processor element fails or is removed as in the first embodiment. This can improve the fault tolerance of the system.

Further, in this embodiment, as in the above-described second embodiment, it is possible to synchronize the processor elements to which a plurality of programs are mapped.

For example, as shown in FIG. 16, each of the processor elements 12 (0) to 12 (6) is connected to each of the reception ports 38 (0) to 38 (6) of the synchronous processor 50, and the processor element 12 (0) is connected. When processings X and Y are mapped to the processing elements 12 (3) to 12 (6) and processings X and Z are mapped to the processor elements 12 (3) to 12 (6), these processors 12 (1 ) To 12 (6) synchronization.

First, the synchronization factor M0 is used for the process X, and the synchronization factor is used for the process Y.
If H1 and various synchronization factors M2 and M3 exist in the process Z, the number of synchronization messages for the synchronization factor M0 among the synchronization messages output from the processor elements 12 (0) to 12 (6). Is "7", the number of synchronization messages for the synchronization factor M1 is "3", the number of synchronization messages for the synchronization factor M2 is "4", and the number of synchronization messages for the synchronization factor M3 is "4". Each processor element 12
Among the synchronization messages output from (0) to 12 (6), the number of synchronization messages for the other synchronization factors M4 to Mf is “0”.

Therefore, as shown in FIG. 17, the active port number setting register 52 is connected via the active port number input terminal 53.
“0” is set to (0) and the number of active ports setting register 52
"1" is set to (1) and the number of active ports setting register 52
“2” is set in (2) and the number of active ports setting register 52
“4” is set in (3) and the number of active ports setting register 52
A value other than "0", for example, "15" is set in (4) to 52 (f).

If in this way, the synchronization factor from the 18 processor elements 12 at time t ₀ as shown in FIG. (0) -12 (6)
Arbitration circuit when synchronization message for M0 is output
The reference numeral 39 designates a multiplexer 40 for sequentially taking the identification numbers N (0) to N (6) output from the reception ports 38 (0) to 38 (6) and supplying the same to the decoder 33, and a count obtained by the decoding operation. Counter 41 with pulse C (0)
The count value of (0) is incremented.

When the count value of the counter 41 (0) is incremented by the decoding operation of the identification number N (6) output from the receiving port 38 (6) to become “7”, the counter 41 (0) Comparator 42 that compares the count value of the above with the output of the active port number setting register 52 (0).
(0) detects that these values have become equal, and outputs a synchronous message generation request signal GR (0).

As a result, the synchronization message generation circuit 37
A synchronization message for M0 is generated and broadcast to each processor element 12 (0) to 12 (6).
A clear signal CL (0) corresponding to the synchronous message generation request signal GR (0) is generated to clear the counter 41 (0).

Further, when the same conditions as the above-described operation, if the processor element 12 (0) at the timing indicated from 12 (6) in FIG. 14 synchronization messages is output, at time t ₁ in the same manner as the operation described above counter 41 (1) is incremented to the value "1", the at time t ₂ the counter 41 (1) becomes is further incremented value "2". Thereafter, the counter 41 (3) is incremented value "1" at time t _3, also the time t ₄ in the counter 41 (2) is incremented to the value "1", and at time t _5, t ₆ The counter 41 (2) is sequentially incremented to a value "3".

Then, if the counter 41 (1) is incremented value "3" at time t _7, the comparator 41 (1) is detected by synchronous message generation request signal GR from these values become equal
(1) is output.

As a result, the synchronization message generation circuit 37
A synchronization message for M1 is generated and broadcast to each processor element 12 (0) to 12 (6),
A clear signal CL (1) corresponding to the synchronous message generation request signal GR (1) is generated, and this is output to the counter 41.
Clear (1).

Further, if the counter 41 at time t ₈ (2) is incremented to the value "4", comparator 42 (2) outputs a was detected synchronous message generation request signal GR (2) which.

As a result, the synchronization message generation circuit 37
A synchronization message for M2 is generated and broadcast to each processor element 12 (0) -12 (6),
A clear signal CL (2) corresponding to the synchronous message generation request signal GR (2) is generated and this is output to the counter 41.
Clear (2). At this time, since the number of synchronization messages for the synchronization factor M3 is insufficient, the synchronization message for the synchronization factor M3 is not broadcast.

Further, in this embodiment, since the synchronous message is processed serially, there is a demerit that the processing speed is slightly lower than in the first and second embodiments described above, but a large amount of hardware can be greatly reduced. Benefits can be obtained.

In each of the embodiments described above, the synchronous processor 1
Synchronization messages output from 1, 29, 30, and 50 are broadcast to the processor elements 12 (0) to 12 (6). However, as shown in FIG. Even if the processors 11, 29, 30, and 50 are connected in multiple stages, there are many cases.

〔The invention's effect〕

As described above, according to the present invention, the system can be operated even when the processor element or the lower-level synchronous processor fails or is removed, so that the fault tolerance of the system can be improved. In addition, the number of processor elements and the number of lower-order synchronous processors can be set freely, thereby eliminating restrictions on the number of processors. Further, when there is a processor element that does not perform substantial processing, the overhead of the synchronous processing can be reduced by that much, and the processing can be speeded up.

[Brief description of the drawings]

FIG. 1 shows a first example of a multiprocessor synchronization system according to the present invention.
FIG. 2 is a block diagram showing an example of a cell shown in FIG. 1; FIG. 3 is a block diagram for explaining an operation example of the first embodiment;
FIG. 5 is a timing chart for explaining one operation example of the first embodiment, FIG. 5 is a timing chart for explaining another operation example of the first embodiment, and FIG. 6 is a multiprocessor synchronization system according to the present invention. FIG. 7 is a block diagram showing an example of a synchronous processor according to the second embodiment, FIG. 7 is a block diagram for explaining an operation example of the second embodiment, and FIG. 8 is a diagram for explaining an operation example of the second embodiment. FIG. 9 is a timing chart for explaining one operation example of the second embodiment, FIG. 10 is a timing chart for explaining another operation example of the second embodiment, and FIG. 11 is the present invention. FIG. 12 is a block diagram showing an example of a synchronous processor according to a third embodiment of the multiprocessor synchronization system according to the present invention, FIG. 12 is a block diagram for explaining an operation example of the third embodiment, and FIG. 13 is an operation of the third embodiment. Timing chart to illustrate the example FIG. 14 is a timing chart for explaining another operation example of the third embodiment. FIG. 15 is a block diagram showing an example of a synchronous processor according to a fourth embodiment of the multiprocessor synchronization system according to the present invention. FIG. 17 is a block diagram for explaining an operation example of the fourth embodiment, FIG. 17 is a table diagram for explaining an operation example of the fourth embodiment, and FIG.
FIG. 19 is a timing chart for explaining one operation example of the embodiment, FIG. 19 is a timing chart for explaining another operation example of the fourth embodiment, and FIG. 20 is a timing chart of a multiprocessor synchronization system according to the present invention. FIG. 21 is a block diagram showing another connection example, and FIG. 21 is a block diagram for explaining a conventional synchronous processor. 1 (0,0) to 1 (7,0) synchronization discriminator 2 synchronization message generator 6 (0,0) to 6 (7, f) cell 9 (0,0) to 9 ( 0, f) ... AND gate 11 ... Synchronous processor

Claims (5)

(57) [Claims] 1. Synchronous messages sent from a plurality of processor elements are classified according to their types, and when the number of synchronous messages for each type or information relating to a transmission source satisfies a predetermined condition, a synchronous message is generated. A multiprocessor synchronization method, wherein processor elements are synchronized. 2. The multiprocessor synchronization system according to claim 1, wherein when a synchronization message is output from each of the processor elements specified in advance, it is determined that a predetermined condition is satisfied, and the respective processor elements are synchronized. 3. When a predetermined type of synchronization message is output from each of the processor elements specified in advance, it is determined that a predetermined condition is satisfied, and the processor elements are synchronized with respect to the type. Multiprocessor synchronization scheme as described. 4. When the number of synchronization messages output from each processor element for each type becomes equal to or greater than a predetermined number, it is determined that a predetermined condition is satisfied, and the respective processor elements are synchronized. 2. The multiprocessor synchronization system according to 1. 5. When the number of synchronization messages output from each processor element for each type is equal to or greater than the number for each type specified in advance, it is determined that a predetermined condition is satisfied, and each processor element is determined for the type. 2. The multiprocessor synchronization method according to claim 1, wherein the synchronization is performed.