JP2765366B2 - Integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit which employs a so-called scan path method among design techniques for testability.

In recent years, the scale of an integrated circuit has been increased, and it has become difficult to create a test pattern. Therefore, the use frequency of the automatic test pattern generation by the scan path method is increasing, but it is desired to improve the failure detection rate.

[0003]

2. Description of the Related Art Conventionally, as an integrated circuit designed by adopting a scan path system, there is known an integrated circuit whose main part is shown in a block diagram in FIG.

In the figure, 1 is a chip body, 2 is a combination circuit,
3 _1, 3 ₂ ··· 3 _n is the scan-in terminal with a master-slave flip-flop (hereinafter, SFF hereinafter) is, in these _{SFF3 1, 3 2 ··· 3 n} , PR
And CL are a preset terminal and a clear terminal which are asynchronous signal input terminals, respectively.

4 ₁ ... 4 _m are general input terminals, 5 ₁
... 5 _k is a general output terminal, 6 is scan-in data S
A scan-in terminal to which DI is input and a scan-out terminal 7 to which scan-out data SDO is output.

[0006] 8 is SFF3 _1, 3 ₂ ··· 3 _n clock signals for writing scan-in data SDI to the master latch of, A clock signal input terminal to which the so-called A clock signal XACK is input.

[0007] 9 SFF3 _1, 3 ₂ ··· 3 _n clock signal for data transfer the output from the master latch to the slave latch, the B clock signal input terminal to which the so-called B clock signal BCK is inputted It is.

Reference numeral 10 denotes a clock signal in a test clock mode, that is, a mode in which all the SFFs 3 ₁ , 3 ₂ ... 3 _n in the integrated circuit are operated as if they were regarded as external terminals and the entire circuit is operated. Test clock signal X
A test clock signal input terminal to which TCK is input.

In such an integrated circuit, the operation in the integrated circuit in the test mode is given in two modes. The first mode, scan mode, i.e., all SFF3 _1, 3 ₂ ··· 3 _n in an integrated circuit to the shift register configuration, the data serially to these SFF3 _1, 3 ₂ ··· 3 _n input Output mode, and the second mode is
The test clock mode described above, that is, a mode in which all the SFFs 3 ₁ , 3 ₂ ... 3 _n in the integrated circuit are regarded as if they are part of external terminals, and the entire circuit is operated.

That is, in such an integrated circuit, the test is first performed in the scan mode, and the SFFs 3 ₁ , 3 _2.
After the scan-in data SDI is scanned into 3 _n , the test clock mode is set, and the entire circuit is operated by the general input and the scanned-in scan-in data SDI.
3 _1, 3 ₂ ... 3 simultaneously the data written to the _n scan out SFF3 _1, 3 ₂ ... 3 scans in the next scan-in data SDI to _n, below, procedure, repeating the It is performed by

[0011]

In such a conventional integrated circuit, in the scan mode, the SFFs 3 ₁ , 3 _2.
3 If the clear signal either or when or clear terminal CL preset signal is input to all of the preset terminal PR of the _n is input, the scan-in data SDI and scan-out data SDO is destroyed by preset operation or clearing operation In some cases.

Therefore, in the scan mode, it is necessary to inhibit the input of the preset signal to the preset terminal PR and the input of the clear signal to the clear terminal CL of the SFFs 3 ₁ , 3 ₂ ... 3 _n .

When the output terminal of one of the SFFs is connected to the preset terminal PR or the clear terminal CL of the other SFF, the output signal of one of the SFFs in the test clock mode. The preset terminal PR or the clear terminal CL becomes active, and data written in another SFF may be destroyed in synchronization with the test clock signal XTCK.

In this case, as in the scan mode, the SFF is also used in the test clock mode.
When the input of the preset signal to the preset terminal PR and the input of the clear signal to the clear terminal CL of 3 ₁ , 3 ₂ ... 3 _n are prohibited, the data is written to the SFF in synchronization with the test clock signal XTCK. Data destruction can be prevented.

However, when such control is performed, SF
F3 ₁ , 3 ₂ ... 3 _n The failure of the preset terminal PR, the failure of the clear terminal CL, and these preset terminals PR
Alternatively, there is a problem that a failure transmitted only to the clear terminal CL cannot be detected.

In view of the above, the present invention prevents the scan-in data and the scan-out data from being destroyed by the asynchronous signal in the scan mode,
It is an object of the present invention to provide an integrated circuit capable of detecting a failure of the asynchronous signal input section of F and a failure transmitted only to the asynchronous signal input section and improving a failure detection rate.

[0017]

An integrated circuit according to the present invention comprises a combinational circuit and a plurality of SFFs.
In the test mode, the SFF has a shift register configuration, and a scan mode in which data is serially input / output to / from these SFFs and a test clock mode in which the SFF is regarded as a part of an external terminal to operate the entire circuit are provided. It is to improve the circuit.

According to the present invention, an asynchronous signal input section is provided for each of the master latch and the slave latch of the SFF, and the input of an asynchronous signal to the asynchronous signal input section of the master latch and the slave latch of the SFF is prohibited in the scan mode. , Test clock mode, SFF
And an asynchronous signal input control unit for prohibiting the input of the asynchronous signal to the asynchronous signal input unit of the slave latch of the SFF.

[0019]

According to the present invention, in the scan mode, the input of the asynchronous signal to the asynchronous signal input sections of the master latch and the slave latch of the SFF is inhibited by the asynchronous signal input control section, so that the scan-in data and the scan-out data are asynchronous. It is not destroyed by signals.

On the other hand, in the test clock mode, the input of an asynchronous signal to the asynchronous signal input section of the master latch of the SFF is permitted by the asynchronous signal input control section, and the asynchronous signal input to the asynchronous signal input section of the slave latch of the SFF is performed. Input is prohibited, the data written in the SFF is prevented from being destroyed by the asynchronous signal, the entire circuit is operated, and the failure of the asynchronous signal input section of the SFF and the failure transmitted only to the asynchronous signal input section can be detected. It becomes possible.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, portions corresponding to those in FIG. 8 are denoted by the same reference numerals, and redundant description thereof will be omitted.

FIG. 1 is a block diagram showing an essential portion of an embodiment of the present invention, in _{FIG., 12 1, 12 2 ··· 12} n each master latch 12 _1A, 12 _2A ··· 12 _nA and slave Latches 12 _1B , 12 _2B ... 12 _nB are SFFs each provided with a preset circuit and a clear circuit.

Here, the MPR is the master latch 12 _1A , 1
2 _2A ... 12 _nA preset terminal, MCL is a master latch 12 _1A , 12 _2A ... 12 _nA clear terminal, SPR
_Are preset terminals of slave latches 12 _1B , 12 _2B ... 12 _nB , and SCL is slave latches 12 _1B , 12 _2B.
• Indicates a 12 _nB clear terminal. Note that these preset terminals MPR, SPR and clear terminals MCL, SC
L is active at "0".

Further, FIG. 2 is a diagram showing in more detail the SFF12 ₁ part, 13 ₁ SFF12 ₁ preset terminal MPR, the input and clear terminal MCL preset signal to the SPR, the input of the clear signal to SCL Is an asynchronous signal input control unit for prohibiting and permitting.

Note that 15 ₁ , 16 ₁ , 17 ₁ , 18 ₁ are OR
Circuit, PR is a preset signal, CL is a clear signal, TM
Is a test mode signal, SM is a scan mode signal. The test mode signal TM is "1" in the test mode, "0" in the normal mode (user mode), and the scan mode signal SM is the scan mode. At the time, it is set to "1", and at the time of the test clock mode, it is set to "0".

[0026] As shown in this Figure 2, in this embodiment, the SFF12 ₁ and the asynchronous signal controller 13 ₁ is understood as one cell 14 _1. SFF12 ₂ ... 12
_{The same} applies to _n .

This embodiment will be described with reference to FIG. 2. In the test mode, the test mode signal TM
Is set to “1”, so that the outputs of the OR circuits 15 ₁ and 18 ₁ are fixed to “1” regardless of the preset signal PR and the clear signal CL, and the SFF1 of the preset signal PR
2 inputs and input to the clear terminal SCL of SFF12 ₁ of the slave latch 12 _1B clear signal CL to the preset terminal SPR of ₁ of the slave latch 12 _1A is prohibited.

In particular, during the test mode and the scan mode, the scan mode signal SM is set to "1", so that the outputs of the OR circuits 16 ₁ and 17 ₁ are independent of the preset signal PR and the clear signal CL. is fixed to "1", SFF12 input ₁ to SFF12 ₁ of the master latch 12 _1A of clear terminal MCL input and the clear signal CL to the master latch 12 _1A preset terminal MPR preset signal PR is prohibited.

That is, referring to FIG. 1, in the scan mode, the SFFs 12 ₁ and 1 of the preset signal PR are used.
2 _2, ... to 12 _n master latch 12 _1A, 12 _2A ··· 1
2 _nA and the slave latch 12 _1B, 12 _2B ··· 12 _nB preset terminal MPR, SFF12 ₁ of the input and the clear signal CL to the SPR, 12 ₂ ··· 12 _n to the master latch 12 _1A, 12 _2A ··· 12 _nA and slave latch 1
2 _1B , 12 _2B ... 12 _nB clear terminals MCL, SCL
Input to is prohibited.

Therefore, according to the present embodiment, in the scan mode, the scan-in data SDI and the scan-out data SDO are supplied with the preset signal PR and the clear signal CL.
Can be prevented from being destroyed.

Further, when described using FIG. 2, in the test mode, even during the test clock mode, since the test mode signal TM is "1", SFF12 ₁ of the slave latch 12 of the preset signal PR Input to preset terminal SPR of _1B and SF of clear signal CL
F12 ₁ input to the clear terminal SCL of the slave latch 12 _1B is prohibited.

Further, in the test clock mode, since the scan mode signal SM is set to "0", the preset signal PR and the clear signal CL is prioritized, preset terminal MPR of SFF12 ₁ of the master latch 12 _1A of the preset signal PR To the input and S of the clear signal CL
FF12 input to the _first master latch 12 _1A of the clear terminal MCL is permitted.

Therefore, according to the present embodiment, the SFF1
_{2 1,} 12 2 ··· 12 _n written data is prevented from being destroyed by the preset signal PR and the clear signal CL can operate the entire circuit, SFF12
₁ , 12 ₂ ... 12 _n master latches 12 _1A , 12 _2A.
..12 _nA preset terminal MPR failure, clear terminal MCL failure, preset terminal MPR, clear terminal M
It is possible to detect a fault that is transmitted only to the CL and improve the fault detection rate.

Here, in the test clock mode, the SFFs 12 ₁ and 12 ₂ are synchronized with the test clock signal XTCK.
... If the data written in 12 _n is output due to the operation timing before shifting to the scan mode, the data written in the output destination SFF may be destroyed. We need to stop this.

Here, the SFFs 12 ₁ , 12 ₂ ... 12 _n
If the scan mode signal SM is set to “1” before the data written in the SFF is output, the SFF 12 ₁ , 1
The output of the data written in 2 ₂ ... 12 _n can be prevented. In this case, although not shown in FIGS. It is necessary to set the mode signal XSM to “0”.

However, when the combination circuit 2 includes a bus input / output circuit using the scan mode signal XSM as a control signal, it is necessary to set the scan mode signal XSM to "0" in the test clock mode. There's a problem.

In the scan mode, only the scan path portion is guaranteed to operate, and a bus conflict may occur. Therefore, in the scan mode, the scan mode signal XSM is set to "0" and the bus input / output is set to "0". The circuit is fixed in the input state, and in the test clock mode,
This is because it is necessary to set the scan mode signal XSM to "1" and control the bus input / output circuit so that it can take either the input state or the output state.

[0038] In such a case, if Shimese on behalf of cell 14 ₁ shown in FIG. 2, as shown in FIG. 3, it is necessary to configure the circuit. 3, parts corresponding to those in FIG. 2 are denoted by the same reference numerals.

In the figure, XTST is a test mode signal, 1
9, 20 are I / O circuits, 21 is a scan mode signal XS
M is a circuit including a bus input / output circuit used as a control signal, 22 to 26 are through gates, 27 to 29 are inverters, 30 is a NAND circuit, 31 is a NOR circuit, 32, 3
3 is an OR circuit. Note that one input terminal 30A of the NAND circuit 30 is fixed to “1”.

In the test clock mode, the circuit 34 surrounded by the dashed line has the SFF 12 _{1 of the} preset signal PR.
A circuit for performing control to prohibit the input to the clear terminal MCL of SFF12 ₁ of the master latch 12 _1A preset terminals MPR and the clear signal CL of the master latch 12 _1A.

That is, in this example, as shown in FIG. 4, when the test mode signal XTST is set to "0" and the scan mode signal XSM is set to "0" and the scan mode is set, N
The output of the AND circuit 30 is set to "1", the bus input / output circuit included in the circuit 21 is fixed to the input state, and the occurrence of bus conflict is prevented.

In this case, the output of the inverter 27 becomes "1" and the output of the NOR circuit 31 becomes "0".
Output of OR circuit 33 = “0”, output of inverter 28,
That is, the scan mode signal SM = "1", SF of the input and the clear signal CL to the preset terminal MPR of SFF12 ₁ of the master latch 12 _1A of the preset signal PR
F12 inputs to the _first master latch 12 _1A of clear terminal MCL is prohibited.

On the other hand, as shown in FIG. 5, test mode signal XTST = "0" and scan mode signal XS
When M = “1” and the test clock mode is set,
The output of the NAND circuit 30 is set to “0”, and the bus input / output circuit included in the circuit 21 is released from the state fixed to the input state.

In this case, the A clock signal XACK
= If the state is “0”, the output of the NOR circuit 31 =
When “1”, the output of the OR circuit 33 = “1”, the inverter 2
8 outputs, that is, the scan mode signal SM is set to "0", the priority preset signal PR and the clear signal CL is input and the clear signal CL to the preset terminal MPR of SFF12 ₁ of the master latch 12 _1A of the preset signal PR SFF12 input to the _first master latch 12 _1A of the clear terminal MCL is permitted.

Here, as shown in FIG. 6, when the state of the A clock signal XACK = "1", the output of the NOR circuit 31 = "0", the output of the OR circuit 33 = "0", and the output of the inverter 28 Output, that is, the scan mode signal SM =
In "1", the input to SFF12 ₁ of the master latch 12 _1A of clear terminal MCL input and the clear signal CL to the preset terminal MPR of SFF12 ₁ of the master latch 12 _1A of the preset signal PR is inhibited.

Therefore, according to the circuit shown in FIG. 3, when the combinational circuit 2 includes a bus input / output circuit using the scan mode signal XSM as a control signal, the test clock signal is used in the test clock mode. In the case where data written to the SFFs 12 ₁ , 12 ₂ ... 12 _n in synchronization with XTCK is output due to the operation timing before shifting to the scan mode, this can be prevented. .

If the combinational circuit 2 does not include a bus input / output circuit using the scan mode signal XSM as a control signal, there is no need to consider a bus conflict during the scan mode. As shown in (1), the scan mode signal SM can be controlled to "1" by the scan mode signal XSM. In addition, 35 is an I / O circuit, 36 is a through gate, and 37 is an inverter.

[0048]

As described above, according to the present invention, the SFF
Asynchronous signal input sections are provided for the master latch and the slave latch, respectively. In the scan mode, the input of asynchronous signals to the asynchronous signal input sections of the master latch and the slave latch of the SFF is prohibited. In addition to preventing destruction by the asynchronous signal, in the test clock mode, the input of an asynchronous signal to the asynchronous signal input section of the master latch of the SFF is permitted, and the asynchronous operation of the slave latch of the SFF to the asynchronous signal input section is enabled. Since the input of the signal is prohibited, the internal circuit is operated without destroying the data written in the SFF, and the failure of the asynchronous signal input portion of the SFF and the failure transmitted only to the asynchronous signal input portion are detected. The failure detection rate can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a diagram showing a flip-flop and an asynchronous signal input control unit included in an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a circuit for generating a scan mode signal SM together with other circuits.

FIG. 4 is a diagram for explaining the operation of the circuit shown in FIG. 3;

FIG. 5 is a diagram for explaining the operation of the circuit shown in FIG. 3;

FIG. 6 is a diagram for explaining the operation of the circuit shown in FIG. 3;

FIG. 7 is a diagram showing another example of a circuit for generating a scan mode signal SM.

FIG. 8 is a block diagram showing a main part of a conventional integrated circuit configured by employing a scan path method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Chip body 2 Combination circuit 12 ₁ Master-slave type flip-flop with scan-in terminal 12 ₂ Master-slave type flip-flop with scan-in terminal 12 Master-slave type flip-flop with _n scan-in terminal SDI Scan-in data SDO Scanout data XTCK Test clock signal XACK A clock signal (master latch clock signal) BCK B clock signal (slave latch clock signal)

Claims (4)

(57) [Claims] The present invention comprises a combinational circuit and a plurality of master-slave flip-flops having scan-in terminals. In a test mode, the plurality of flip-flops have a shift register configuration. An integrated circuit in which a first mode for serially inputting and outputting data and a second mode for operating the entire circuit by treating the plurality of flip-flops as part of external terminals are alternately provided. An asynchronous signal input section is provided for each of the master latch and the slave latch of the plurality of flip-flops, and in the first mode, input of an asynchronous signal to the asynchronous signal input section of the master latch and the slave latch of the plurality of flip-flops is inhibited. , In the second mode, the master latch of the plurality of flip-flops An asynchronous signal input control unit that permits input of an asynchronous signal to the synchronous signal input unit and inhibits input of an asynchronous signal to the asynchronous signal input unit of the slave latches of the plurality of flip-flops is provided. Integrated circuit characterized. 2. In the second mode, when data written in the flip-flop is output before shifting to the first mode, the data written in the flip-flop is output. 2. The integrated circuit according to claim 1, wherein the control is performed such that the input of the asynchronous signal to the asynchronous signal input section of the master latch of the plurality of flip-flops is inhibited before the operation. 3. The control for inhibiting the input of an asynchronous signal to an asynchronous signal input section of a master latch of the plurality of flip-flops in the second mode is performed by a signal for setting the first mode in the combinational circuit. When a bus input / output circuit used as a control signal is included, the bus input / output circuit is configured to use a signal for serially inputting and outputting data to and from the plurality of flip-flops in the first mode. 3. The integrated circuit according to claim 2, wherein: 4. A control for inhibiting input of an asynchronous signal to an asynchronous signal input section of a master latch of the plurality of flip-flops, wherein the control circuit uses a signal for setting the first mode in the combinational circuit as a control signal. 3. The integrated circuit according to claim 2, wherein when an input / output circuit is not included, the operation is performed using a signal for setting the first mode.