JP2762815B2 - Transmission line error compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line error compensating circuit, and more particularly to an error compensating circuit for cell discard in an ATM (asynchronous transfer mode) transmission line (hereinafter referred to as an ATM transmission line).

[0002]

2. Description of the Related Art Conventionally, as a countermeasure against cell discard in an ATM transmission line, a method using retransmission, a method using duplicate transmission, and a method using a combination of cell interleaving and bit error correction have been taken.

[0003]

In the conventional measures for discarding cells, when the method is first performed by retransmission, there is a problem that the method cannot be used for real-time communication, and a retransmission procedure is required. However, there is a problem that the transmission efficiency decreases due to the increase of the information.

[0004] In addition, the method using the overlapping transmission has a problem that the transmission efficiency is reduced by repeatedly transmitting the same information.

[0005] The method using a combination of cell interleaving and bit error correction has a problem that the hardware for realizing the circuit becomes complicated and the hardware scale becomes large. Further, there is a problem that the delay amount due to the interleaving is very large.

The present invention has been proposed to solve the problems of the prior art, and can simplify the circuit configuration, and can compensate for discarded cells in real time without lowering the transmission efficiency. An object of the present invention is to provide a transmission line error compensation circuit.

[0007]

In order to achieve this object, a transmission line error compensating circuit according to the present invention comprises a parity operation cell for determining the number m of parity operation cells in accordance with a cell loss rate sent from a transmission unit. A number determination circuit, and when the number of parity calculation cells is m, each cell is multiplexed with n-bit input data by successive cell numbers from 1 to m-1 indicating the order of the cells, thereby forming a cell number multiplexed signal. A cell number multiplexing circuit to be output and this cell number multiplexed signal are inputted, and the first bit to the n-th cell of each cell of cell numbers 1 to m-1 are input.
A parity operation circuit that calculates and outputs n parity bits of i-th constituent bits among the bits, and a parity cell that multiplexes a cell number m by assembling data of one cell from the n parity bits The transmission unit has a parity cell assembling circuit that outputs a parity cell and a parity cell insertion circuit that inserts the parity cell into the cell number multiplexed signal to generate transmission data and sends the transmission data to a transmission path. A cell number separating circuit that separates received data input from a channel into data and a cell number and outputs separated data and a received cell number, and that receives the received cell number and corresponds to a cell missing in the transmission line A cell number missing detection circuit that detects a cell number and outputs a missing cell number, counts the missing cell number, measures a cell loss rate, and receives the cell loss rate And the cell discard rate measuring circuit to be transmitted to the cell, and n pieces of the i-th constituent bits among the first bit to the n-th bit of each cell from 1 to m of the cell number excluding the lost cell, in which the separated data are inputted. A parity operation circuit for calculating and outputting the parity bit of the above, a compensating cell assembling circuit for assembling data for one cell from the n parity bits and outputting a compensating cell, and a compensating cell based on the missing cell number. A missing cell insertion timing signal generating circuit for outputting an insertion timing signal indicating a missing cell position into which the data is to be inserted; and a cell compensation signal for inserting the compensation cell into the missing cell position in the separated data based on the insertion timing signal. And a parity cell removing circuit for removing parity cells from the cell compensation signal and outputting output data. It is constituted to have.

[0008]

According to the above-described configuration, the transmitting section performs a parity operation at intervals of the number of cells m according to the cell loss rate of the transmission path to generate a parity cell, and adds the parity cell to input data. Transmission data in which cell numbers are multiplexed can be transmitted to a transmission path. In addition, the receiving unit can detect a lost cell on the transmission line by checking the cell number in the received data, and can supplement the compensation cell created by the parity operation to the position of the missing cell.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a transmission line error compensating circuit according to the present invention. FIG. 1 is a block diagram showing one embodiment of the transmission line error compensation circuit. In these figures, the input data S1 taken into the input terminal IN is input to the cell number multiplexing circuit 2, and the cell number multiplexing circuit 2 supplies the cell number counter 1 with the cell number S.
2 is input. The cell number multiplexed signal S3 output from the cell number multiplexing circuit 2 is input to the parity cell insertion circuit 5 and the parity operation circuit 3. This parity operation circuit 3
Is output to the parity assembling circuit 4, and the parity cell S5 generated by the parity assembling circuit 4 is input to the parity cell inserting circuit 5. From the parity cell insertion circuit 5, transmission data S 6 is output to the transmission line 6.

[0010] Separated data S8 is output from the cell number separating circuit 7 into which the received data S7 from the transmission line 6 is taken, and is input to the delay circuit 8 and the parity operation circuit 9.
The received cell number S12 output from the cell number separation circuit 7 is input to the cell number deletion circuit 11. The delay data S9 output from the delay circuit 8 is input to the missing cell insertion circuit 13. A compensation cell S11 is output from the compensation cell assembling circuit 10 to which the missing cell data S10 from the reception parity operation circuit 9 is input, and is input to the missing cell insertion circuit 13. Also, the cell number missing detection circuit 11
Is input to the missing cell insertion timing signal generating circuit 12 and the cell discard rate measuring circuit 15. The insertion timing signal S14 indicating the position of the missing cell output from the missing cell insertion timing signal generation circuit 12 is input to the missing cell position insertion circuit 13. The cell compensation signal S15 is output from the missing cell position insertion circuit 13, and is input to the parity cell deletion circuit 14. The output data S16 output from the parity deletion circuit 14 is taken out from the output terminal OUT.

On the other hand, the cell loss rate measurement circuit 15 outputs the cell loss rate S17,
It is input to the parity calculation cell number determination circuit 17 on the one side.
The parity operation cell number S18 output from the parity operation cell number determination circuit 17 is input to the cell number counter 1.

Next, the operation of the transmission line error compensating circuit thus configured will be described. FIG. 2 shows a data structure of a cell handled in this embodiment. Each cell of the input data S1 is composed of n bits from the first bit to the n-th bit (n is a natural number). When the number of input parity operation cells S18 is m (m is a natural number), the cell number counter 1 counts the number of cells of the input data S1 from 1 to m-1, and sets a cell number multiplexing circuit as a cell number S2. Output to 2. When the cell number S2 is counted from 1 to m-1, it returns to 1 again and continues to be counted. The cell number multiplexing circuit 2 outputs a cell number multiplexed signal S3 obtained by multiplexing the input data S1 and the cell number S2 to the parity insertion circuit 5 and the parity operation circuit 3. In the parity operation circuit 3 to which the cell number multiplexed signal S3 is input, the number of 1s of the i-th bit of the constituent bits in the cell is counted from the first cell to the (m-1) th cell, and the i-th parity bit Is calculated as That is, assuming that the ith bit of the jth cell is bij (i and j are natural numbers), the parity bit Pi of the ith bit is given by Equation 1. In addition, Σ is the cumulative sum at the first completion. Here, the parity bit Pi indicates that an even parity is calculated.

[0013]

(Equation 1)

In the parity assembling circuit 4 to which the parity data S4 from the parity operation circuit 3 is input, data of one cell is assembled by the calculated n parity bits Pi from i = 1 to i = n. This is the cell number m
Is output to the parity insertion circuit 5. The parity insertion circuit 5 inserts the parity cell S5 into the cell number multiplexed signal S3 to generate transmission data S6, and sends the transmission data S6 to the transmission line 6. FIG.
(A) shows the configuration of the transmission data S6.

The data transmitted from the transmission unit U1 via the transmission path 6 is taken into the cell number separation circuit 7 of the reception unit U2 as reception data S7. FIG. 2B shows the received data S7 in which the d-th (d is a natural number) cell is missing in the transmission path 6. The cell number separation circuit 7 separates the reception cell number S12 from the reception data S7, outputs the separated reception cell number S12 to the cell number loss detection circuit 11, and outputs the separation data S8 to the delay circuit 8 and the reception parity calculation. Output to the circuit 9.

The missing cell number detecting circuit 11 detects a missing cell number d among the cell numbers 1 to m and outputs a missing cell number S13 to the missing cell insertion timing signal generating circuit 12. The missing cell insertion timing signal generation circuit 12 generates an insertion timing signal S14 for inserting the compensation cell S11 at the missing cell position from the missing cell number S13, and outputs it to the missing cell insertion circuit 13.

The reception parity operation circuit 9 performs the same operation as the operation in the parity operation circuit 3 described above.
In this case, since the cell with the cell number d is missing, the first
Parity bits are calculated in the cells from the cell to the (d-1) th cell and in the cells from the (d + 1) th cell to the (m) th cell. That is, if the i-th bit of the j-th cell is Rbij, the parity bit RPi is given by Equation 2. In addition, Σ is a cumulative sum in the first compliment, and + is a sum in the first compliment.
Here, even parity calculation is performed.

[0018]

(Equation 2)

In the compensating cell assembling circuit 10 to which the missing cell data S10, which is the result of the operation in the receiving parity operation circuit 9, is input, the parity bits RPi from the operation circuit 9 are collected from i = 1 to i = n to form one cell. The data is assembled and output to the missing cell insertion circuit 13 as the compensation cell S11. Since the operation of the compensation cell S11 requires a time corresponding to m cells, the delay circuit S8 compensates for the delay and outputs the delay data S9 to the missing cell insertion circuit 13.

In the missing cell insertion circuit 13, the data S
9, the compensation cell S11 is inserted at the timing of the insertion timing signal S14, and the cell compensation signal S15 is output to the parity cell deletion circuit 14. When the number of the missing cell detected by the missing cell number detecting circuit 11 is m, the missing cell is not complemented. In this parity cell deletion circuit 14, the parity cell, that is, the m-th cell is deleted and FIG.
The output data S16 shown in (c) is output from the output terminal OUT to the outside.

On the other hand, the cell discard rate measuring circuit 15 to which the missing cell number S13 is input counts the missing cell number S13 and measures the cell discard rate corresponding to the frequency of cell discard on the transmission line 6, and the cell discard rate is measured. The transmission line 16 is sent to the parity calculation cell number determination circuit 17 on the transmission unit U1 side as the rate S17.
Out through. This parity calculation cell number determination circuit 1
7, the cell discard rate S17 input from the receiving unit U2 side
, The number m of parity operation cells corresponding to the cell interval for performing the parity operation is calculated, and a signal S18 of the number of parity operation cells is output to the cell number counter 1.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist.

[0023]

As described above, according to the present invention, the transmitting section multiplexes the cell number into each cell and transmits the transmission data to which the parity cell is added to the transmission path, so that the transmission section can transmit the transmission data to the transmission path. The missing cells can be easily detected on the receiving side, and there is an effect that the missing cells can be compensated in real time by a simple operation of only the parity operation. Also, by measuring the cell loss rate on the receiving side, it is possible to detect the frequency of cell loss in the transmission path, and to perform cell loss compensation in units of cells according to the frequency of this cell loss. There is an effect that cell discarding can be complemented only by adding a redundant cell. As a result, the transmission efficiency does not decrease as in the related art, the circuit configuration can be simplified, and the size of the mounted circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a transmission line error compensation circuit according to the present invention.

FIG. 2 is a data configuration diagram showing a configuration of transmission data, reception data, and output data.

[Explanation of symbols]

 U1 transmitting unit U2 receiving unit 1 cell number counter 2 cell number multiplexing circuit 3 parity operation circuit 4 parity cell assembling circuit 5 parity cell insertion circuit 6,16 transmission line 7 cell number separation circuit 8 delay circuit 9 reception parity operation circuit 10 compensation cell Assembly Circuit 11 Cell Number Missing Detection Circuit 12 Missing Cell Insertion Timing Signal Generating Circuit 13 Missing Cell Inserting Circuit 14 Parity Cell Deletion Circuit 15 Cell Discard Rate Measurement Circuit 17 Parity Calculation Cell Number Measurement Circuit S1 Input Data S2 Cell Number S3 Cell Number Multiplexed Signal S4 Parity data S5 Parity cell S6 Transmission data S7 Reception data S8 Separation data S9 Delay data S10 Missing cell data S11 Compensation cell S12 Receiving cell number S13 Missing cell number S14 Insertion timing signal S15 Cell compensation signal S16 Output Data S17 Cell loss rate S18 Number of parity operation cells

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/28 H04L 12/56 H04L 1/00 H04L 1/24

Claims (1)

(57) [Claims] 1. A parity calculation cell number determining circuit for determining a parity calculation cell number m according to a cell discard rate transmitted from a transmission unit, and when the parity calculation cell number is m, each cell starts from n bits. A cell number multiplexing circuit for multiplexing continuous cell numbers from 1 to m-1 indicating the order of cells to the input data to output a cell number multiplexed signal; A parity operation circuit that calculates and outputs n parity bits of the i-th constituent bits among the first to n-th bits of each cell from 1 to m-1;
A parity cell assembling circuit for assembling data for the cells and outputting a parity cell multiplexed with the cell number m; and inserting the parity cell into the cell number multiplexed signal to generate transmission data, and transmitting the transmission data to a transmission path. A transmitting unit having a parity cell insertion circuit for transmitting, a cell number separating circuit for separating received data input from the transmission line into data and a cell number, and outputting separated data and a received cell number; A received cell number is input, a cell number loss detection circuit that detects a cell number corresponding to a cell lost on the transmission path and outputs a lost cell number, counts the lost cell number, measures a cell discard rate, A cell discard rate measuring circuit for transmitting the cell discard rate to the receiving unit; and the first data of each cell from 1 to m of the cell number excluding the lost cell, to which the separated data is inputted. A parity operation circuit that calculates and outputs n parity bits of the i-th constituent bits among the n bits, and a compensating cell assembly that assembles one cell of data from the n parity bits and outputs a compensation cell. Based on the circuit and the missing cell number,
A missing cell insertion timing signal generating circuit for outputting an insertion timing signal indicating the position of the missing cell into which the compensation cell is to be inserted; and, based on the insertion timing signal, inserting the compensation cell into the missing cell position in the separated data. A transmission line error compensating circuit, characterized in that a receiving unit includes a missing cell inserting circuit that outputs a cell compensating signal and a parity cell deleting circuit that deletes a parity cell from the cell compensating signal and outputs output data.