JPH11355280A - Source clock recovery device, data transmission device, data reception device, and data transmission system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent disturbance of a reproduced clock in any state and reduce jitter of the reproduced clock. SOLUTION: A time stamp generated and transmitted on a transmission side, which is difference information between a count value obtained by counting up a network clock and a cycle obtained by dividing a source clock, is received via a transmission path. A time stamp correction unit that corrects the received time stamp to output a corrected time stamp, a counter that counts up the network clock and outputs a count value, and a correction time that is output from the time stamp correction unit. A comparator that reproduces the cycle using the stamp and the count value output from the counter and outputs a reproduction cycle; and a source clock that reproduces the source clock using the reproduction cycle output from the comparator. And a PLL circuit for outputting the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a source clock regenerating device, a data transmitting device, a data receiving device, and a data transmission system for reproducing a source clock frequency on a transmitting side on a receiving side. The present invention relates to a source clock reproducing device that transmits a time stamp and reproduces a source clock from the time stamp in a data receiving device, and a data transmission system using the source clock reproducing device.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for high-speed and multi-media networks.
us Transfer Mode: Asynchronous transfer mode) technology is being introduced. However, on the other hand, there are existing STM line services such as voice communication and video conference, and with the spread of the ATM network, it is necessary to accommodate these line services in the ATM network. In order to realize the existing STM line service via the ATM network, a technology for synchronizing the line clock between the transmission side and the reception side, that is, a source clock recovery technology is required.

As a conventional source clock recovery technique, for example, there is a clock recovery circuit disclosed in Japanese Patent Application Laid-Open No. H8-8918. FIG. 18 is a block diagram showing a configuration of a conventional clock recovery circuit. The operation will be described with reference to FIG.

When a cell, which is transmission information transmitted by the ATM transmission system S1, is received, an SAR (Segmenta
The SAR header S2 is separated in the header separation unit 1 in the SAR header S2. The SAR header S2 separated by the SAR header separation unit 1 includes a sequence number, frequency difference information, and a sequence number protection for protecting the sequence number and the frequency difference information in a prescribed format.

[0005] A sequence number is a number sequence added on the transmitting side in the order of generation of cells. The sequence number frequency difference information detection unit 2 detects the sequence number S3 and the frequency difference information S4 from the SAR header S2 separated by the SAR header separation unit 1. The detected sequence number S3 is monitored by the sequence number monitoring unit 3, and cell discard is detected due to discontinuity of the sequence number S3. Then, the presence or absence of cell discard is output from the sequence number monitoring unit 3 as a sequence number monitoring result signal S5. Further, the received frequency difference information S4 is managed by the frequency difference information management prediction processing unit 4 based on the sequence number monitoring result signal S5.

Here, in a normal case where no cell discard or cell delay occurs, the frequency difference information management prediction processing unit 4
From the frequency difference information management signal S6 output from
The received frequency difference information S4 is recorded instead of the oldest frequency difference information recorded in the memory 5, and the frequency difference information of the M-th cycle and the frequency difference information of the (M-1) -th cycle are stored in the memory 5. Information is recorded.

When a cell in which the frequency difference information of the M-th cycle is multiplexed is discarded, the sequence number monitoring unit 3 detects the occurrence of the cell discard by sending a sequence number monitoring result signal S5 to the frequency difference information management prediction processing. Output to the unit 4. Then, the frequency difference information management prediction processing unit 4
As a result, the predicted value of the frequency difference information of the Mth cycle is calculated by using the frequency difference information S4 of the Nth cycle accurately received before the Mth cycle recorded in the memory 5, and is calculated. The frequency difference information predicted value S7 is output to the clock reproducing unit 6. Then, the clock reproducing unit 6
And the source clock S using the frequency difference information prediction value S7.
9 is played.

As described above, according to the conventional clock recovery circuit, even if a cell is discarded in the ATM transmission system, it is possible to suppress the influence of the cell discard on the reproduction of the source clock, and to suppress the source clock. The clock can be reproduced stably.

[0009]

However, the conventional clock recovery circuit has a problem that the recovered clock on the receiving side is disturbed at the time of initial startup of a device provided with the clock recovery circuit. That is, the conventional clock recovery circuit is
The frequency difference information received during normal operation when cell discarding or cell delay does not occur is stored, and when cell discarding or cell delay occurs, a clock is reproduced using the frequency difference information stored during normal operation. Therefore, at the time of initial startup, since the state before the frequency difference information is stored on the receiving side, the reproduced clock is disturbed.

[0010] Further, there is a problem that jitter is always generated in a reproduced clock reproduced on the receiving side. That is, in the ATM transmission system, the frequency difference information used when reproducing the clock is digitally approximated on the transmission side, and thus the reproduced clock cannot be completely matched with the clock on the transmission side.

The present invention has been made in order to solve the above-mentioned problems, and has been made in any state (normal, initial startup, reset, cell discarding, fault occurrence, illegal timestamp reception, It is an object of the present invention to provide a source clock reproducing device, a data transmitting device, a data receiving device, and a data transmission system that can suppress disturbance of the reproduced clock even during cell delay and the like and reduce jitter of the reproduced clock.

[0012]

According to the present invention, there is provided a source clock regenerating apparatus on a transmitting side comprising difference information between a count value obtained by counting up a network clock and a cycle obtained by dividing a source clock. Time stamp correction means for receiving a generated and transmitted time stamp via a transmission path, correcting the received time stamp and outputting a corrected time stamp, and counting up the network clock and outputting a count value And a comparator that reproduces the cycle using the corrected time stamp output from the time stamp correction unit and the count value output from the counter, and outputs a playback cycle. And a PLL circuit that reproduces the source clock by using the reproduction cycle and outputs the reproduced clock.

Further, in the source clock reproducing apparatus according to the next invention, the time stamp correcting means for outputting the corrected time stamp includes two time stamps received at a fixed period interval among the plurality of time stamps sequentially received. A difference calculation circuit for calculating a difference between stamps and outputting the calculated difference value; a default output means for outputting a preset default difference value; a calculated difference value output from the difference calculation circuit; and the default output means Selects one of the default difference values output from the selector, and outputs a new correction timestamp by adding a difference value output from the selector to the correction timestamp output last time and a selector for outputting a new correction timestamp. And an adder for generating and outputting the same.

In the source clock reproducing apparatus according to the next invention, the time stamp correction means includes detection means for outputting a detection signal to the selector at the time of reset and / or occurrence of a failure in the transmission line. ,
It is configured to select the default difference value based on a detection signal output from the detection means.

In the source clock reproducing apparatus according to the next invention, the time stamp correction means determines whether the calculated difference value output from the difference calculation circuit is within a predetermined allowable setting range. A difference determination unit that outputs a fraud detection signal to the selector when the value is out of a predetermined allowable setting range; and the selector selects the default difference value based on the fraud detection signal output from the difference determination unit. It is configured to do so.

Further, in the source clock reproducing apparatus according to the next invention, the time stamp correcting means for outputting the corrected time stamp includes two time stamps received at a fixed period interval among the plurality of time stamps sequentially received. A difference calculation circuit that calculates a difference between stamps and outputs the calculated difference value, a register that stores the calculated difference value output from the difference calculation circuit, and a plurality of calculations including the calculated difference value stored in the register A first adder for adding a difference value to output a total difference value, and recursively adding a total difference value output from the first adder to the correction time stamp output last time to generate a new correction time stamp And a second adder that generates and outputs the calculated difference value, wherein the counter receives the network clock as an input and corresponds to the number of calculation difference values added by the first adder. And a clock generating means for generating a lock, is intended to be configured to output a count value counted up by the clock generated by the clock generating means.

A source clock reproducing apparatus according to the next invention temporarily stores the received time stamp,
A time stamp buffer for outputting the time stamp to the time stamp correction means in accordance with the reproduction clock output from the PLL circuit.

Still further, the data transmission apparatus according to the next invention transmits a time stamp which generates difference information between a count value obtained by counting up a network clock and a cycle obtained by dividing a source clock. Time stamp generating means, when assembling and transmitting a plurality of cells using a plurality of transmission data and a time stamp generated by the transmission time stamp generating means, the same time stamp information constituting the time stamp And a cell assembler for mapping to a plurality of cells.

Further, a data receiving apparatus according to the next invention is characterized in that a time stamp and transmission data which are difference information between a count value obtained by counting up a network clock and a cycle obtained by dividing a source clock are provided. Receiving the cell via the transmission line, disassembling the cell and outputting a time stamp and transmission data, and a plurality of the same time stamps constituting the time stamp output from the cell disassembly unit A time stamp correction unit that supplements the time stamp information with reference to any of the information, corrects the time stamp and outputs a corrected time stamp, and a counter that counts up the network clock and outputs a count value; The correction time stamp output from the time stamp correction means and the count value output from the counter , A comparator that reproduces the above cycle and outputs a reproduction cycle, a PLL circuit that reproduces the source clock using the reproduction cycle output from the comparator, and outputs a reproduced clock, And a buffer for temporarily storing transmission data output from the PLL circuit and outputting the transmission data in accordance with a reproduction clock output from the PLL circuit.

Further, in the data transmission system according to the next invention, the data transmission device has a time stamp comprising difference information between a count value obtained by counting up a network clock and a cycle obtained by dividing the source clock. Transmission timestamp generation means for generating the same timestamp information constituting the timestamp when assembling and transmitting cells using transmission data and a timestamp generated by the transmission timestamp generation means. A cell assembling unit for mapping to a plurality of cells, a data receiving device, a cell disassembling unit for disassembling a cell assembled by the cell assembling unit and transmitted via a transmission path, and outputting a time stamp and transmission data. And a plurality of the same time stamp information constituting the time stamp output from the cell disassembling unit. A time stamp correction means for compensating the time stamp information and outputting the corrected time stamp by referring to the time stamp information; a counter for counting up the network clock to output a count value; The comparator reproduces the period using the correction time stamp output from the correction means and the count value output from the counter, and outputs a reproduction period. A PLL circuit that reproduces a source clock and outputs a reproduced clock, and a buffer that temporarily accumulates transmission data output from the cell disassembly unit and outputs the transmission data in accordance with the reproduced clock output from the PLL circuit. Things.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiment, the transmitted time stamp will be described as a transmission time stamp, the received time stamp will be described as a reception time stamp, the transmitted transmission data will be described as transmission data, and the received transmission data will be described as reception data.

FIG. 1 is a block diagram showing a configuration of a data transmission system according to one embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a data transmitting device for performing data communication in an ATM network, and reference numeral 20 denotes a data receiving device.

Numeral 11 denotes a counter which counts up by the network clock S11 and outputs a count value S13. Here, a 4-bit counter is used. Reference numeral 12 denotes a frequency divider which divides the source clock S12 and generates a predetermined periodic pulse.
Is output.

Reference numeral 13 latches (holds) a count value S13 output from the 4-bit counter 11 for each cycle T S14 of the periodic pulse generated by the frequency divider 12.
Then, the network clock S11 and the source clock S1
This is a latch that outputs a transmission time stamp S15 that is difference information from the period TS14 obtained by dividing the frequency of 2. In the present embodiment, the transmission time stamp generating means includes the 4-bit counter 11, the frequency divider 12, and the latch 13.

Reference numeral 14 denotes the transmission data S10 and the latch 1
3 is a cell assembling unit that assembles and transmits a cell S16 using the transmission time stamp S15 output from the third cell. Fifteen
Is a transmission path for transmitting the cell S16 assembled by the cell assembling section 14.

Reference numeral 21 denotes a cell decomposing unit that decomposes the cell S16 transmitted from the data transmission device 10 via the transmission line 15 and outputs the reception data S20 and the reception time stamp S21. Reference numeral 22 denotes a time for calculating the difference between two consecutive reception timestamps S21 among the reception timestamps S21 sequentially output from the cell disassembly unit 21 and correcting and outputting the correction timestamp S22 using the difference value. Stamp correction means.

Reference numeral 23 denotes a comparator mask counter 2 described later.
4 while the enable signal S24 output from the data receiving device 20 is asserted.
Counter value S13 output from the time stamp correction time stamp S22 output from the time stamp correction means 22
And a matcher, and detects a match, reproduces the period T S14 output from the frequency divider 12, and outputs a reproduction period Tr S23.

Reference numeral 24 denotes a comparator mask counter which invalidates the operation of the comparator 23 for a certain period.
When the count is incremented by 11 and exceeds a predetermined threshold value, the enable signal S24 is asserted. When the reproduction cycle Tr S23 is output from the comparator 23, the count is reset.

A PLL 25 reproduces a clock by a phase feedback loop using a reproduction cycle Tr S23 output from the comparator 23, and outputs a reproduced clock S25.
Circuit (Phase Lock Loop circuit). Reference numeral 26 denotes a buffer for temporarily storing the reception data S20 output from the cell disassembly unit 21 and outputting the reception data S26 in accordance with the reproduction clock S25 output from the PLL circuit 25.

Next, the operation will be described. For the sake of simplicity, a case where the source clock S12 is 1.544 MHz will be described as an example, but the range of the source clock frequency is not limited. The basic transmission rate in the ATM network is 155.52 Mbps or 622.0 Mbps.
According to ITU-T I.363, if the frequency of the network clock S11 is fn and the frequency of the source clock S12 is fs, then 1 <fn / fs ≦ 2
There is a restriction.

Therefore, here, the frequency of the network clock S11 is obtained by multiplying 155.52 MHz by 2.sup.-6 to 2.43.
MHz. Further, a case will be described in which the 4-bit counter 11 is used as the counter and the bit width of the time stamp is set to 4, based on ITU-T I.363, but other counters and bit widths of the time stamp may be used. Needless to say.

In the data transmitting apparatus 10, first, the 4-bit counter 11 outputs a count value S13 unconditionally counted up by the network clock S11. On the other hand, the frequency divider 12 outputs a period T S14 obtained by dividing the frequency of the source clock S12. In the present embodiment, this cycle T S14 is a data transmission period for eight cells.

Then, the 4-bit counter 1 is latched by the latch 13 every period TS14 output from the frequency divider 12.
The count value S13 output from 1 is latched and output to the cell assembling unit 14 as the transmission time stamp S15.

In the present embodiment, the value of the transmission time stamp is the remainder obtained by adding the value of the previous transmission time stamp to the number of periods T in terms of the network clock and dividing by 16. As described above, the period T S14 is equal to 8 of the cell S16.
This corresponds to the transmission period of the cell, and is equal to the source clock frequency of 3
008 clocks, that is, 1.948 ms. When this is converted to a network clock, the value is 4733 or 4
334. The value of the previous transmission time stamp is added to this value, and the remainder obtained by dividing by 16 is the value of the current transmission time stamp.

The transmission time stamp S from the latch 13
15 is output to the cell assembling section 14, the cell assembling section 14
, A cell S16 is assembled using the transmission data S10 and the transmission time stamp S15, and the cell S16 is assembled.
16 is transmitted to the data receiving device 20 via the transmission path 15.

FIG. 2 is a conceptual diagram showing the structure of a 53-byte long cell based on AAL (ATM adaptation layer) type 1. In FIG. 2, D1 is a 5-byte ATM header storing header information of ATM transmission, and D2 is a 1-byte SAR-PDU storing header information of transmission information.
Header (Segmentation And Reassembly-Protocol Data
Unit header), D3 is SAR- storing transmission data.
PDU payload, D4 is C that stores time stamp
An SI bit (Convergence Sublayer Indication bit), D5 is an SC field (Sequence field) for storing a sequence number, D6 is a CRC field (Cycric Redundancy Check field) used for cyclic redundancy check, and D7 is an even parity used for parity check.

The transmission data S1 is transmitted by the cell assembling section 14.
0 is mapped to the SAR-PDU payload D3, the transmission time stamp S15 is mapped to the CSI bit D4, and the cell S16 is assembled.

FIG. 3 is a conceptual diagram showing an example of how the transmission time stamp is mapped to the cell S16 in the cell assembling section 14. In the case of FIG. 3, the 4-bit transmission time stamp S15 is divided into transmission time stamp information of one bit at a time, and is mapped to the CSI bit D4 of the cell whose SC field D5 is an odd number among the eight cells S16.

Next, the data receiving device 20 will be described. First, the cell S1 transmitted from the data transmitting apparatus 10
6 is decomposed by the cell decomposing unit 21, the reception data S 20 is output to the buffer 26, and the reception time stamp S 21 is output to the time stamp correction unit 22.

When the reception time stamp S21 is output to the time stamp correction means 22, the time stamp correction means 22 outputs the last reception time stamp S21 and the current reception time stamp among the reception time stamps S21 sequentially input. The difference from S21 is calculated,
Corrected time stamp S2 corrected using the difference value
2 is output to the comparator 34. The detailed operation of the time stamp correction unit 22 will be described later.

On the other hand, the 4-bit counter 11 outputs a count value S13 unconditionally counted up by the network clock S11 to the comparator 23. At the same time, the comparator mask counter 24 counts up by the network clock S11 until the threshold value is exceeded, and when the threshold value is exceeded, the enable signal S24 is asserted.

While the enable signal S24 is asserted, the comparator 23 detects the coincidence between the count value S13 output from the 4-bit counter 11 and the correction time stamp S22 output from the time stamp correction means 22. Is performed, and from the result, the period T S14 output from the frequency divider 12 is reproduced to obtain the reproduction period TrS2.
3 is output.

Here, as the threshold value of the comparator mask counter 24, a value slightly smaller than the minimum possible value of the period TS14 is used. For example, frequency 1.544MH
The transfer characteristic of the z source clock S12 is ± 100 ppm
In this case, the cycle T S14 is 4733 to 4735 clocks in terms of the network clock S11. Therefore, about 4730 may be selected as the threshold. By doing so, the comparator 23 outputs the reproduction cycle Tr
S23 can be obtained.

Then, from the comparator 23, the reproduction cycle Tr
When S23 is output, the comparator mask counter 24 is reset. When the reproduction cycle Tr S23 output from the comparator 23 is input to the PLL circuit 25, a clock is reproduced by a phase feedback loop using the reproduction cycle Tr S23 in the PLL circuit 25, and the reproduction clock S25 is output. Is done. Then, according to the reproduced clock S25, the reception data S
26 is output. Thus, the data transmission device 1
0 period T S14 is reproduced by the data receiving device 20 at the reproduction period T
The data is reproduced as rS23, and the received data can be read.

Next, the time stamp correcting means 22, which is a main part of the present embodiment, will be described in detail.
FIG. 4 is a block diagram showing the configuration of the time stamp correction means 22. In FIG. 4, reference numeral 31 denotes a default output unit that outputs a preset default difference value S30. In this example, a difference between two consecutive reception time stamps among the reception time stamps S21 sequentially output from the cell decomposition unit 21 is shown. The value “+14” which occurs most frequently as a value is output as a default difference value. 32
Represents two consecutive reception time stamps S2 of the reception time stamps S21 sequentially output from the cell decomposition unit 21.
1 is a difference calculation circuit that calculates the difference of 1 and outputs the calculated difference value S31.

Reference numeral 33a denotes detection means for outputting a detection signal. Here, a reset signal detection means for detecting a reset signal S32 from a system monitor (not shown) and outputting a reset detection signal S33 when the reset signal S32 is detected. It is. For example, the system monitoring unit 33a
The reset signal S32 is output at the time of initial startup of the system, at the time of recovery from the occurrence of a line failure or device failure, or at the time of reset such as when the user resets the device.

A selector 34 selects one of the calculated difference value S31 output from the difference calculation circuit 32 and the default difference value S30 output from the default output means 31, and outputs the selected value as a difference value S34. Based on the reset detection signal S33 output from the reset signal detection means 33a, the default difference value S30 output from the default output means 31 is selected at the time of reset, and the difference calculation circuit 32 is output if not reset.
Is selected as the calculation difference value S31. 35 is
This is an adder that recursively generates and outputs a new correction time stamp S22 by adding the difference value S34 output from the selector 34 to the correction time stamp S22 output last time.

The operation of the time stamp correction means 22 will be described. FIG. 5 is a conceptual diagram showing a normal operation concept of the time stamp correction means 22 having the configuration of FIG. The reception time stamp S output from the cell disassembly unit 21
21 is a difference calculation circuit 3 of the time stamp correction means 22
2 is input.

Then, a default difference value S 30 is output from the default output means 31 to the selector 34. On the other hand, the difference calculation circuit 12 calculates a difference between two consecutive reception timestamps S21 of the reception timestamps S21 sequentially output from the cell decomposing unit 21, and outputs a calculated difference value S31 to the selector.

For example, if the reception time stamp S21 “14” was input to the difference calculation circuit 32 last time and the reception time stamp S21 “12” was input this time, the calculated difference value S31 becomes “12−14 = + 14”. ".

In the normal state (when not at the time of resetting), the reset detecting signal S33 is output from the reset signal detecting means 33a.
Is not output, the selector 34 selects the calculated difference value S31 output from the difference calculation circuit 32, and outputs the difference value S34 to the adder 35.

Then, the selector 34 is used by the adder 35.
Is added to the previously output corrected time stamp S22, and output as the current corrected time stamp S22. For example, the selector 3
4, the calculated difference value S31 is “+14”, and the previously output corrected time stamp S22 is “8”.
In this case, the current correction time stamp S22 is “8 + (+
14) = 6 ".

As described above, in the normal state, the correction time stamp is generated using the calculated difference value S31 calculated from the reception time stamp S21, and is output to the comparator 23.

Next, the operation at the time of reset will be described. FIG. 6 is a conceptual diagram showing an operation concept at the time of reset of the time stamp correction unit 22 having the configuration of FIG. FIG.
In the above, S21a is a reception time stamp received at the time of reset.

At the time of reset, the reset signal S32 is detected by the reset signal detection means 33a while the received reception time stamp S21a is being input, and the reset detection signal S33 is output to the selector 34.

On the other hand, when the received time stamp S21 output from the cell disassembly unit 21 is input to the difference calculation circuit 32 of the time stamp correction unit 22 at the time of reset, similarly to the normal state, the default output unit 31 outputs the received time stamp S21. The default difference value S30 “+14” is output to the selector 34, and the difference calculation circuit 12 outputs the calculated difference value S31 to the selector 34.

Then, in the selector 34, the reset detection signal S33 output from the reset signal detection means 33a is output.
, The default difference value S30 “+14” output from the default output means 31 is selected, and is output as the difference value S34.

Then, the selector 34 is used by the adder 35.
Is added to the previously output corrected time stamp S22, and is output to the comparator 23 as the current corrected time stamp S22. As described above, at the time of resetting, the default difference value S30 output from the default output means 31 is selected by the selector 34, so that the reception time stamp S21 at the time of resetting is selected.
a is not reflected in the correction time stamp S22.

As for the reception time stamp S21a received at the time of reset, the state of the system is unstable, and the reception timing fluctuates. In particular, at the time of initial system startup, the system is in a state before receiving the reception time stamp S21. Therefore, since the calculation difference value S31 cannot be calculated accurately, the reception time stamp S21 at the time of resetting is not available.
Since a is not reflected in the correction time stamp S22, the time stamp correction unit 22 can generate the correction time stamp S22 at the time of reset, and the data receiving device 20 can reproduce the stable reproduction cycle Tr S23.

Thereafter, when the system becomes normal after a lapse of time, the reset signal is not detected by the reset signal detecting means 33a. Then, the reset signal detecting means 33
The reset detection signal S33 is no longer output from a, and the selector 34 selects the calculation difference value S31 output from the difference calculation circuit 32 as in the normal operation described above.

As described above, according to the present embodiment, the data receiving device corrects the reception time stamp using the calculated difference value calculated from two consecutive reception time stamps, and generates a corrected time stamp. Thereby, a stable reproduction clock can be obtained.

In the data receiving device, a correction time stamp is generated using a calculated difference value calculated from two consecutive reception time stamps in a normal state, and a correction time stamp is generated using a preset default difference value in a reset state. By generating a stamp and using the corrected time stamp to regenerate the source clock on the transmitting side, not only can a stable recovered clock be obtained during normal operation, but also during resetting, including when the system is initially started up. A reproduced clock can be obtained without giving any disturbance.

In the present embodiment, the case where the calculation difference value is calculated from two consecutive reception time stamps has been described, but the present invention is not limited to this. The calculated difference value may be a difference value between the reception time stamps at regular intervals, for example, a difference value between every other reception time stamp. In this case, the time required for the reproduction clock to stabilize slightly increases, but the jitter of the reproduction clock can be reduced.

Embodiment 2 In the above-described embodiment, the time stamp correction unit 22 includes the reset signal detection unit 33a.
Is provided so that a stable reproduced clock can be obtained even at the time of reset. Next, an embodiment in which a stable reproduced clock can be obtained when a failure occurs in the transmission path will be described.

FIG. 7 is a block diagram showing a configuration of the time stamp correction means 22 according to the present embodiment. The same reference numerals are given to the same or corresponding parts as in the above-described embodiment, and the description is omitted. Reference numeral 13b denotes detection means for outputting a detection signal to the selector 34. Here, a failure is detected by monitoring the sequence number S35 of the cell stored in the SC field D5 shown in FIG. This is a failure detection unit that outputs the detection signal S33 to the selector 34. Here, the sequence number S35 is input from the cell disassembly unit 21 shown in FIG. Note that a failure is a failure in the transmission path that can be detected from the sequence number S35, such as a cell loss (cell discard) in which a cell does not reach the receiving side, an erroneous insertion of an unnecessary cell, or a sequence error in which the arrival order of cells is disturbed. And so on.

The selector 34 selects the default difference value S30 output from the default output means 31 when a fault occurs, based on the fault detection signal S33 output from the fault detection means 33b, and selects the default difference value S30 when not reset. The calculation difference value S31 output from the difference calculation circuit 32 is selected, and the difference value S34 is output.

The operation will be described. FIG. 8 is a conceptual diagram showing an operation concept of the time stamp correction unit 22 having the configuration of FIG. 7 when a failure occurs. In FIG. 8, S21b
Is a time stamp lost when a failure occurs, and indicates that the time stamp has not reached the data receiving device.

In a normal state (when a failure does not occur), no failure is detected by the failure checking means 33 b, and no failure detection signal S 33 is output to the selector 34. Therefore,
The received time stamp S21 output from the cell decomposing unit 21 is used as the difference calculation circuit 3 of the time stamp correction unit 22.
2, the default output means 31 outputs the default difference value S30 to the selector 34, and the difference calculation circuit 32 outputs the calculated difference value S31 to the selector 34. The output calculation difference value S31 is selected, and this is the difference value S
It is output to the adder 35 as 34.

That is, while the reception time stamp S21 is normally transmitted as "3, 1, 14", the selector 34 selects the calculation difference value S31 output from the difference calculation circuit 32, and the difference value S34 As "+1
3, +14 "are sequentially output to the adder 35.

On the other hand, when a failure occurs, the failure inspection means 33b
As a result, a failure is detected from the sequence number S35, and a failure detection signal S33 is output to the selector. Then, after the reception time stamp S21 output from the cell disassembly unit 21 is input to the difference calculation circuit 32 of the time stamp correction unit 22, a default difference value S30 is output from the default output unit 31 to the selector 34, and the difference calculation is performed. When the calculated difference value S31 is output from the circuit 32 to the selector 34, the selector 34 selects the default difference value S30 output from the default output means 31, and outputs this to the adder 35 as the difference value S34.

That is, the lost time stamp S21
If the reception time stamp has not arrived as shown in FIG.
Is selected, and “+14” is output to the adder 35 as the difference value S34.

When the difference value S34 is output from the selector 34 to the adder 35, a correction time stamp S22 is generated by the adder 35 and output to the comparator 23, as in the above-described embodiment. Further, the reproduction cycle Tr S23 is reproduced by the comparator 23 using the correction time stamp S22, the clock is reproduced by the PLL circuit 25 using the reproduction cycle Tr S23, and the reproduction clock S25 is output.

As described above, according to the present embodiment, the data receiving apparatus generates a correction timestamp using a calculation difference value calculated from two consecutive reception timestamps in a normal state, and generates a correction timestamp in advance when a failure occurs. By generating a correction timestamp using the set default difference value and using the corrected timestamp to reproduce the source clock on the transmission side, not only can a stable reproduction clock be obtained during normal operation, but also a failure can occur. At the time, for example, even when a failure occurs in the transmission path and the time stamp does not arrive, a reproduced clock can be obtained without giving a large disturbance.

In the present embodiment, the case has been described where the calculation difference value is calculated from two consecutive reception time stamps. However, the calculation difference value may be any difference value between the reception time stamps at regular intervals. Needless to say, the present invention is not limited to this.

Embodiment 3 In the above-described embodiment, a stable reproduction clock can be obtained even at the time of reset or occurrence of a failure. Next, a stable reproduction clock can be obtained when an incorrect time stamp is received. Is shown.

FIG. 9 is a block diagram showing a configuration of the time stamp correction means 22 according to the present embodiment. The same reference numerals are given to the same or corresponding parts as in the above-described embodiment, and the description is omitted. 33c monitors the calculation difference value S32 output from the difference calculation circuit 12, determines whether the calculation difference value S32 is a value within the allowable setting range as the time stamp difference value, and uses a value outside the allowable setting range. This is a difference determination unit that determines that an invalid time stamp has been received at a certain time, and outputs a fraud detection signal S33 to the selector. For example,
The allowable setting range as the time stamp difference value is +13
To +15.

The selector 34 outputs a default value output from the default output means 31 when a value outside the allowable setting range as the time stamp difference value is generated based on the fraud detection signal S33 output from the difference determination means 33c. The difference value S30 is selected. Otherwise, the calculated difference value S31 output from the difference calculation circuit 32 is selected, and the difference value S34 is output.

The operation will be described. FIG. 10 is a conceptual diagram showing an operation concept when a value outside the allowable setting range as the time stamp difference value occurs in the time stamp correction unit 22 having the configuration of FIG.

Similarly to the above-described embodiment, when the reception time stamp S21 output from the cell decomposing unit 21 is input to the difference calculation circuit 32 of the time stamp correction unit 22, the default output unit 31 outputs the default difference value. S
30 is output to the selector 34, and the calculated difference value S 31 is output to the selector 34 from the difference calculation circuit 32.

At the same time, the calculated difference value S31 from the difference calculation circuit 32 is output to the difference judgment means 33c. Then, the calculated difference value S31 is calculated by the difference determination unit 33.
At c, it is determined whether or not the value is within the allowable setting range as the difference value of the time stamp.

As a result, when the calculated difference value S31 is within the allowable set range, it is not determined that an invalid time stamp has been received, and the difference determination means 33c does not output the fraud detection signal S33. In this case, the selector 34 selects the calculated difference value S31 output from the difference calculation circuit 32, and outputs it to the adder 35 as the difference value S34. That is, when the difference value between two consecutive reception time stamps S21 is +13 to +15, the selector 34 selects the calculated difference value S31.

On the other hand, when the calculated difference value S31 is out of the allowable setting range, it is determined that an invalid time stamp has been received, and the difference determination means 33c outputs an illegality detection signal S33 to the selector. . Then, the selector 34 outputs the default difference value S3 output from the default output means 31 based on the fraud detection signal S33.
0 is selected and output to the adder 35 as the difference value S34.

That is, for example, in FIG. 10, when the previous reception time stamp S21 is “14” and the current reception time stamp S21 is “9”, the calculated difference value S31 becomes “14−9 = + 11”. ". However, since “+11” is out of the allowable setting range (+13 to +15), the fraud detection signal S33 is output from the difference determination unit 33c to the selector 34, and the selector 34 performs the above based on the fraud detection signal S33. The default difference value S30 “+14” is selected.

When the difference value S34 is output from the selector 34 to the adder 35, a correction time stamp S22 is generated by the adder 35 and output to the comparator 23, as in the above-described embodiment. Further, the reproduction cycle Tr S23 is reproduced by the comparator 23 using the correction time stamp S22, the clock is reproduced by the PLL circuit 25 using the reproduction cycle Tr S23, and the reproduction clock S25 is output.

As described above, according to the present embodiment, when the calculated difference value calculated from two consecutive received time stamps is a value outside the allowable setting range as the time stamp difference value, the value is set in advance. By generating a correction time stamp using the default difference value and reproducing the source clock on the transmission side using the correction time stamp, not only can a stable reproduction clock be obtained in a normal state, but also the difference value of the time stamp can be obtained. When a value outside the allowable setting range occurs, for example, when an incorrect time stamp is received, a reproduced clock can be obtained without giving a large disturbance.

In the present embodiment, the case has been described where the calculation difference value is calculated from two consecutive reception time stamps. However, the calculation difference value may be any difference value between the reception time stamps at regular intervals. Needless to say, the present invention is not limited to this.

Embodiment 4 In the above-described embodiment, the correction time stamp is generated from one difference value. Next, the number of bits of the counter of the data receiving device is extended, the operation clock is increased, and the correction is performed from a plurality of difference values. 5 shows an embodiment for generating a time stamp.

FIG. 11 is a block diagram showing a configuration of the time stamp correction means 22 according to the present embodiment. FIG.
In FIG. 1, the same or corresponding portions as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Reference numeral 36 stores the calculated difference value S31 output from the difference calculation circuit 32, and further stores the next calculated difference value S3.
This is a register that outputs 1 as the previous calculation difference value S36 when 1 is output from the difference calculation circuit 32.

A first adder 37 adds the calculated difference value S31 output from the difference calculation circuit 32 and the immediately preceding calculated difference value S36 output from the register and outputs a total difference value S37. is there. An adder 38 recursively generates a new corrected time stamp S22 by adding the total difference value S37 output from the first adder 37 to the previously output corrected time stamp S22 and outputs the new corrected time stamp S22.

FIG. 12 is a block diagram showing a configuration of data receiving apparatus 20 according to the present embodiment. The same reference numerals are given to the same or corresponding parts as in the above-described embodiment, and the description is omitted. Reference numeral 27 denotes a clock generation unit that receives the network clock S11 as input, and generates a clock corresponding to the number of calculation difference values added by the first adder. Here, since the two calculation difference values are added by the first adder, a clock twice as large as the network clock is generated.

Reference numeral 28 denotes an extension counter for outputting a count value S22 counted up by the clock generated by the clock generation means 27. In this case, the operation clock (network clock) is doubled by the clock generation means 27. Therefore, a 5-bit counter obtained by extending the 4-bit counter by 1 bit is used. In this embodiment, the counter includes the clock generation means 27 and the 5-bit counter. The time stamp correction unit 22 generates a correction time stamp S22, as in the above-described embodiment, but generates a correction time stamp corresponding to 5 bits here.

The operation will be described. FIG. 13 is a conceptual diagram showing the concept of the operation of the time stamp correction unit 22 in this case. The same reference numerals are given to the same or corresponding parts as in the above-described embodiment, and the description is omitted. S31 is a calculated difference value output from the difference calculation circuit 32, and is output in the order of a, b, and c. S36 is the previous calculation difference value output from the register 36 in accordance with the timing at which the calculation difference value S31 is output, and d, e, and f are the same as a, b, and c, respectively. . S37 is the total difference value output from the first adder 37.

First, as in the above-described embodiment, when the reception time stamp S21 is input to the difference calculation circuit 32, a calculation difference value S31 is output. In the initial state, the calculated difference value S31a “+14” is stored in the register 36 as the previous calculated difference value S36d “+14”.

When the next reception time stamp S21 is input to the difference calculation circuit 32, the calculation difference value S31b “+14” is output from the difference calculation circuit 32 and input to the first adder 37. At the same time, the register 36
Outputs the previous calculated difference value S36d “+14” from
It is input to the first adder 37.

Then, the first adder 37 calculates the calculated difference value S31b “+14” and the previous calculated difference value S36d.
"+14" is added, and the total difference value S37g "+28" is input to the second adder 38. In the second adder 38, the total difference value S37g “+28” is added to the previously output correction time stamp “11”, and a new correction time stamp S22 “7” is output.

As described above, by generating the correction time stamp S22 corresponding to the extension bit from the total difference value S37 obtained by adding the current calculation difference value S31 and the previous calculation difference value S36, the error (variation) of the correction time stamp can be obtained. ) Can be averaged, and the error given to the reproduction cycle Tr S23 can be averaged, and the jitter of the reproduction clock S25 can be reduced.

That is, since the time stamp is digitally approximated on the transmission side, the calculation difference value is disturbed on the reception side. For example, in the calculation difference value S31, only the calculation difference value S31c is “+13”. Therefore, when the correction time stamp on the receiving side is not extended, the correction time stamp is shifted in this portion, and the reproduction cycle Tr S23 generated using this correction time stamp is disturbed, and jitter occurs in the reproduction clock S25.

On the other hand, when the correction time stamp on the receiving side is extended, "+27" is repeated twice in the total difference value S37. That is, if "+27" is converted to a normal network clock, it is "+13.5", and the reproduction cycle T
The error given to rS23 can be averaged. Therefore, the clock can be reproduced using the averaged reproduction cycle Tr S23, and the jitter of the reproduction clock S25 can be reduced.

As described above, according to the present embodiment, the 4-bit counter of the data receiving apparatus is extended by 1 bit, the operation clock is doubled, and the current difference value and the previous difference value are added. By generating a correction time stamp corresponding to the extension bit from the total difference value thus generated, a correction time stamp with a small error (fluctuation) can be generated, and the error given to the reproduction cycle Tr S23 can be averaged. Thus, the jitter of the reproduction clock can be reduced.

In the present embodiment, the 4-bit counter is extended by one bit, the operation clock is doubled,
Although the case where the correction time stamp is generated from the total difference value of the two difference values has been described, the present invention is not limited to this. The N (N is a natural number) bit counter is extended by k (k is a natural number) bits, and the operating clock is multiplied by m (m is k of 2).
The correction time stamp may be generated from the total difference value of the 2 ^k difference values.

In this case, the clock generating means is configured to generate a clock corresponding to the number of extension bits k, and the extension counter uses an N + k bit counter. Further, the time stamp correction means has, for example, a configuration as shown in FIG. FIG. 14 is a block diagram showing the configuration of the time stamp correction means when an N + k bit counter is used. The same or corresponding parts as those in FIG.
Description is omitted.

Reference numeral 36 denotes a group of registers for storing the calculated difference value output from the difference calculation circuit 32.
It consists of ^k-1 registers. 361 stores a calculated difference value S31 output from the difference calculation circuit 32,
Further, when the next calculation difference value S31 is output from the difference calculation circuit 32, it is a first register that outputs the immediately preceding calculation difference value S361. 362 stores the immediately preceding calculation difference value S361 output from the first register, and further stores the next calculation difference value S31 in the difference calculation circuit 3.
2 is a second register that outputs as the calculation difference value S362 two times before when the data is output from the second register. Similarly, 363, 2 ^k when the first 2 ^k-2 register before 2 ^k-2 times outputted from the calculated difference value is stored, the following additional computational difference value S31 is outputted from the difference calculation circuit 32 ^-1 previous calculation difference value S3
A second ^k-1 register output as 63;

As described above, the counter of the data receiving apparatus is expanded by k bits, and the operation clock is multiplied by m (m is 2 to the power of k).
And a correction time stamp corresponding to N + k bits is generated from the total difference value obtained by adding the k calculation difference values, so that the larger the number k of calculation difference values to be added, the larger the calculation amount and the number of registers. However, the jitter of the reproduction clock can be further reduced.

The case where the calculation difference value is calculated from two consecutive reception time stamps has been described. However, the calculation difference value may be a difference value between reception time stamps at regular intervals, and is not limited to this. Needless to say, it is not a thing.

Embodiment 5 FIG. In the above-described embodiment, the correction time stamp is generated according to the timing at which the cell arrives at the data receiving apparatus. Next, an embodiment will be described in which the correction time stamp is generated according to the cell delay fluctuation. .

FIG. 15 is a block diagram showing a configuration of data receiving apparatus 20 according to the present embodiment. The same reference numerals are given to the same or corresponding parts as in the above-described embodiment, and the description is omitted. The buffer 26 is composed of a data buffer for storing the received data S20 decomposed and output by the cell decomposing unit 21 and a time stamp buffer for storing the received time stamp S21, and temporarily stores the received data S20 and the received time stamp S21. The received data S is accumulated according to the reproduced clock S25 output from the PLL circuit 25.
26 and the reception time stamp S21.

The operation will be described. Data transmission device 1
The cell transmitted from 0 is decomposed by the cell decomposing unit 21 into the reception data S20 and the reception time stamp S21, and the decomposed reception data S20 and the reception time stamp S2
1 is stored in the buffer 26. At this time, buffer 2
6 stores one or a plurality of reception time stamps S21 according to the state of the cell delay fluctuation of the transmission path.

The reception time stamp S21 stored in the buffer 26 is read out according to the reproduction clock S25 output from the PLL circuit 25, and output to the time stamp correction means 22.

Thereafter, similarly to the above-described embodiment, the correction time stamp S22 is output from the time stamp correction means 22 to the comparator 23, and the reproduction cycle Tr S
23 is reproduced. Then, the clock is reproduced by the PLL circuit 25 using the reproduction cycle Tr S23, and the reproduction clock S25 is output.

As described above, according to the present embodiment, the reception time stamp is temporarily stored in the buffer and read from the buffer according to the reproduction clock so that the reception time stamp is not affected by the cell delay fluctuation in the transmission path. And the disturbance of the reproduction clock can be suppressed.

Embodiment 6 FIG. In the above-described embodiment, when the transmission time stamp is mapped to the cell by the cell assembling unit, the transmission time stamp is mapped to a cell having an odd sequence number (hereinafter, referred to as an odd cell). In the following, an embodiment will be described in which a transmission time stamp is mapped to a cell having an even sequence number (hereinafter, referred to as an even cell) to compensate for a loss in the reception time stamp.

FIG. 16 is a conceptual diagram showing how cell assembling section 14 maps transmission time stamps to cells in the present embodiment. The same reference numerals are given to the same portions as those in the above-described embodiment, and the description is omitted. Cell assembly unit 14
When assembling and transmitting a cell using transmission data and the transmission time stamp output from the latch 13, the same transmission time stamp information constituting the transmission time stamp is mapped to a plurality of cells.

The operation will be described. When mapping the 4-bit transmission time stamp S15 to eight cells, the cell assembling unit 14 converts the 1-bit transmission time stamp information of the 4-bit transmission time stamp S15 into two consecutive cells ( (Odd cell and even cell). That is, in FIG. 16, after mapping the 1-bit transmission time stamp information of the transmission time stamp S15 to the odd cell C1, the same 1-bit transmission time stamp information is mapped to the subsequent even cell C2. Similarly, odd cell C3 and even cell C4, odd cell C
5 and the even cell C6, and the same 1-bit transmission timestamp information is mapped to each of the odd cell C7 and the even cell C8.

In the data receiving apparatus 20, when a fault in the transmission path detectable from the sequence number, for example, the fault detecting means 33b detects a cell loss of an odd cell, the information of the reception time stamp S21 of the even cell is referred to. To compensate for the loss of the reception time stamp information.

Then, the corrected time stamp created by using the supplemented information of the received time stamp is output from the time stamp correcting means 22 to the comparator 23, and the reproducing cycle Tr S23 is reproduced by the comparator 23. Furthermore, P
The clock is reproduced by the LL circuit 25 using the reproduction cycle Tr S23, and the reproduction clock S25 is output.

As described above, according to the present embodiment, the transmission side maps transmission time stamp information of 1 bit of a transmission time stamp of 4 bits into two consecutive cells (odd cell and even cell). Then, when the receiving side detects a failure in the transmission path of the odd-numbered cell, by referring to the information of the receiving timestamp of the even-numbered cell to compensate for the loss of the information of the receiving timestamp, a single cell loss occurs. Also, the loss of the reception time stamp can be compensated by the data receiving device, and a stable reproduction clock can be obtained.

In the present embodiment, a case has been described in which a 4-bit transmission time stamp is mapped to eight cells. However, the present invention is not limited to this. Even if the number of cells is changed, the same effect as in the present embodiment can be obtained.

Also, a case has been described where the transmission time stamp information of each bit of the transmission time stamp is mapped to two consecutive cells (odd cell and even cell), but the transmission time stamp information is mapped to a plurality of cells. What is necessary is just to map, and it is not limited to this.

For example, as shown in FIG. 17, after mapping the transmission time stamp information for each bit of the transmission time stamp S15 to odd cells, the same transmission time stamp information is mapped to even cells in the next 8-cell cycle. You may do it. Thereby, even when a plurality of cells are lost, the loss of the reception time stamp can be compensated by referring to the information of the reception time stamp in the next 8-cell cycle in the data receiving device. Furthermore, the same effect can be obtained even if the same transmission time stamp information is mapped to a plurality of cells irrespective of odd cells and even cells.

Although the embodiments of the invention have been described separately in this specification, it is of course possible to combine a plurality of these configurations. In each embodiment of the present invention, ATM communication is described as a model, but the present invention can be applied to other than ATM communication.

[0122]

As described above, according to the source clock reproducing apparatus of the present invention, transmission consisting of difference information between the count value obtained by counting up the network clock and the cycle obtained by dividing the source clock is performed. The transmission time stamp generated on the transmission side is received via a transmission path, the reception time stamp is corrected, a correction time stamp is generated, and the source clock is reproduced using the correction time stamp, thereby achieving stable reproduction. You can get a clock.

Further, according to the source clock reproducing apparatus of the next invention, a calculated difference value which is a difference between two reception time stamps received at regular intervals among the plurality of reception time stamps sequentially received, By selecting one of the preset difference values, generating a correction timestamp using the selected difference value, and reproducing the source clock using the correction timestamp, stable reproduction at normal time Not only can a clock be obtained, but also a reproduced clock can be obtained without giving any great disturbance in any state.

Further, according to the source clock reproducing apparatus of the next invention, at the time of reset and / or when a failure occurs in the transmission line, a preset default difference value is selected to generate a correction time stamp, and the correction time stamp is generated. By regenerating the source clock by using, not only can a stable recovered clock be obtained during normal operation, but also, especially during initial startup, reset, cell discard and / or when a failure occurs in the transmission path. A reproduced clock can be obtained without giving any disturbance.

Further, according to the source clock reproducing apparatus of the next invention, a calculation difference value calculated from two reception time stamps received at regular intervals among a plurality of reception time stamps sequentially received is a time difference. When the value is out of the allowable setting range as the stamp difference value, a correction time stamp is generated using a preset default difference value, and the source clock is reproduced using the correction time stamp, thereby stabilizing the normal time. Not only can a reproduced clock be obtained, but also when a value outside the allowable setting range as a timestamp difference value occurs, for example, when an invalid timestamp is received, a large disturbance is not caused. A reproduction clock can be obtained.

Further, according to the source clock reproducing apparatus of the next invention, the counter is extended, the operation clock is increased, and correction is performed using the total difference value obtained by adding a plurality of calculation difference values including the past calculation difference value. By generating the time stamp, it is possible to generate a corrected time stamp with a small error (fluctuation), and to average the error given to the reproduction cycle, thereby reducing the jitter of the reproduction clock.

According to the source clock reproducing apparatus of the next invention, the received time stamp is temporarily stored in the time stamp buffer, read from the buffer according to the reproduced clock, and output to the time stamp correcting means.
It is possible to prevent the reception time stamp from being affected by the cell delay fluctuation in the transmission path, and to suppress the disturbance of the reproduced clock.

Furthermore, according to the data transmission apparatus of the next invention, when assembling and transmitting a cell using transmission data and a transmission time stamp, the same transmission time stamp information constituting the transmission time stamp is transmitted. By mapping to a plurality of cells, it is possible to compensate for the loss of the reception time stamp on the receiving side, and to obtain a stable recovered clock even when a cell is discarded or a failure occurs.

Further, according to the data receiving apparatus of the next invention, the reception time stamp information is supplemented by referring to any one of a plurality of identical reception time stamp information constituting the reception time stamp. , It is possible to obtain a stable reproduced clock even when a cell is discarded or a failure occurs.

Further, according to the data transmission system of the next invention, when the transmitting side assembles and transmits a cell using the transmission data and the transmission time stamp, the same transmission time constituting the transmission time stamp is used. The stamp information is mapped to a plurality of cells, and the reception time stamp information is supplemented by referring to any one of the plurality of identical reception time stamp information constituting the reception time stamp on the reception side, and the reception time stamp is corrected. Accordingly, a stable reproduced clock can be obtained even when a cell is discarded or a failure occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission system according to Embodiment 1 of the present invention.

FIG. 2 is a conceptual diagram showing a configuration of a cell.

FIG. 3 is a conceptual diagram showing how transmission time stamps are mapped to cells in Embodiment 1 of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a time stamp correction unit according to the first embodiment of the present invention.

FIG. 5 is a conceptual diagram showing a normal operation concept of the time stamp correction unit.

FIG. 6 is a conceptual diagram showing an operation concept at the time of reset of a time stamp correction unit.

FIG. 7 is a block diagram showing a configuration of a time stamp correction unit according to Embodiment 2 of the present invention.

FIG. 8 is a conceptual diagram illustrating an operation concept of the time stamp correction unit when a failure occurs.

FIG. 9 is a block diagram showing a configuration of a time stamp correction unit according to Embodiment 3 of the present invention.

FIG. 10 is a conceptual diagram illustrating an operation concept when a calculation difference value outside the allowable setting range of the time stamp correction unit occurs.

FIG. 11 is a block diagram showing a configuration of a time stamp correction unit according to Embodiment 4 of the present invention.

FIG. 12 is a block diagram showing a configuration of a data receiving device according to Embodiment 4 of the present invention.

FIG. 13 is a conceptual diagram showing the concept of the operation of a time stamp correction unit according to Embodiment 4 of the present invention.

FIG. 14 is a block diagram illustrating a configuration of a time stamp correction unit when an N + k bit counter is used.

FIG. 15 is a block diagram showing a configuration of a data receiving device according to Embodiment 5 of the present invention.

FIG. 16 is a conceptual diagram showing how transmission time stamps are mapped to consecutive cells according to Embodiment 6 of the present invention.

FIG. 17 is a conceptual diagram showing how transmission time stamps are mapped to cells of eight periods in Embodiment 6 of the present invention.

FIG. 18 is a block diagram illustrating a configuration of a conventional clock recovery circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 SAR header separation part 2 Sequence number frequency difference information detection part 3 Sequence number monitoring part 4 Frequency difference information management prediction processing part 5 Memory 6 Clock reproduction part 10 Data transmission device 11 4 bit counter 12 Divider 13 Latch 14 Cell assembly part REFERENCE SIGNS LIST 15 transmission line 20 data receiving device 21 cell decomposition unit 22 time stamp correction means 23 comparator 24 comparator mask counter 25 PLL circuit 26 buffer 27 clock generation means 28 5-bit counter 31 default output means 32 difference calculation circuit 33a reset signal detection means 33b Failure detection means 33c Difference determination means 34 Selector 35 Adder 36 Register 37 First adder 38 Second adder C0-C15 cells

Claims (9)

[Claims] 1. A time stamp generated and transmitted on a transmission side, which is information on a difference between a count value obtained by counting up a network clock and a cycle obtained by dividing a source clock, is received via a transmission line. A time stamp correction unit that corrects the received time stamp to output a corrected time stamp; a counter that counts up the network clock and outputs a count value; and a correction that is output from the time stamp correction unit. A comparator that reproduces the period using a time stamp and a count value output from the counter and outputs a reproduction period, and reproduces the source clock using the reproduction period output from the comparator and reproduces the source clock. And a PLL circuit for outputting a clock. 2. The time stamp correction means for outputting the corrected time stamp calculates a difference between two time stamps received at a constant period interval among a plurality of time stamps received sequentially, and calculates the calculated difference value. , A default output means for outputting a preset default difference value, and one of a calculated difference value output from the difference calculation circuit and a default difference value output from the default output means. A selector for selecting and outputting the difference value as a difference value; and an adder for recursively generating and outputting a new correction time stamp by adding the difference value output from the selector to the correction time stamp previously output. The source clock reproducing device according to claim 1, wherein: 3. The time stamp correction unit includes a detection unit that outputs a detection signal to the selector at the time of reset and / or when a failure occurs in the transmission path, and the selector outputs a detection signal to the detection signal output from the detection unit. 3. The apparatus according to claim 2, wherein the apparatus is configured to select the default difference value on the basis of the default value. 4. The time stamp correction unit determines whether a calculated difference value output from the difference calculation circuit is a value within a predetermined allowable setting range. A difference determination unit that outputs a fraud detection signal to the selector, wherein the selector is configured to select the default difference value based on the fraud detection signal output from the difference determination unit. The source clock reproducing device according to claim 2. 5. A time stamp correcting means for outputting the corrected time stamp calculates a difference between two time stamps received at a constant period interval among a plurality of time stamps received sequentially, and calculates a calculated difference value. , A register for storing the calculation difference value output from the difference calculation circuit, and a plurality of calculation difference values including the calculation difference value stored in the register are added to output a total difference value A second adder for adding a total difference value output from the first adder to the previously output corrected time stamp and recursively generating and outputting a new corrected time stamp. And the clock generating means for receiving the network clock as input and generating a clock corresponding to the number of calculation difference values added by the first adder. 2. The source clock reproducing device according to claim 1, wherein the source clock reproducing device is configured to count up with a clock generated by the clock generating means and output a count value. 6. A time stamp buffer for temporarily accumulating the received time stamp and outputting the time stamp to the time stamp correction means in accordance with a reproduction clock output from the PLL circuit. 2. The source clock reproducing device according to 1. 7. A transmission time stamp generating means for generating a time stamp comprising difference information between a count value obtained by counting up a network clock and a cycle obtained by dividing a source clock, and a plurality of transmission data. When assembling and transmitting a plurality of cells using the timestamp generated by the transmission timestamp generating means, a cell assembling unit that maps the same timestamp information constituting the timestamp to a plurality of cells. A data transmission device, comprising: 8. A cell containing a time stamp and transmission data, which are difference information between a count value obtained by counting up a network clock and a cycle obtained by dividing a source clock, is received via a transmission line. A cell decomposer that disassembles the cell to output a time stamp and transmission data, and the time stamp by referring to any one of a plurality of pieces of the same time stamp information constituting the time stamp output from the cell decomposer. A time stamp correction means for supplementing information, correcting the time stamp and outputting a corrected time stamp, a counter for counting up the network clock and outputting a count value, and a correction time output from the time stamp correction means Using the stamp and the count value output from the counter, reproduce the period and output the reproduction period And reproducing the source clock using a reproduction cycle output from the comparator,
Data comprising: a PLL circuit for outputting a reproduction clock; and a buffer for temporarily storing transmission data output from the cell disassembly unit and outputting the transmission data in accordance with the reproduction clock output from the PLL circuit. Receiver. 9. A transmission time stamp generating means for generating a time stamp comprising difference information between a count value obtained by counting up a network clock and a period obtained by dividing a source clock, and a transmission time stamp. When assembling and transmitting a cell using data and a time stamp generated by the transmission time stamp generating means, a cell assembling unit that maps the same time stamp information constituting the time stamp to a plurality of cells. A data receiving device configured to decompose a cell assembled by the cell assembling unit and transmitted via a transmission line, and output a time stamp and transmission data; and a time output from the cell decomposing unit. The above time stamp information is supplemented by referring to any one of a plurality of the same time stamp information constituting the stamp, and A time stamp correction unit that corrects the time stamp and outputs a corrected time stamp; a counter that counts up the network clock and outputs a count value; and a correction time stamp output from the time stamp correction unit and the counter. A comparator for reproducing the period using the output count value and outputting a reproduction period, and a PLL circuit for reproducing the source clock using the reproduction period output from the comparator and outputting the reproduction clock And a buffer for temporarily storing transmission data output from the cell disassembly unit and outputting the transmission data in accordance with a reproduction clock output from the PLL circuit.