JP2762550B2 - Control system - Google Patents

Description

The present invention relates to a control system including a process I / O coupled to a process and a processor for controlling the process I / O. The present invention relates to a system in which a power supply unit for a processor and a power supply unit for a process I / O are independently configured, and to a control system in which measures are taken against a power failure or voltage drop of an AC power supply connected to each of these power supply units.

<Conventional technology> Process I / O coupled to a process and this process I / O
Is configured to perform a control operation according to the power outage time after the power outage is recovered (power recovery) when the power supply is interrupted.

That is, the power supply unit or the processor is provided with, for example, a unit for measuring a power failure time and a unit for reading the measured time. If the power failure time is shorter than a predetermined time (in the case of a momentary power failure), the processor Controls to return to the value output by the process I / O just before the power failure.If the power failure continues for a long time, the output value of the process I / O initialized by the power failure Follow,
Control is started from there.

FIG. 4 is a configuration conceptual diagram showing an example of a conventional control system having such functions.

In the figure, PC is the processor section, PS0 is the processor section P
A power supply unit for a processor for supplying power to C, and SI is a first bus relay device for data transmission and is a processor bus.
It is connected to the processor PC via BS1.

IO1 to IOn are multiple process I / Os, PS1 is each process I / O
An I / O power supply unit NC for supplying power to the power supply is a second bus relay device, which is connected to each process I / O via an I / O bus BS2. BS3 is a system bus connecting the first bus relay device SI and the second bus relay device NC.

TM runs on battery inside processor PC
A timer composed of CMOS detects that the DC power supplied to the processor PC turns off, and
Measure the time in the off state.

After the power is restored, the processor PC reads the value measured by the timer TM, compares the measured time with the measured value (power failure time), and if the power failure time is shorter than the predetermined time, processes the process immediately before the power failure. The control operation is performed so as to immediately return to the value output by the I / O. If the power outage time is long, the operation first follows the output value of the process I / O, and the control is started from there.

<Problem to be Solved by the Invention> The system configured as described above includes the power supply units PS
0, AC power supplied from outside to PS1 is as shown in Fig. 5 (a)
When a power failure occurs such that there is a period during which the voltage becomes zero as shown in (1), the power to each of the power supply units PS0 and PS1 is almost simultaneously cut off, so the voltage of one of the processor power supply units PS0 is monitored. By doing so, the system can be managed.

However, when the AC power supplied to each of the power supply units PS0 and PS1 undergoes a halfway power failure or voltage drop such as a temporary voltage drop as shown in FIG. Between PS1, a state occurs in which one power failure occurs while the other does not. In this case, if only the power supply unit for I / O PS1 fails, the data transfer from the processor unit PC to the process I / O becomes an error.

The present invention has been made in view of such a point, and an object of the present invention is to generate a data transfer error when a supply voltage is abnormal in a system in which a processor power supply unit and a process power supply unit are configured independently. The object of the present invention is to realize a control system with stable operation without using the control system.

<Means for Solving the Problems> The present invention for solving the above problems includes a processor unit,
A first bus relay device connected thereto via a processor bus, a processor power supply unit for supplying DC power to the processor unit and the first bus relay device, and at least one process I / O; A second bus relay device connected thereto via an I / O bus, and a process of supplying DC power to the process I / O and the second bus relay device.
An I / O power supply unit, wherein the processor unit transmits data to and from the process I / O via a first bus relay device, a second bus relay device, and a system bus connecting them. A control system for performing a predetermined control operation, wherein the second bus relay device detects whether or not the DC power supply voltage supplied from the process I / O power supply unit has become a voltage state equal to or lower than a specified value. A voltage detection unit, comprising a driver unit that receives an output from the voltage detection unit and outputs a power fail signal via a signal line of the system bus when the DC power supply voltage is equal to or lower than a specified value, The first bus relay device includes a read unit for transmitting a power fail signal transmitted through a signal line of the internal bus to the processor unit.

<Operation> When a power failure occurs in the process I / O power supply unit that supplies DC power to the process I / O and the second bus relay device, the voltage detection unit in the second bus relay device detects this. The driver unit transmits a power fail signal to the processor unit via the system bus and the first bus relay device.

When receiving the power fail signal via the first bus relay device, the processor unit suspends the control operation. This makes it possible to prevent a data transfer error from the processor unit to the process I / O at the time of a halfway power failure of the power supply.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a conceptual view of the configuration of the entire system according to the present invention. In the figure, PC is a processor unit, PS0 is a processor power supply unit that supplies power to the processor unit PC,
SI is a first bus relay device for data transmission and is connected to the processor unit PC via the processor bus BS1.

IO11 to IOmn are multiple process I / Os, PS1 to PSm are I / O power supply units that supply power to each process I / O, NC1 to NCn
Is a second bus relay device, which is connected to each process I / O via an I / O bus BS2. BS3 is a system bus that connects the first bus relay device SI and each second bus relay device NC.
Here, n is one I / O subsystem, consisting of m I / O subsystems, and corresponding to each subsystem, the process I / O power supply units are also PC1 to PCm m I have prepared. Their main overall configuration is the same as that of the conventional system shown in FIG.

FIG. 2 is a block diagram showing the configuration of the system bus BS3 and the first bus relay device SI and the second bus relay device NC connected to this bus.

In the system bus BS3, in addition to the data bus DB for data transmission, a line L1 for transmitting a power failure signal indicating a power failure of the I / O power supply units PS1 to PSm to the first bus relay device SI, a process power supply Unit PS0 voltage output and I /
A power supply line VTT in which the voltage outputs of the O power supply units PS1 to PSm are respectively output via diodes D1 and D2.
And

In the second bus relay device NC, reference numeral 11 denotes a voltage detection unit that detects whether the DC voltage V2 supplied from the I / O power supply unit PS1 (PS2... PSm) has dropped below a specified value, and 12 denotes a voltage detection unit. When the output signal from the unit 11 indicates that the DC voltage V2 has dropped below the specified value, the driver unit for activating the power fail signal on the line L1; 13 is the system of the second bus relay device NC. An attachment / detachment detection unit 14 for detecting detachment from the server is a maintenance switch that is turned on when the second bus relay device NC is in operation and the operation is checked or maintenance is performed.

Reference numeral 15 denotes a mask function unit that inhibits the driver unit 12 from activating the signal on the line L1, and receives a signal from the attachment / detachment detection unit 13 and a signal from the maintenance switch 14.

D1 outputs the DC voltage supplied from the I / O power supply unit PS1 to the line VTT, and outputs the driver unit 12, the mask function unit 15
Is a diode to give.

In the first bus repeater SI, reference numeral 21 denotes a buffer gate for inputting a signal on the line L1, and reference numeral 22 reads a signal on the line L1 via the buffer gate 21, and the processor bus BS1
A signal reading means for transmitting the signal to the processor unit PC via the buffer gate 23 and a timing control means 24 for controlling the gates 21 and 23.

D2 is DC supplied from the processor power supply unit PS0
A diode for outputting a voltage to the power supply line VTT.

FIG. 3 is a connection diagram showing a specific configuration of the second bus relay device NC.

The voltage detection unit 11 is configured to include, for example, a comparator. The voltage detection unit 11 compares a DC voltage (+5 V) V2 applied from the power supply unit for I / O PS1 via the connector CC1 with a specified value, and compares the DC voltage V2 Is lower than the specified value, the output of the R terminal is set to low level. The driver unit 12 includes an inverter INV1 to which a signal from the voltage detection unit 11 is applied, and a transistor Q1 that is turned on when an input to the inverter goes to a low level and activates a signal (power fail signal) on the line L1. It is composed of Here, even if the DC voltage V2 supplied via the diode D1 falls below the operating range of the inverter INV1, the DC voltage V2 is supplied via the diode D2, the line VTT, and the resistors R1, R2 of the first bus relay device SI. Since a DC voltage is supplied from the processor power supply unit PS0, the transistor Q1 is kept on.

When the DC voltage V2 from the I / O power supply unit PS1 is maintained at a normal value, the input of the inverter INV1 is at a high level, the base of the transistor Q1 is at the ground level, and is in an off state. .

The attachment / detachment detection unit 13 is configured by a connector CC2, and when the second bus relay device NC is mounted on the system, a common potential on the system side is output as a status signal via the connector CC2. . Here, the connectors CC1 and CC2 are connected so that the connector CC2 is disconnected first and then the connector CC1 is disconnected when the second bus relay device NC is removed from the system. The lengths P1 and P2 between the terminals are selected.

The mask function unit 15 includes a transistor Q2 that is turned on when the attachment / detachment detection unit 13 detects attachment / detachment of the second bus relay device NC from the system, and a transistor Q3 that is turned on when the maintenance switch 14 is on. In addition, the outputs of these transistors Q2 and Q3 are applied to the base of the transistor Q1 via the diode D3 to mask the ON / OFF operation of Q1. Here, the bases of the transistors Q2 and Q3 are connected to a power supply line VTT provided on a bus in the system via resistors R3 and R4, respectively, and power is supplied from the power supply line VTT.

The operation of the system configured as described above will now be described.
In the following description, the voltage drop of the AC power supply is in an incomplete state as shown in FIG.
It is assumed that at least one of the power supply units PS1 to PSm detects a power failure, but the processor power supply unit PS0 does not detect a power failure and continues to operate normally.

When the power supply unit for process I / O PS1 detects a power failure,
The supply of the DC voltage V2 to each process I / O is stopped. When the supply of the DC voltage V2 stops, the voltage detection unit 11 in the second bus relay device NC detects this, and the driver unit 12 activates the power fail signal on the line L1.

The power fail signal on the line L1 is a low active signal and the wired-OR state between each I / O subsystem. Even if one process I / O power supply unit PS1 detects a power failure, I / O power supply unit P
The state becomes the same as when S1 to PSm detects a power failure.

The power fail signal transmitted via line L1 is
Buffer gate 21 of first bus relay device SI, reading means
It is transmitted to the processor unit PS via 22.

The processor unit PC detects an error when performing an access to the process I / O during the power failure while performing the control operation for the process I / OIO11 to IOmn. From the state of the power fail signal read via the terminal 22, it is possible to immediately know the power outage of the process I / O. Therefore, when the active state of the signal of the power failure is detected, the control operation for the process I / O is immediately interrupted and brought into the wait state until the power is restored.

When in this wait state, the processor unit PC performs an operation of measuring the wait time and monitors the state of the power fail signal. When the power recovery of the process I / O power supply unit is detected, the measurement of the wait time is stopped, and whether the wait time corresponds to a predetermined momentary power outage time or a long time power outage (long power outage) is determined. to decide.

Here, if it is determined that the instantaneous power failure has occurred, the control operation is started after the output of the process I / O is returned to the value output immediately before the power failure.

If it is determined that a long suspension has occurred, the control operation is started after first following the output value of the process I / O initialized by the power failure.

In the system of the present invention, a means for detecting a power failure of the process I / O power supply unit and transmitting the detected power failure to the first bus relay apparatus SI is provided in the second bus relay apparatus NC. The processor unit receives a power fail signal indicating a power failure of the process I / O power supply unit,
By interrupting the control of the process I / O, an access error to the process I / O during the power failure can be eliminated.

The second bus relay device NC is also provided with a detachment detection unit 13 and a maintenance switch 14. Next, these operations will be described.

When maintenance or inspection is performed for each I / O subsystem in each process I / O, in the corresponding second bus relay device NC,
The maintenance switch 14 is turned on. In this state, since the mask function unit 15 receives a signal indicating the ON state from the maintenance switch 14 and masks the operation of the driver unit 12, even if the process I / O power supply unit PS1 is turned off to perform maintenance or inspection. , The power fail signal on line L1 does not become active. Therefore, maintenance or inspection of the corresponding I / O subsystem does not affect other parts.

Even when the second bus relay device NC itself is maintained and inspected, the maintenance switch 14 is turned on, so that influence on other parts can be prevented. Further, in this case, even if the second bus relay device NC is removed from the system without turning on the maintenance switch 14, the detachment detection unit 13 detects the removal by the voltage detection unit.
11 detects the power failure before detecting
Activate 15 to prevent the power fail signal on line L1 from becoming active.

Therefore, removal of the second bus relay device NC from the system does not affect other parts.

The above description is based on the assumption that the voltage drop of the AC power supply is in an incomplete state as shown in FIG. 5 (b), but the power failure state as shown in FIG. 5 (a) is assumed. If a power failure occurs, a power failure occurs in the entire system, and after the power recovery, a control operation according to the power failure time is performed.

That is, during a power outage, the power outage time is measured, and in the case of an instantaneous power outage, the control operation is started after returning the output of the process I / O to the value output immediately before the power outage, and If it is a power failure, the control operation is started after first following the output value of the process I / O initialized by the power failure.

In the above-described embodiment, the attachment / detachment detection unit 13, the maintenance switch 14, and the mask function unit 15 are provided so that the maintenance can be performed with the second bus relay device NC removed from the system. Not.

<Effects of the Invention> As described in detail above, according to the present invention, there is no need to cooperate with respect to a power failure between the power supply unit for the processor and the power supply unit for the process I / O. A system that can be set close to the system and that is not significantly affected by power supply fluctuations can be realized.

In addition, by providing the mask function unit, the attachment / detachment detection unit, and the maintenance switch, the maintenance of the second bus relay device and the maintenance of each I / O subsystem can be performed without special consideration.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of the entire system according to the present invention, FIG. 2 is a block diagram showing the internal bus and the configuration of a first bus relay device and a second bus relay device connected to the bus, and FIG. Is a connection diagram showing a specific configuration of the second bus relay device, FIG. 4 is a configuration conceptual diagram showing an example of a conventional control system, and FIG. 5 is a diagram showing a voltage waveform in a power failure state of an AC power supply. . PC: Processor unit SI: First bus relay device PS0: Processor power supply units IO11 to IOmn: Process I / O PS1 to PSm: Process I / O power supply unit BS1: Processor bus BS2 I / O bus BS3… System bus 11… Voltage detection unit 12, Driver unit 13… Removal detection unit 14, Maintenance switch 15… Mask function unit 21… Buffer gate 22… Readout means

Claims (4)

(57) [Claims] 1. A processor unit, a first bus relay unit connected to the processor unit via a processor bus, a processor power supply unit for supplying DC power to the processor unit and the first bus relay unit, At least one process
A process I / O power supply for supplying DC power to the I / O, a second bus relay device connected thereto via an I / O bus, and the process I / O and the second bus relay device The processor unit performs data transmission between a first bus relay device, a second bus relay device, and process I / O via a system bus connecting them, and performs a predetermined control operation. A second bus relay device, wherein the second bus relay device, a voltage detection unit that detects whether the DC power supply voltage supplied from the process I / O power supply unit has become a voltage state equal to or less than a specified value, A driver unit that receives an output from the voltage detection unit and outputs a power fail signal via a signal line of the bus in the system when the DC power supply voltage is equal to or less than a specified value; The relay device transmits a signal of the bus in the system. Reading means for transmitting a power fail signal transmitted through the first bus relay device to the processor unit, and the processor unit controls the process I / O upon receiving the power fail signal via the first bus relay device. A control system for relaying an operation. 2. A second bus relay device, comprising: a detachment detection unit for detecting that the second bus relay device has been removed from the system; a maintenance switch; a signal from the detachment detection unit and the maintenance. The control system according to claim 1, further comprising: a mask function unit that receives a signal indicating that the power switch is on, and prohibits a function of transmitting a power fail signal from the driver unit. 3. The system bus includes a DC power supply voltage supplied from a processor power supply unit via a diode and a DC power supply voltage supplied from a process I / O power supply unit.
A power supply line (VTT) supplied with a power supply voltage, wherein the driver unit in the second bus relay device is configured to operate by being supplied with power also from the power supply line (VTT). The control system as described. 4. An internal system bus includes a DC power supply voltage supplied from a processor power supply unit via a diode and a DC power supply voltage supplied from a process I / O power supply unit.
A power supply line (VTT) to which a power supply voltage is applied, wherein the mask function unit in the second bus relay device is configured to operate by being supplied with power also from the power supply line (VTT). A) the control system described.