JP2760756B2 - Digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter including a plurality of stages of delay elements, and more particularly to processing at the end of a signal such as the start and end of filtering.

[0002]

2. Description of the Related Art Generally, in a system for performing digital processing, a digital filter is frequently used.
A digital filter of a type or IIR type includes a delay circuit including a plurality of stages of delay elements for sequentially delaying an input signal in synchronization with a clock signal.

[0003] Conventionally, a process of multiplying the output itself of these delay elements by a predetermined coefficient as necessary and adding the obtained multiplication result has been performed.

[0004]

When a filtering process is performed by a digital filter, invalid data exists before and after the end of the portion where the filtering process starts and ends. Therefore, in the above-described delay circuit including a plurality of delay elements, the processing is performed while the invalid data existing before and after at the end is included, and the deviation from the actual data occurs more or less. However, in the conventional configuration, regardless of whether the data to be processed is at the end or not, the outputs of the delay elements in a plurality of stages are always used as they are, and no measures have been taken against this.

[0005]

According to the present invention, a first delay means comprising a plurality of delay elements for sequentially delaying an input signal in synchronization with a clock signal, and an effective area signal indicating an effective area of data are provided. A second delay unit comprising a plurality of delay elements for sequentially delaying in synchronization with a clock signal; and a data capturing unit for capturing the input signal in response to a data load signal synchronized with a rise or fall of the effective area signal. The output of the delay element of each stage of the delay means is input to one end, the output of the capturing means is input to the other end, and one of the outputs is output by the delay element of the corresponding stage of the second delay means. The object is achieved by providing a plurality of switch means for selectively outputting an input.

[0006]

According to the present invention, at the end of the start and end of the signal, the data at the end, which is the input signal, is selectively output instead of the output of the delay element by the switch means. Instead of being used, the data at the extreme end is used redundantly for the filtering process.

[0007]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, showing an example of a 3-tap FIR type digital filter. In the figure, reference numeral 1 denotes a first delay circuit comprising three D flip-flops 2, 3, and 4 connected in series for sequentially delaying an input signal IN in synchronization with a clock signal CLK; A second delay circuit 9 composed of three D flip-flops 6, 7, 8 connected in series for sequentially delaying in synchronization with the signal CLK is a data load signal LOA generated based on the effective area signal.
D flip-flop in which D is input as a clock and an input signal IN is applied to a data input terminal D, 10, 11, 1
2 receives the outputs T1, T2, and T3 of the D flip-flops 2, 3, and 4 at one end, and receives the output DT of the D flip-flop 9 at the other end. According to the outputs W1, W2, W3 of 7, 8
Select one of the inputs and tap TP1, TP,
These switches output to TP3. These switches are multiplied by coefficients K1, K2, and K3 as necessary, and the multiplication result is added by the adder 13. Of course, if the coefficient is 1, there is no need for multiplication.

This embodiment has an optimum configuration as a digital filter used in a display device. In this embodiment, an effective area signal WIN and a data load signal LOAD are used as an effective pixel area signal DISPWIN indicating an effective pixel area of the display apparatus.
Is generated by the circuit of FIG. In FIG. 2, reference numeral 20 denotes a D flip-flop for inputting an effective pixel area signal DISPWIN to a data terminal D and inputting a clock signal CLK as a clock;
An OR gate 22 that receives a Q output of 0 and an effective pixel area signal DISPWIN and generates an effective area signal WIN as an output. The OR gate 22 includes a D flip-flop 23 and an exclusive NOR gate (E-NOR gate) 24, and the rising edge of the signal WIN. And a cutout circuit that outputs a signal LOAD of H level for one cycle period of the clock pulse CLK in synchronization with the falling edge.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. As shown in FIG. 3A, input signals D1, D2,
When D3,..., And Dn are input, the signals of the D flip-flops 2, 3, and 4 output the signal T obtained by delaying the input signal by one cycle, two cycles, and three cycles of the clock pulse, respectively.
1, T2 and T3 are output as shown in FIG.

The effective pixel area signal DISPWIN is
As shown in FIG. 3, the valid data D1, D2, D3,.
,..., Becomes L level only during the period in which Dn exists, and goes to H level in the period before and after invalid data.
This signal DISPWIN is delayed by one clock in the D flip-flop 20, and the delayed signal DWIN (FIG.
) And the signal DISPWIN are ORed by the OR gate, so that a signal which is at L level only when both signals are at L level is generated, and this signal becomes the effective area signal WIN as shown in FIG. .

In the D flip-flops 6, 7, and 8, the signal WIN is sequentially delayed in synchronization with the clock CLK, and the outputs W1, W2, and W3 are output from the clocks as shown in FIGS. The pulse is delayed by one cycle, two cycles, and three cycles, respectively. Further, the signal WIN is
Since the signal is input to the cutout circuit 22, a signal LOAD which becomes H level only for one cycle period of the clock pulse CLK is output in synchronization with the rise and fall of the signal WIN, as shown in FIG. Then, the D flip-flop 9 takes in the input signal at that time in response to the rise of the signal LOAD. Therefore, as shown in FIG. 3, the start data D1 of the effective pixel area is taken in at the time of the rise, and the start data is started until the next rise. Data D1 is held in D flip-flop 9. Since the next rising occurs in the last portion of the effective pixel area, the final data Dn is captured and held in the D flip-flop 9 at this time.

In this embodiment, an example of three taps is shown. Considering the output T2 of the second tap as a center, when the output T2 is the start data D1, the output T2 is indicated by oblique lines in FIGS. As shown, the output T1 is D2 one clock later, but the output T3 contains invalid data XX one clock before the start data D1. The output T2
Is the end data Dn, the output T3 is Dn-1 one clock before, as shown by hatching in FIG. 3, c, d, and e, but the output T1 has invalid data one clock after the end data. XX will be included.

Therefore, conventionally, a filtering process has been performed while including such invalid data. However, in this embodiment, the switches 10, 11, and 12
When the switching signals W1, W2, W3 are at the L level, the outputs T1, T2, T3 are selected and TP1, TP
2 and TP3 as they are, but the signals W1 and W
2, when W3 goes high, the output DT of the D flip-flop 9 is selected instead of the outputs T1, T2, and T3 and output from TP1, TP2, and TP3.

Therefore, at the beginning of the valid data indicated by the oblique lines in FIGS. 3A, 3B and 3C, the data D2 of T1 and the data D2 of T2 are supplied to TP1 and TP2 via switches 10 and 11, respectively.
Although 1 is output as it is, start data D1 held in DT is output to TP3 via the switch 12, and invalid data XX is not output. Also, at the end of the valid data, TP3 and TP2 have switch 1
Data Dn−1 of T3 and data D of T2 via 2, 11
Although n is output as it is, the end data Dn held in DT is output to TP1 via the switch 10, and invalid data XX is not output.

As described above, at the end of the start and end of the effective area, the data at the end is used redundantly, thereby preventing the entry of invalid data. Although the embodiment described above is a three-tap digital filter, it is needless to say that the present invention can be applied to a digital filter having a larger number of taps. In addition, the present invention is naturally applicable not only to the FIR type but also to a different digital filter such as the IIR type.

[0016]

According to the present invention, at the ends of the start and end of the signal, the data at the extreme end is used redundantly instead of the output of the delay element. Processing that does not include invalid data can be performed, and therefore, higher quality signal processing can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram showing details of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the embodiment.

[Explanation of symbols]

Reference Signs List 1 first delay circuit 2, 3, 4, 6, 7, 8, 9, 20, 23 D flip-flop 5 second delay circuit 10, 11, 12 switch 21 OR gate 22 cutout circuit 24 E-NOR gate

Claims (2)

(57) [Claims] 1. A delay means comprising a plurality of delay elements for sequentially delaying an input signal in synchronization with a clock signal, and an effective area signal indicating an effective area of data is sequentially delayed in synchronization with the clock signal. A second delay unit comprising a plurality of stages of delay elements, a data capture unit for capturing the input signal in response to a data load signal synchronized with a rise or fall of the effective area signal,
The output of the delay element of each stage of the first delay means is input to one end, the output of the capturing means is input to the other end, and the output of the delay element of the corresponding stage of the second delay means A plurality of switch means for selectively outputting one input; multiplying each output of the switch means by a coefficient;
A digital filter comprising multiplication and addition means for adding a calculation result . 2. The digital filter according to claim 1, wherein the effective area signal is a signal indicating an effective pixel area in a display device.