JP2757701B2 - Circuit for preventing electrostatic breakdown of LSI chips, etc. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for preventing electrostatic breakdown such as an LSI (Large Scale Integrated Circuit) chip or an LSI (Large Scale Integrated Circuit) chip.

[0002]

2. Description of the Related Art FIG. 3 is a schematic diagram showing a configuration example of a conventional LSI chip 1, and FIG. 4 is a partially enlarged view of FIG. The LSI chip 1 includes, for example, an analog circuit 2 constituting an 8-bit to 16-bit digital / analog converter and a digital circuit 3, and guard rings 4 and 5 around the periphery for preventing electrostatic breakdown. Are formed.

The guard rings 4 and 5 are connected to a power supply voltage V to prevent electrostatic damage.
_VDD (for example, 5 V) and V _DD for supplying a digital / analog pad for applying V _SS (for example, 0 V)
And V _SS , 8 are analog input pins, 9 is an analog output pin, 10 is a digital output pin such as an 8-bit to 16-bit bus output pin, and 11 is a digital input pin. Further, 12 is a diode for protecting a circuit inside the LSI chip 1 connected to each of the pins 6 to 11 from electrostatic damage, and 13 is a FET 13a, 13a.
Bus output buffer. The above-described components 4, 5, 12, 12,... Constitute an electrostatic breakdown prevention circuit.

[0004]

In the conventional LSI chip 1 described above, for example, the voltage at the point 14 shown in FIG. 4 changes as shown in FIG. Are turned on / off, the voltages at the point 15 of the guard ring 5 and the point 16 of the guard ring 4 change as shown in FIGS. 5B and 5C, respectively.

Thus, the point 1 of the guard ring 5
7 and the voltage at the point 18 of the guard ring 4 similarly to the voltage at the point 15 of the guard ring 5 and the voltage at the point 16 of the guard ring 4 change as shown in FIGS. 5B and 5C, respectively. Pin 8
As shown in FIGS. 5A and 5B, noise is generated in the output voltage of the nearby point 19, and a bit shift occurs in this portion. The present invention
Under such a background, it is an object of the present invention to provide an electrostatic discharge protection circuit for an LSI chip or the like in which an output voltage of an analog output pin is not affected even when an output buffer of a digital circuit is turned on / off. I do.

[0006]

SUMMARY OF THE INVENTION The present invention is based on an LSI chip or the like in which an analog circuit and a digital circuit are mixed. A guard ring is formed, first and second power supply voltages are respectively applied to the first and second guard rings, and a plurality of analog input pins and a plurality of analog output pins respectively connected to the analog circuit. And a diode or the like for preventing electrostatic breakdown between each of the plurality of digital input pins and the plurality of digital output pins respectively connected to the digital circuit and the first and second guard rings. In a circuit for preventing electrostatic destruction such as an LSI chip in which a protection circuit is inserted, the plurality of digital input pins or the plurality of A digital output pin, a point of the first and second guard rings connected via the protection circuit, and the plurality of analog input pins or the plurality of analog output pins connected to the plurality of analog output pins via the protection circuit. A resistor having a predetermined value is interposed between each point of the first and second guard rings.

[0007]

According to the above arrangement, for example, the voltage at the point of the first guard ring connected to a certain digital output pin via the protection circuit changes according to the change in the signal output from the digital output pin. However, the voltage at the analog input pin near the digital output pin or at the point of the first guard ring connected to the analog output pin via the protection circuit does not change much. Therefore, the signal input or output from the analog input pin or analog output pin is not significantly affected by the change in the signal output from the digital output pin.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows L according to an embodiment of the present invention.
FIG. 4 is a schematic diagram showing a configuration of an LSI chip 20 to which an electrostatic discharge protection circuit such as an SI chip is applied. In this figure, parts corresponding to the respective parts in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In the LSI chip 20 shown in this figure, a resistor 21 is newly inserted between the points 15 and 17 of the guard ring 5 and the point 1 of the guard ring 4 is inserted.
A resistor 22 is newly inserted between 6 and 18.
Also, between the points 23 and 24 of the guard ring 5,
A resistor 25 is newly inserted, and a resistor 28 is newly inserted between the points 26 and 27 of the guard ring 4.

That is, diodes 12, 12,... Are connected to the digital output pin 10 and the digital input pin 11, respectively.
.. are connected to the points 15, 16, 23, 26,... Of the guard rings 4 and 5 and the analog output pins 8 and the analog input pins 9 for which noise must be prevented. ,... Points 17, 18, 2 of guard rings 4 and 5 connected via
, 27,...
2, 24, 27, ... are interposed. The values of the resistors 21, 22, 25, 28,... Are, for example, about 100Ω.

In such a configuration, for example, FIG.
When the digital output buffer 13 is turned on / off by changing the voltage at the point 14 shown in FIG. 5A as shown in FIG. 5A, the voltages at the point 15 of the guard ring 5 and the point 16 of the guard ring 4 become FIG.
It changes as shown in (b) and (c).

However, since the resistors 21 and 22 are interposed, the voltage at the point 17 of the guard ring 5 and the voltage at the point 18 of the guard ring 4 are as shown in FIG.
As shown in (a) and (b), the change is caused by the resistance 2
Compared to the conventional case where 1 and 22 are not interposed,
Point 1 near the analog input pin 8
No noise is generated in the output voltage of No. 9. Therefore,
Bit shift in this portion as shown in FIG. 5D can be prevented.

In the above-described embodiment, the value of the resistors 21, 22, 25, 28,... Is set to about 100Ω, but the present invention is not limited to this. Resistance 2
In short, the values of 1, 22, 25, 28,... Indicate that the noise generated in the guard rings 4 and 5 due to the change in the voltage applied to the digital output pin 10 and the digital input pin 11 causes the analog output pin 8 and Of course, any value may be used as long as the value does not affect the analog input pin 9.

[0013]

As described above, according to the present invention, even if the output buffer of the digital circuit is turned on / off, the output voltage of the analog output pin is not affected.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration example of an LSI chip to which an electrostatic discharge protection circuit such as an LSI chip according to an embodiment of the present invention is applied.

FIG. 2 is a diagram illustrating an example of a waveform of a voltage appearing in each unit in FIG. 1;

FIG. 3 is a schematic diagram showing a configuration example of a conventional LSI chip 1.

FIG. 4 is a partially enlarged view of FIG. 3;

FIG. 5 is a diagram illustrating an example of a waveform of a voltage appearing in each unit in FIG. 4;

[Explanation of symbols]

1,20 ... LSI chip, 2 ... Analog circuit, 3 ...
... Digital circuit, 4,5 ... Guard ring, 6,7 ...
... V _DD and V _SS for digital / analog pad supply,
8: Analog output pin, 9: Analog input pin, 1
0 ... digital output pin, 11 ... digital input pin, 12, 12, ... diode, 13 ... bus output buffer, 13a ... FET, 14 to 19, 23,
24, 26, 27 ... Points 21, 22, 25, 2
7 ... Resistance.

Claims (1)

(57) [Claims] 1. An LSI chip or the like in which an analog circuit and a digital circuit are mixed, a first and a second guard ring for preventing electrostatic discharge are formed around the LSI chip. First and second power supply voltages are respectively applied to first and second guard rings, and a plurality of analog input pins and a plurality of analog output pins respectively connected to the analog circuit, and the digital circuit and An LSI in which a protection circuit such as a diode for preventing electrostatic breakdown is interposed between each of a plurality of connected digital input pins and a plurality of digital output pins and the first and second guard rings. An electrostatic discharge prevention circuit such as a chip, wherein the plurality of digital input pins or the plurality of digital output pins are Points of the first and second guard rings connected via a protection circuit, and the first and second guard rings connected to the plurality of analog input pins or the plurality of analog output pins via the protection circuit. Wherein a resistor having a predetermined value is interposed between the guard ring and a point of the guard ring.