JP2755242B2 - Error notification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an error notification system, and more particularly, to an error notification system in a bus system.

[0002]

2. Description of the Related Art A conventional bus error notification system generally includes:
When a device connected to the bus detects an error on the bus, the device outputs an error notification signal via the bus to notify occurrence of the error.

[0003] As a conventional error notification method for notifying an error type, for example, Japanese Patent Laid-Open No. 2-143630 discloses that an error type and an error detection device board can be notified by one error notification line. An error notification method has been proposed. That is, when an error is detected, an error classification unit (error editing unit) that classifies the detected asynchronous error according to the degree of the error, an error device number detection unit that detects a device number in which the error has occurred, An error notification method has been proposed, comprising: an error classification unit; an error information transmission unit that transmits an error classification detected by the error device substrate detection unit and information on the error device substrate to an error notification line based on an error information format. Have been.

FIG. 4, FIG. 5, and FIG.
FIG. 1 is a diagram for explaining an error notification method proposed in Japanese Patent No. 143630.

[0005] Referring to FIG.
The error notification method proposed in Japanese Patent Publication No. 30 is an error detecting unit 1 for detecting an input asynchronous error, an error editing unit for classifying detected errors, and a local device number output unit 3 for outputting a local device number. 5. An error information transmitting unit 4 for transmitting error information in an information format shown in FIG. 5 described below, an error information transmitting control unit for controlling the error information transmitting unit 4, an error notification line 6, and a station processor accommodating the error notification device. 7.

FIG. 5 is a diagram for explaining an error information format in the error notification system proposed in the above-mentioned Japanese Patent Application Laid-Open No. 2-143630.

Referring to FIGS. 4 and 5, error information transmitting section 4 transmits error information in the format shown in FIG. In the error information format shown in FIG. 5, bit 9 is for displaying a major alarm (MJA), bit 8 is for displaying a minor alarm, bits 0 to 7
Is for device substrate display.

Next, the operation of the error notification system proposed in Japanese Patent Laid-Open No. 2-143630 will be described. Referring to FIGS. 4 and 5, according to this error notification method,
Several types of asynchronous errors detected by the error detection unit 1 are classified into a major error and a minor error by the error editing unit 2. Under the control of the error information transmission control unit 5, the classified error type information and the error detection device number output from the own device number transmission unit 3 are transmitted to the error information transmission unit 4.
To the error notification line in the format shown in FIG.

FIG. 6 is a diagram for explaining a system configuration of a bus system proposed in the above-mentioned Japanese Patent Application Laid-Open No. 2-143630 to which the above-described error notification system is applied.

[0010] Referring to FIG.
The bus system proposed in Japanese Patent Publication No. 30 is a main processor (MP) 8 and a station processor (SP).
7 and a system bus (SB) 9. When an asynchronous error is detected by the station processor 7, an error is notified to the main processor 8 in the format shown in FIG. Is done.

[0011]

However, in the above-described conventional error notification system and bus system proposed in, for example, JP-A-2-143630, a transfer cycle in which an error has occurred is specified. ,
There is a problem that it is impossible to perform error processing such as retry.

The reason is as described in the above-mentioned Japanese Patent Application Laid-Open No. 2-143630.
In the error notification system and the bus system proposed in Japanese Patent Application Laid-Open Publication No. H11-270, only the device number of the bus slave device in which the error has occurred is notified, and the bus master device that manages communication related to the error is unknown. This is because it is unclear in which transfer cycle an error has occurred.

Accordingly, the present invention has been made in view of the above-mentioned problems, and the detected error corresponds to the transmission from which bus master and to which transfer cycle of the bus master. It is an object of the present invention to provide an error notification method that enables a bus master to be notified of whether or not the above is true.

[0014]

According to one aspect of the present invention, there is provided an error notification method in a bus system configured by connecting a plurality of bus masters and a plurality of bus slaves. The bus slave manages information indicating an error generated at the time of reception and / or an error generated in processing of received data, and a bus transfer cycle among the plurality of bus masters when the error occurs. Means for transmitting an error command, comprising: information for identifying a bus master that has performed, and identification information for identifying a processing number of the bus transfer cycle related to the error, wherein the plurality of bus masters include: Means for receiving the transmitted error command, wherein the plurality of bus masters and the plurality of bus threads
To a common bus line for connecting
A signal line for transmitting the error command is added to the bus master, which manages the bus transfer cycle related to the error, from the bus slave in which the error occurs without depending on the timing at which the error occurs. An error notification method is provided which is configured to be able to transmit a processing number of a bus transfer cycle in which the error has occurred and information indicating the content of the error.

With the above arrangement, according to the present invention, the bus master device stores in the processing information storage section information on the transfer cycle to which the processing number input from the processing number counter is added. The bus master device transfers the information for identifying the bus master device and the processing number of the numbered transfer cycle to the bus slave device via the processing code signal line installed on the bus. The bus slave side receives the information for identifying the bus master device and the processing number of the numbered transfer cycle, and stores it in the processing code storage unit.

If an error occurs in the bus slave device that has received the data after the data transfer is completed via the common bus line, this bus slave device is stored in the processing code storage unit. Then, the information for identifying the bus master device and the transfer cycle information are read out, and the information added with the error information is again notified to the predetermined bus master device indicated by the read out information via the processing code signal line.

As a result, a predetermined bus master device can recognize in which transfer cycle an error has occurred, and further, by reading information stored in the processing information storage section, It is possible to execute an error handling process such as a retry to perform data transmission again to the bus slave device in which the error has occurred.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

Referring to FIG. 1, an error notification device to which an error notification method according to an embodiment of the present invention is applied includes a bus master device 10, a bus slave device 20, and a bus master device 10 and a bus slave device 20. , And a common bus 31 and a processing code signal line 32 for connecting each other. In FIG. 1, the bus master device 1
Although only one 0 and one bus slave device 20 are shown for the sake of illustration, a plurality of bus master devices and a plurality of bus slave devices are connected to the common bus line 31 and the processing code signal line 32. .

More specifically, the bus master device 10 includes a bus control unit 11, a processing code control unit 12, a processing code storage unit 13, a processing number counter 14, and a processing information storage unit 15. Also, the bus slave device 2
0 is composed of a bus control unit 21, a processing code control unit 22, a processing code storage unit 23, a processing number counter 24, and a processing information storage unit 25. Further, the common bus 30 includes a common bus line 31 for transmitting commands and data in which a plurality of digital signal lines are bundled.
And a processing code line 32.

The bus master device 10 has a common bus line 3
1 manages the transmission of data. The bus slave device 20 transmits and receives data under the control of the bus master device 10. Common bus line 31
Is a data transmission bus which is a bundle of a plurality of digital signal lines. The processing code line 32 transmits the processing code. In the present embodiment, a plurality of processing code lines 32 are provided so that an error command can be transmitted in parallel. However, a single processing code line 32 is used to serially transmit an error command composed of a plurality of bits. Of course, it may be transmitted.

In the bus master device 10, a bus control unit 11 performs command and data transmission control. The processing code control unit 12 performs processing code generation, processing code transmission, and reception control. The processing code storage unit 13 temporarily stores the generated processing code. Processing number counter 14
Each time the bus master device 10 executes a transfer cycle, it assigns a process number of this transfer cycle. The processing information storage unit 15 stores information on the transfer cycle to which the processing number assigned from the processing number counter 14 is added.

In the bus slave device 20, a bus control unit 21 performs command and data reception control. The processing code control unit 22 controls reception and transmission of the processing code. The processing information storage unit 23 stores the received processing code. Although the processing number counter 24 is not normally used, when the bus slave device 20 becomes a bus master,
Similar to the processing number counter 14, a new transfer cycle number is generated each time a transfer cycle is executed. The processing information storage unit 15 stores the information of the received transfer cycle.

FIG. 2 shows a bit map (format) of the error command according to the embodiment of the present invention shown in FIG.
FIG. 6 is a diagram for explaining an example of the embodiment.

Referring to FIGS. 1 and 2, the error command is transmitted from processing code control unit 12 provided in bus master device 10 and received by processing code control unit 22 provided in bus slave device 20. The error command shown in FIG. 2 includes a 1-bit used / unused switching bit 41, a 1-bit error notification bit 42, a 3-bit error type notification bit 43, and a 5-bit number bit 44. Have been.

Processing code use / non-use switching bit 41
Indicates that the processing code line is in use in the ON state. The error notification bit 42 indicates that the bus slave device 2
At 0, a predetermined error occurs, and the bus slave device 20 is turned on when transmitting this error to the bus master device 10, and is turned off otherwise. The error type notification bit 43 is a bit for notifying the type of error which is turned on or off by the bus slave device 20. The number bit 44 is a bit for notifying the processor number which is the identification information of the bus master and the processing number of the transfer cycle.

Next, the operation of the error notification device according to one embodiment of the present invention will be described.

FIGS. 3A and 3B show timings at which the error notification device according to the embodiment of the present invention shown in FIG. 1 transmits or receives a processing code including error information via a bus. FIG. 3A is a diagram for explaining
FIG. 3B is a timing chart for explaining a bus transfer operation from a bus master to a bus slave, and FIG. 3B is a timing chart for explaining an error notification process.

Referring to FIG. 1, FIG. 2 and FIG. 3, according to the error notification device according to one embodiment of the present invention, bus master device 10 transmits commands and data controlled by bus control unit 11. When a transfer cycle is performed, the processing number counter of this transfer cycle is numbered from the processing number counter 14, and predetermined information to which the numbered processing number is added is stored in the processing information storage unit 15. You. The processing code control unit 12 writes the processing number and the processor number stored in the processing information recording unit 15 into the number bit 44 of the error command, and sets the processing code use / unused switching bit 41 to the ON state.

At the same time that the command is transmitted via the common bus line 31 in the command phase 51 by the bus control unit 11, the processing code control unit 12
The processor number 61 is transmitted via the processing code line 32. Subsequently, in the data phase 52, data is transmitted via the common bus line 31 by the bus control unit 11, and at the same time, the processing number is transmitted via the processing code line 32 by the processing code control unit 12. During these transmissions, the processing code use / unused switching bit 41 is turned on, and the processing code line 3 is transmitted via one of the processing code lines 32.
2 is transmitted (see FIG. 3A).

The bus slave device 20 receives the error command transmitted from the bus master 10 in the processing code control section 22, receives the processing code (number information) in the received error command, and receives the processing code (number). (Information) is stored in the processing code storage unit 23.

When the bus slave device 20 detects an error after the reception of the data transmitted from the bus master device 10, the bus slave device 20 stores the stored processing code in the processing code storage unit 23. Read from The processing code control unit 22 turns on the error notification bit 42, sets an error code corresponding to the type of error that has occurred in the error notification bit 43, and sets the processing number of the transfer cycle in which this error has occurred to the number bit 44. Set to.

In the bus slave device 20, when the transmission permission is obtained, the processing code use / unused switching bit 41 and the error notification bit 42 are turned on, and the predetermined error type notification bit 43 is set to the predetermined error type notification bit 43. An error command in which the processing number of the transfer cycle and the processor number indicating the bus master device 10 are written is transmitted to the bus master device 10 via the processing code line 32 as shown in the timing chart of FIG.

The bus master device 10 monitors the processing code (error command) in the error command transmitted from the bus slave device 20, recognizes that the processing code line 32 is in use, and recognizes the processor in the error command. The number confirms (recognizes) that this error command was transmitted to itself, and from the processing number in the error command, which bus transfer cycle the error occurred in the bus slave device 20 based on the processing number in the error command. Recognition, and the type of the error can be recognized from the error type notification bit 43 in the error command.

Thus, the bus master device 10 can execute processing corresponding to the type of error, such as retry of communication, by reading the processing information stored in the processing information storage unit 15.

In the present embodiment, by adding a signal line for notifying an interrupt request from the bus slave device 20 to the bus master device 10, the bus slave device 20 can be connected via the interrupt signal line. Permission to transmit an error command to the bus master device 10 may be received.

Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment, but may take various forms based on the principle of the present invention.

[0039]

As described above, according to the present invention,
After the data transfer from the bus master is completed, even if an error is detected in the bus slave, the detected error is managed by which bus master and which transfer cycle of the managed bus master device. Or the type of the detected error can be notified to the bus master, and the bus master can execute a process corresponding to the error type. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of an error notification device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a bitmap of an error command according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining an operation of the error notification device according to one embodiment of the present invention. FIG. 3A is a timing chart for explaining a bus transfer operation from a bus master to a bus slave. FIG. 6B is a timing chart for explaining an error notification process.

FIG. 4 is a diagram for explaining a schematic configuration of a conventional error notification method.

FIG. 5 is a diagram for explaining a format of error information in a conventional error notification method.

FIG. 6 is a diagram for explaining a configuration of a system using a bus to which a conventional error notification method is applied.

[Explanation of symbols]

 Reference Signs List 10 bus master device 11 bus control unit 12 processing code control unit 13 processing code storage unit 14 processing number counter 15 processing information storage unit 20 bus slave device 21 bus control unit 22 processing code control unit 23 processing code storage unit 24 processing number counter 25 processing Information storage unit 30 Common bus 31 Common bus line 32 Processing code line 41 Processing code use / non-use switching bit 42 Error notification bit 43 Error type notification bit 44 Number bit 51 Command phase 52 Data phase 61 Processor number 62 Processing number 71 Error identification Information 81 Error notification information 91 Processing code use / non-use switching information

Claims (3)

(57) [Claims] An error notification system in a bus system configured by connecting a plurality of bus masters and a plurality of bus slaves, wherein the plurality of bus slaves receive an error generated at the time of reception and / or receive the error. Information indicating the content of an error that has occurred in data processing, information for identifying a bus master that has managed a bus transfer cycle when the error has occurred among the plurality of bus masters, and information related to the error. and means for transmitting identification information for identifying the process number of the bus transfer cycle, the error commands that consist of, the plurality of bus masters, the means for receiving the transmitted error command, wherein said Connecting a plurality of bus masters to the plurality of bus slaves
To the common bus line for
A signal line for transmitting the command, without depending on the timing at which the error occurs,
The bus slave in which the error has occurred is configured to be able to transmit the processing number of the bus transfer cycle in which the error has occurred and information indicating the content of the error to the bus master which has managed the bus transfer cycle relating to the error. An error notification method characterized by: 2. The system according to claim 1, wherein the common bus line includes a plurality of
If the error occurred from the bus slave where the error occurred,
To the bus master who managed the bus transfer cycle when
To ask for permission to send the error command
2. The error notification system according to claim 1 , further comprising: 3. A plurality of bus masters and a plurality of bus slaves
Error notification for a bus system configured by connecting
A wherein said bus master and each identifies data, the bus master
Information and the processing number of the bus transfer cycle.
For transmitting the transmitted information among the plurality of bus slaves.
Receive and store, after receiving signals completion, the information that is the stored
The bus slave in which the processing error occurred has the information
The bus master that manages the transmission of the
For identifying data and the processing number of the bus transfer cycle
Information for identifying the issue and the content of the error that occurred.
And an information notification method.