JP2754712B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2754712B2
JP2754712B2 JP1103941A JP10394189A JP2754712B2 JP 2754712 B2 JP2754712 B2 JP 2754712B2 JP 1103941 A JP1103941 A JP 1103941A JP 10394189 A JP10394189 A JP 10394189A JP 2754712 B2 JP2754712 B2 JP 2754712B2
Authority
JP
Japan
Prior art keywords
bonding pad
chip
die
die bonding
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1103941A
Other languages
Japanese (ja)
Other versions
JPH06166394A (en
JPH02281739A (en
Inventor
三津男 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1103941A priority Critical patent/JP2754712B2/en
Publication of JPH02281739A publication Critical patent/JPH02281739A/en
Publication of JPH06166394A publication Critical patent/JPH06166394A/en
Application granted granted Critical
Publication of JP2754712B2 publication Critical patent/JP2754712B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors

Abstract

PURPOSE:To obtain a bonding pad enabling execution of bonding at low cost and with especially high reliability by forming a conductor thin film in a specified thickness and in a linear pattern containing three points not being located on a straight line, within an IC chip mounting region on an insulative substrate. CONSTITUTION:A die-bonding pad 11 so formed as to contain three points p1 to p3 not being located on a straight line at least and also made up of a convolution-shaped gold Au thin film 10mum thick is formed within an IC chip mounting region on an insulative substrate 1. When an IC chip 4 is mounted on a bonding agent 3 and pressed from above, a part of the bonding agent 3 is forced out into a part wherein the die-bonding pad is not formed. When the bonding agent 3 is cured, excellent continuity is obtained between the die- bonding pad 11 and the IC chip 4, while the die shear strength of the IC chip 4 in relation to the insulative substrate 1 is prevented from lowering. By this method, the die-bonding pad enabling efficient and low-cost execution of bonding of high reliability can be obtained.

Description

【発明の詳細な説明】 〔概 要〕 絶縁基板上に形成するダイボンディングパッドに関
し、 信頼度の高いボンディングを低価格に実現することを
目的とし、 半導体チップが絶縁基板上に形成されたダイボンディ
ングパッドに樹脂ボンディングされてなる半導体装置に
おいて、前記ダイボンディングパッドは少なくとも一直
線上にない三点を通る厚さ10μｍ以上の導体薄膜からな
る複数の線状パターンで構成されると共に該線状パター
ンは直接又は他の線状パターンを介して相互に接続さ
れ、前記ダイボンディングパッドが形成されていない部
分には少なくとも該ダイボンディングパッドの厚さ以上
の前記樹脂を形成して構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] A die bonding pad formed on an insulating substrate is provided with a view to realizing highly reliable bonding at a low cost. In a semiconductor device which is resin-bonded to a pad, the die bonding pad is composed of a plurality of linear patterns made of a conductive thin film having a thickness of 10 μm or more passing at least three points that are not on a straight line, and the linear pattern is directly formed. Alternatively, the resin is connected to each other via another linear pattern, and the resin having a thickness not less than the thickness of the die bonding pad is formed in a portion where the die bonding pad is not formed.

〔産業上の利用分野〕[Industrial applications]

本発明は絶縁基板上に形成する半導体装置に係り、特
に信頼度の高いボンディングを低価格に実現して生産性
の高いボンディング作業ができるダイボンディングパッ
ドに関する。The present invention relates to a semiconductor device formed on an insulating substrate, and more particularly, to a die bonding pad capable of performing highly reliable bonding at low cost and performing a bonding operation with high productivity.

一般に、アルミナ等からなる絶縁基板上に電極として
のダイボンディングパッドを形成し該ダイボンディング
パッド上にICチップを導電性接着剤等で接合して形成す
るハイブリッドICやチップ・オン・ボードIC（COB・I
C）の分野では、ICチップの裏面に形成されている電極
と上記絶縁基板上のダイボンディングパッドおよび該絶
縁基板との間の電気的，機械的接続の信頼度はこれら各
半導体装置としての信頼度を保証する上で必要不可欠な
条件である。Generally, a hybrid IC or a chip-on-board IC (COB) is formed by forming a die bonding pad as an electrode on an insulating substrate made of alumina or the like and bonding an IC chip on the die bonding pad with a conductive adhesive or the like.・ I
In the field C), the reliability of the electrical and mechanical connection between the electrode formed on the back surface of the IC chip, the die bonding pad on the insulating substrate, and the insulating substrate depends on the reliability of each of these semiconductor devices. It is an indispensable condition to guarantee the degree.

現在、ICチップのダイボンディング方法には共晶ボン
ディングや樹脂ボンディング等種々の手段が実用化され
ており、例えば低価格で量産する場合には樹脂ボンディ
ングをまた特に信頼性の高いボンディングが要求される
場合には価格的に高い共晶ボンディングを行う等目的や
用途によって使い分けている現状にあるが、低価格で特
に信頼性の高いボンディングが実現できるボンディング
方法が強く望まれている。At present, various methods such as eutectic bonding and resin bonding have been put to practical use as die bonding methods for IC chips. In such a case, it is presently used depending on the purpose and application, such as performing eutectic bonding at a high price. However, there is a strong demand for a bonding method capable of realizing particularly reliable bonding at low cost.

〔従来の技術〕[Conventional technology]

第３図は従来のダイボンディングパッドの例を示す図
であり、（ａ）はボンディング前の状態をまた（ｂ）は
ボンディング後の状態を断面で示したものである。FIG. 3 is a diagram showing an example of a conventional die bonding pad. FIG. 3 (a) shows a state before bonding and FIG. 3 (b) shows a state after bonding.

図（ａ）で、１はアルミナ（Al2O3）等からなる絶縁
基板であり、２は該絶縁基板１上の所定位置の少なくと
も被搭載ICチップをカバーするに足る領域A1と該領域A1
に繋がる信号線路A2とで形成されている厚さ10μｍの金
（Au）薄膜からるダイボンディングパッドを，また３は
該ダイボンディングパッド２上の上記領域A1部分に塗布
した例えば銀（Ag）ペーストの如きエポキシ系導電樹脂
からなる厚さ30μｍ程度の接着剤,4は該接着剤３を介し
て上記のダイボンディングパッド２にボンディング接続
するICチップをそれぞれ示しており、該ICチップ４の上
記ダイボンディングパッド２との接合面すなわち接着剤
３で接着される面全体には厚さ３μｍ程度の金蒸着膜4a
が被膜形成されている。In FIG. 1A, reference numeral 1 denotes an insulating substrate made of, for example, alumina (Al 2 O 3 ). Reference numeral 2 denotes an area A 1 sufficient to cover at least a mounted IC chip at a predetermined position on the insulating substrate 1 and the area. A 1
Signal line A 2 and the thickness of 10μm are formed of lead to gold (Au) thin film Calalou die bonding pad and 3, for example of silver was applied to the area A 1 moiety on the die bonding pad 2 (Ag ) An adhesive made of an epoxy-based conductive resin such as a paste and having a thickness of about 30 μm. Reference numeral 4 denotes an IC chip which is connected to the die bonding pad 2 via the adhesive 3. A gold vapor-deposited film 4a having a thickness of about 3 μm
Is formed as a film.

そこで上記ICチップ４を図示矢印Ｆのように接着剤３
上に載置し該ICチップ４をその上部から押圧した状態で
該接着剤３を硬化させると図（ｂ）に示す状態にするこ
とができる。Then, the IC chip 4 is attached to the adhesive 3 as shown by arrow F in the figure.
When the adhesive 3 is cured while being placed on the IC chip 4 and pressed from above, the state shown in FIG.

この場合には、該接着剤３が低温硬化する材料である
と共に低価格であることから特別な装置を使用すること
なく効率的なボンディング作業を実施することができ
る。In this case, since the adhesive 3 is a material that cures at a low temperature and is inexpensive, an efficient bonding operation can be performed without using a special device.

しかしかかる場合には、ICチップ４の破壊等の面から
該ICチップ４の押圧力には制約があり、結果的にダイボ
ンディングパッド２と上記ICチップ４との間に介在する
接着剤３の厚さｔに５〜15μｍ程度のバラツキが生じた
り，該ICチップ４がダイボンディングパッド２ひいては
絶縁基板１に対して傾いたまま硬化する等のことがあ
り、長期にわたってICとしての特性を確保することに難
点がある。However, in such a case, the pressing force of the IC chip 4 is limited due to the destruction of the IC chip 4, and as a result, the adhesive 3 interposed between the die bonding pad 2 and the IC chip 4 is consequently reduced. The thickness t may vary by about 5 to 15 μm, or the IC chip 4 may be hardened while being inclined with respect to the die bonding pad 2 and thus the insulating substrate 1, and the characteristics of the IC may be secured for a long time. There are difficulties.

更に上記の如き接着剤の場合には、本質的に金属特に
金（Au）に対する密着性が悪いためにボンディング後の
上記ICチップ４のダイボンディングパッド２すなわち絶
縁基板１に対する密着度が不安定になって剥離し易くな
り、絶縁基板上のICチップに該絶縁基板に平行に力を加
えて該ICチップを剥離させるときの力（以下ダイシェア
強度とする）が低下する。Furthermore, in the case of the above-mentioned adhesive, the adhesion to the die bonding pad 2, that is, the insulating substrate 1 of the IC chip 4 after bonding becomes unstable because the adhesion to metal, particularly gold (Au), is essentially poor. As a result, the force (hereinafter referred to as die shear strength) when the IC chip on the insulating substrate is peeled off by applying a force to the IC chip in parallel with the insulating substrate is reduced.

従って、ICチップ４のボンディングの特に高い信頼度
とボンディング後の上記ダイシェア強度の安定化が強く
要求される場合には、図（ａ）における接着剤３を使用
せず例えば400℃以上に加熱した図（ａ）のダイボンデ
ィングパッド２の所定領域A1部分にICチップ４の金蒸着
膜4a面をこすりつけて行う共晶ボンディング法を実施す
るようにしている。Therefore, when particularly high reliability of bonding of the IC chip 4 and stabilization of the above-mentioned die shear strength after bonding are strongly required, the adhesive 3 was heated to, for example, 400 ° C. or higher without using the adhesive 3 in FIG. and so as to implement the eutectic bonding method performed rubbed gold-deposited film 4a surface of the IC chip 4 to the predetermined region a 1 portion of the die bonding pad 2 of Fig. (a).

しかし、この場合には絶縁基板１を加熱する作業に加
えてICチップ４のボンディング作業が一個ずつ行われる
ことから、特別な装置を必要とすると共に多くの工数が
かかる等高価な工程になる難点がある。However, in this case, since the bonding operation of the IC chip 4 is performed one by one in addition to the operation of heating the insulating substrate 1, a special device is required, and the process becomes expensive, requiring many man-hours. There is.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

従来の如き形状のダイボンディングパッドでは、樹脂
ボンディングの場合には長期にわたってICとしての特性
を確保することができずまたICチップの絶縁基板に対す
るダイシェア強度が不安定になると言う問題があり、ま
た共晶ボンディングの場合には高価な工程になると言う
問題があった。In the case of a die bonding pad having a conventional shape, in the case of resin bonding, characteristics as an IC cannot be secured for a long time, and the die shear strength of an IC chip with respect to an insulating substrate becomes unstable. In the case of crystal bonding, there is a problem that the process is expensive.

〔課題を解決するための手段〕[Means for solving the problem]

上記問題点は、半導体チップが絶縁基板上に形成され
たダイボンディングパッドに樹脂ボンディングされてな
る半導体装置において、前記ダイボンディングパッドは
少なくとも一直線上にない三点を通る厚さ10μｍ以上の
導体薄膜からなる複数の線状パターンで構成されると共
に該線状パターンは直接又は他の線状パターンを介して
相互に接続され、前記ダイボンディングパッドが形成さ
れていない部分には少なくとも該ダイボンディングパッ
ドの厚さ以上の前記樹脂が形成されている半導体装置に
よって解決される。The above problem is that, in a semiconductor device in which a semiconductor chip is resin-bonded to a die bonding pad formed on an insulating substrate, the die bonding pad is formed of a conductive thin film having a thickness of 10 μm or more passing at least three non-linear points. And a plurality of linear patterns which are connected to each other directly or via another linear pattern, and a portion where the die bonding pad is not formed has at least a thickness of the die bonding pad. The problem is solved by a semiconductor device in which the above resin is formed.

〔作 用〕(Operation)

エポキシ系導電樹脂からなる接着剤を使用してICチッ
プを絶縁基板上の電極に接合する場合、該ICチップと絶
縁基板の間に介在する接着剤の厚さによって該ICチップ
の絶縁基板に対するダイシェア強度が変わり、特に該接
着剤の厚さが10μｍ以下の場合にはダイシェア強度が急
激に低下することが実験的に確認できた。When bonding an IC chip to an electrode on an insulating substrate using an adhesive made of an epoxy-based conductive resin, a die share of the IC chip with respect to the insulating substrate depends on the thickness of the adhesive interposed between the IC chip and the insulating substrate. It was experimentally confirmed that the strength changed, and especially when the thickness of the adhesive was 10 μm or less, the die shear strength sharply decreased.

一方、該ICチップの接合面すなわち金蒸着膜面はその
一部でもダイボンディングパッドと導通させるとICチッ
プとしての電気的特性を損なうことがない。On the other hand, even if a part of the bonding surface of the IC chip, that is, the surface of the gold vapor-deposited film is electrically connected to the die bonding pad, the electrical characteristics of the IC chip are not impaired.

本発明では、絶縁基板上のICチップを搭載する所定領
域内に厚さ10μｍのダイボンディングパッドを少なくと
も直線上にない三点を含む線状もしくは網目状に形成す
るようにしている。According to the present invention, a 10 μm-thick die bonding pad is formed in a linear or mesh shape including at least three non-linear points in a predetermined area on an insulating substrate on which an IC chip is mounted.

この場合、該絶縁基板上の上記所定領域全面に接着剤
を塗布した後にICチップを押圧すると、ダイボンディン
グパッド形成部分でICチップとの導通をとることができ
ると共にダイボンディングパッド非形成部分では上記絶
縁基板とICチップ接合面との間に最低でも10μｍの厚さ
の接着剤が介在することになる。In this case, when the IC chip is pressed after the adhesive is applied to the entire surface of the predetermined area on the insulating substrate, conduction with the IC chip can be obtained at the die bonding pad forming portion, and the above-mentioned is obtained at the die bonding pad non-forming portion. An adhesive having a thickness of at least 10 μm is interposed between the insulating substrate and the IC chip bonding surface.

従って、ICチップとしての電気的特性を損なわず且つ
ダイシェア強度も低下させることのないICチップの接合
が実現できるダイボンディングパッドを得ることができ
る。Therefore, it is possible to obtain a die bonding pad capable of realizing the bonding of the IC chip without impairing the electrical characteristics of the IC chip and without reducing the die shear strength.

［実施例］ 第１図は本発明になるダイボンディングパッドを説明
する図であり、（Ａ）は一例を示す斜視図，（Ｂ）はこ
の場合の断面図，（Ｃ）は他の実施例を示す斜視図であ
る。FIG. 1 is a view for explaining a die bonding pad according to the present invention. FIG. 1 (A) is a perspective view showing an example, FIG. 1 (B) is a sectional view in this case, and FIG. 1 (C) is another embodiment. FIG.

また第２図は導電性樹脂接着剤の厚さとダイシェア強
度との関係を説明する図である。FIG. 2 is a view for explaining the relationship between the thickness of the conductive resin adhesive and the die shear strength.

第１図（Ａ），（Ｂ）で、１の絶縁基板,4のICチップ
はいずれも第３図同様のものである。1A and 1B, the insulating substrate 1 and the IC chip 4 are the same as those in FIG.

また11は該絶縁基板１上のICチップの搭載領域中に少
なくとも一直線上にない三点p1,p2,p3を含むように該絶
縁基板１上に形成した渦巻状の厚さ10μｍの金（Au）薄
膜からなるダイボンディングパッドを示している。Reference numeral 11 denotes a spiral 10 μm-thick spiral formed on the insulating substrate 1 so as to include at least three points p 1 , p 2 , and p 3 which are not at least in a straight line in the mounting region of the IC chip on the insulating substrate 1. 1 shows a die bonding pad made of a gold (Au) thin film.

なお３は該ダイボンディングパッド11上の所定領域全
面に塗布した第３図同様のエポキシ系導電樹脂からなる
厚さ30μｍの接着剤である。Reference numeral 3 denotes a 30 μm-thick adhesive made of an epoxy-based conductive resin similar to that shown in FIG. 3 and applied to the entire surface of a predetermined region on the die bonding pad 11.

そこで上記ICチップ４を図示矢印Ｆのように接着剤３
上に載置し該ICチップ４をその上部から第３図同様の押
圧力で押圧すると、該ICチップ４の領域内にあるダイボ
ンディングパッド11の面積が第３図の場合に比して小さ
いため該ダイボンディングパッド11に対する単位面積当
たりの押圧力が増大して結果的に上記ダイボンディング
パッド上にある接着剤３の一部がはみ出してダイボンデ
ィングパッド非形成部分に押し出されることから、該ダ
イボンディングパッド11上の接着剤３の厚さが第３図の
場合よりも薄くなると共に、該ICチップ４は少なくとも
一直線上にない三点例えばp1,p2,p3を含む該ダイボンデ
ィングパッド11によって絶縁基板１に平行に且つ安定し
た状態で保持される。Then, the IC chip 4 is attached to the adhesive 3 as shown by arrow F in the figure.
When the IC chip 4 is placed on the IC chip 4 and pressed from above by the same pressing force as in FIG. 3, the area of the die bonding pad 11 in the area of the IC chip 4 is smaller than that in FIG. Therefore, the pressing force per unit area against the die bonding pad 11 increases, and as a result, a part of the adhesive 3 on the die bonding pad protrudes and is extruded to a portion where no die bonding pad is formed. The thickness of the adhesive 3 on the bonding pad 11 is smaller than in the case of FIG. 3, and the IC chip 4 has at least three non-linear points, for example, the die bonding pad including p 1 , p 2 , p 3. 11 keeps the insulating substrate 1 parallel and stable.

ここで接着剤３を硬化させると、例えばダイボンディ
ングパッド11の点p1,p3を結ぶ線ｃ〜ｃ′の断面で示す
図（Ｂ）の如く、p1,p3の近傍領域では該ダイボンディ
ングパッド11とICチップ４が第３図の場合よりも良好な
導通が得られると共に、該ダイボンディングパッド11の
非形成領域では上記接着剤３が最低でも該ダイボンディ
ングパッド11の厚さすなわち10μｍを確保して絶縁基板
１と接合されることになって該絶縁基板１に対するICチ
ップ４のダイシェア強度を低下させることがない。Here, when the adhesive 3 is cured, for example, as shown in the cross section taken along the line c-c 'connecting the points p 1 and p 3 of the die bonding pad 11, in the region near p 1 and p 3 , The conduction between the die bonding pad 11 and the IC chip 4 is better than that in the case of FIG. 3, and the thickness of the die bonding pad 11, ie, the thickness of the die bonding pad 11, 10 μm is secured to the insulating substrate 1 so that the die shear strength of the IC chip 4 with respect to the insulating substrate 1 does not decrease.

他の実施例を示す図（Ｃ）は図（Ａ）における渦巻状
パターンを持つダイボンディングパッド11のみを網目状
パターンを持つダイボンディングパッド12に置き換えた
ものである。FIG. 9C shows another embodiment in which only the die bonding pad 11 having a spiral pattern in FIG. 10A is replaced with a die bonding pad 12 having a mesh pattern.

この場合には、該ダイボンディングパッド12の孔12a
の部分で接着剤３が最低でも10μｍを確保して絶縁基板
１と接合されることから図（Ａ）の場合と同様の効果を
得ることができる。In this case, the hole 12a of the die bonding pad 12
In this part, the adhesive 3 is secured to the insulating substrate 1 with a minimum of 10 μm, so that the same effect as in the case of FIG.

アルミナ（Al2O3）等からなる第３図同様の絶縁基板
上にエポキシ系導電樹脂からなる接着剤を介して1mm角
のICチップを接合した場合の該接着剤の厚さとダイシェ
ア強度との関係を説明する第２図は、横軸Ｘに接着剤の
厚さをμｍ単位で，また縦軸Ｙにダイシェア強度をKg単
位でとったものである。In the case where a 1 mm square IC chip is bonded to an insulating substrate made of alumina (Al 2 O 3 ) or the like through an adhesive made of an epoxy-based conductive resin on an insulating substrate similar to FIG. 3, the thickness of the adhesive and the die shear strength are measured. In FIG. 2 for explaining the relationship, the abscissa X represents the thickness of the adhesive in μm units, and the ordinate Y represents the die shear strength in Kg units.

図のカーブＣおよび●で示す各点は実験結果の例を示
したもので、例えば点F1は接着剤の厚さを６μｍとした
ときのダイシェア強度が約2.4Kgなることを示し、また
点F2は接着剤の厚さが10μｍのときのダイシェア強度が
約4.8Kg,F3点は接着剤を20μｍとしたときにダイシェア
強度が約4.6Kgなることをそれぞれ表わしている。The points indicated by the curves C and ● in the figure show examples of the experimental results. For example, the point F 1 indicates that the die shear strength when the thickness of the adhesive is 6 μm is about 2.4 kg. F 2 denotes die shear strength of about 4.8Kg when the thickness of the adhesive is 10 [mu] m, F 3 points that die shear strength is about 4.6Kg when the adhesive and 20μm respectively.

従って図から明らかな如く接着剤の厚さを10μｍ以上
とすることによって、絶縁基板に対するICチップの安定
した接合を実現させることができる。Therefore, as is apparent from the figure, by setting the thickness of the adhesive to 10 μm or more, stable bonding of the IC chip to the insulating substrate can be realized.

〔発明の効果〕〔The invention's effect〕

上述の如く本発明により、信頼度の高いボンディング
を効率よくしかも低価格に実現することができる半導体
装置を容易に提供することができる。As described above, according to the present invention, it is possible to easily provide a semiconductor device capable of realizing highly reliable bonding efficiently and at low cost.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明になるダイボンディングパッドを説明す
る図、 第２図は導電性樹脂接着剤の厚さとダイシェア強度との
関係を説明する図、 第３図は従来のダイボンディングパッドの例を示す図、 である。図において、 １は絶縁基板、３は接着剤、 ４はICチップ、 11,12はダイボンディングパッド、 12aは孔、 をそれぞれ表わす。FIG. 1 is a diagram illustrating a die bonding pad according to the present invention, FIG. 2 is a diagram illustrating a relationship between the thickness of a conductive resin adhesive and die shear strength, and FIG. 3 is an example of a conventional die bonding pad. FIG. In the figure, 1 is an insulating substrate, 3 is an adhesive, 4 is an IC chip, 11 and 12 are die bonding pads, and 12a is a hole.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】半導体チップが絶縁基板上に形成されたダ
イボンディングパッドに樹脂ボンディングされてなる半
導体装置において、 前記ダイボンディングパッドは少なくとも一直線上にな
い三点を通る厚さ10μｍ以上の導体薄膜からなる複数の
線状パターンで構成されると共に該線状パターンは直接
又は他の線状パターンを介して相互に接続され、 前記ダイボンディングパッドが形成されていない部分に
は少なくとも該ダイボンディングパッドの厚さ以上の前
記樹脂が形成されていることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip is resin-bonded to a die bonding pad formed on an insulating substrate, wherein the die bonding pad is formed of a conductive thin film having a thickness of 10 μm or more passing at least three non-linear points. And the linear patterns are connected to each other directly or via another linear pattern, and the thickness of the die bonding pad is at least in a portion where the die bonding pad is not formed. A semiconductor device, wherein the above resin is formed.
JP1103941A 1989-04-24 1989-04-24 Semiconductor device Expired - Fee Related JP2754712B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1103941A JP2754712B2 (en) 1989-04-24 1989-04-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1103941A JP2754712B2 (en) 1989-04-24 1989-04-24 Semiconductor device

Publications (3)

Publication Number Publication Date
JPH02281739A JPH02281739A (en) 1990-11-19
JPH06166394A JPH06166394A (en) 1994-06-14
JP2754712B2 true JP2754712B2 (en) 1998-05-20

Family

ID=14367472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1103941A Expired - Fee Related JP2754712B2 (en) 1989-04-24 1989-04-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2754712B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61142446U (en) * 1985-02-23 1986-09-03

Also Published As

Publication number Publication date
JPH06166394A (en) 1994-06-14
JPH02281739A (en) 1990-11-19

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