JP2754640B2 - Noise removal circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise removing circuit for removing a white noise included in a composite video signal using a frame memory in a television receiver or the like.

2. Description of the Related Art In recent years, noise elimination circuits have been developed using IDTV (Improved Televisio
With the advance of the technology of n), it has been commercialized as one of the additional functions. This is because the IDTV has a frame memory, and it is easy to add a frame cyclic noise removal circuit using the frame memory. As a conventional example of a frame cyclic noise elimination circuit, “Noise Reducer” written by Takahashi, Journal of the Institute of Television Engineers of Japan, Vol. 33, No. 4, (197
9) There are P.P296 ~ 300.

Hereinafter, an example of the above-described conventional noise elimination circuit will be described with reference to the drawings. FIG. 4 shows a block diagram of a conventional noise elimination circuit. In FIG. 4, 1 is an input terminal of a composite video signal, 2 is a video output terminal after noise removal, and 3 is an A / A connected to the input terminal 1 of the composite video signal.
A D-converter, 4 is a (1-K) multiplying circuit for multiplying the video signal digitized by the A / D converter 3 by a factor of (1-K), 5 is an adder for outputting an input sum, and 6 is an input difference. , A frame memory 7 for delaying the input video signal by one frame period and outputting the same, and 8 a K output signal of the frame memory 7
K is a noise control circuit for controlling the value of K of the (1-K) multiplication circuit 4 and the K multiplication circuit 8 in accordance with the detected noise amount, and 10 is the output of the adder 5 The connected D / A converter 11 is a chroma inverter connected to the output of the frame memory 7.

The operation of the noise elimination circuit configured as described above will be described below. The image information of a TV image signal is transmitted repeatedly at the frame period, but the autocorrelation between frames is very strong, and random noise has only a low energy of the noise component when averaged at the frame period.
S / N can be improved. In the (1-K) multiplier circuit 4 and the K multiplier circuit 8, for example, In this case, the signal at the video output terminal 2 is an averaged output obtained by adding the output signal of the frame memory 7 and the signal of the composite video signal 1 by the adder 5. The degree of S / N improvement is about 5 dB. When K = O, the output of the K-times circuit 8 disappears.
The composite video signal input terminal 1 and the video signal output terminal 2 have the same signal. S / N is not improved. Depending on the amount of noise in the input signal Will be set. The noise detection circuit 9 detects the amount of noise and performs automatic control so as to increase the value of K when the noise is large. Basically, the difference signal between frames is detected by the subtractor 6, but the phase of the chroma signal of the composite video signal is inverted between frames, and a simple difference causes a chroma component to appear at the output of the subtractor 6. So the frame memory 7
Chroma inverter 11 is inserted on the output side of. The chroma inverter 11 includes a line memory and a band-pass filter for the color sub-carrier, and inverts the phase of the chroma signal. Therefore, the output of the subtractor 6 is basically a noise component and a signal component having no correlation between frames, and this is used as an input to the noise detection circuit 9.

 Next, an example of the conventional noise detection circuit 9 will be described.

FIG. 5 is a block diagram of a noise detection circuit used in a conventional noise elimination circuit. In FIG. 5, reference numeral 20 denotes a detection signal input terminal which is connected to the output of the subtractor 6 in FIG. Reference numeral 21 denotes a line memory for delaying the input video signal by one horizontal scanning period and outputs the same, 22 denotes a subtractor, 23
Is a comparator that outputs 1 when the output of the subtractor is larger than the value of the fixed value setting terminal of 24, and outputs O when the output is opposite, and 25 is a comparator
23 is a counter which counts the number of 1 pixels in the horizontal cycle, 26 is a subtractor according to the output of the comparator 23 and the counter 25
An input control circuit for taking in the output of 22; an integration circuit 27 for integrating the output data of the input control circuit; and 28 a noise detection output terminal, which is connected to the (1-K) multiplier 4 and the K multiplier 8 in FIG. An output for setting the value of K is performed.

The operation of the noise detection circuit configured as described above will be described below. As for the signal of the detection signal input terminal 20, a signal having an inter-frame correlation is removed, but a considerable signal component remains in a moving image. Line memory 21 and subtractor
22 removes the remaining signal components having a correlation between lines. The output of the subtractor 22 is a mixed output of noise and a signal component having no correlation between frames and between lines. The circuit that is configured by the comparator 23, the counter 25, and the input control circuit 26 is to further remove components other than noise. When the output 1 of the comparator 23 is continuous, that is, when the output amplitude of the subtractor 22 is large continuously, the input control circuit 26 outputs the output of the subtractor 22 to the integrating circuit.
Don't tell 27. Also, the output of the comparator 23 becomes 1 within one horizontal period.
If the number of pixels is large, it is detected by the counter 25 and the input control circuit 26 does not transmit the data of the subtracter 26 to the integration circuit 27 in the next horizontal scanning period. In this way, the integration circuit 27
The data input to is almost a noise component. When a new noise component is not captured, the integration circuit 27 holds the previous state.

As described above, a noise elimination circuit in which the noise elimination amount K is automatically controlled is configured.

Problems to be Solved by the Invention However, the above configuration has a problem that a signal component having no correlation between frames or lines is erroneously determined as noise.

The present invention has been made in view of the above circumstances, and provides a noise elimination circuit that can more accurately detect a noise component and control the amount of noise elimination.

Means for Solving the Problems In order to solve the above problems, a noise elimination circuit according to the present invention comprises: an input terminal for a composite video signal; a frame memory for storing one frame period of the input composite video signal; An adder for summing the inputs and outputs of the memory; a noise detection circuit connected to the output of the adder for monitoring a burst portion; a coefficient unit controlled by the noise detection circuit; An arithmetic unit for summing the output of the composite video signal and the output of the frame memory and outputting the sum to the frame memory, a synchronization separation circuit connected to the input terminal of the composite video signal, and a color burst position corresponding to the synchronization separation circuit. The switching circuit is controlled by the horizontal pulse output and bypasses the arithmetic unit, and the output terminal of the video signal is connected to the output of the arithmetic unit.

Effect of the Invention With the above-described configuration, the present invention detects noise in a burst period portion of a sum between frames of a composite video signal,
A noise elimination circuit capable of performing stable automatic noise elimination amount control irrespective of the content of an image can be configured.

Embodiment Hereinafter, a noise removal circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a noise removing circuit according to an embodiment of the present invention. In FIG. 1, 1 is a composite video signal input terminal,
2 is a video signal output terminal, 3 is an A / D converter, and 4 is (1-
K) Doubler, 5 is an adder, 7 is a frame memory, 8 is K
A doubler circuit, 9 is a noise detection circuit, 10 is a D / A converter, and the above is the same circuit as that of the conventional example. 12,1
3 is a two-input one-output switch, 14 is an adder, 15 is a synchronous reproduction separation circuit, 16 is a burst gate pulse output terminal, and 17 is a vertical pulse output terminal.

The operation of the noise elimination circuit configured as described above will be described below. First, when the control input is O, the switches 12 and 13 select and output the upper input (the side indicated by O in the figure). In this case, the connection of the signal system is the fourth connection of the conventional example.
It becomes the same as the figure. The signal at the burst gate pulse output terminal 16 of the sync separation / reproduction circuit 15 is a signal having a horizontal period of 1 during the color burst period, and this signal is connected to the control inputs of the switches 12 and 13. Therefore, during the color burst period, switches 12 and 13 output the lower input and switch 12 and 13
Becomes the output of the A / D converter 3, and the output of the switch 13 disappears. That is, the output of the adder 5 that takes the sum of the outputs of the switches 12 and 13 becomes equal to the signal from the composite video signal input terminal 1. The output of the adder 5 is connected to the input of the frame memory 7, and the output of the frame memory 7 has a burst portion in which the input composite video signal has been removed for only one frame period. The part is the signal from which noise has been removed. Next, the input of the noise detection circuit 9 is obtained by adding the input / output sum of the frame memory 7 by the adder 14, and the operation of this circuit will be described with reference to FIGS. FIG. 2 is a block diagram of a noise detection circuit used in the noise elimination circuit according to one embodiment of the present invention. In the figure, reference numeral 30 denotes an input terminal of a noise detection signal, which is connected to the output of the adder 14 in FIG. 31
Is a bandpass filter that passes through the band of the chrominance subcarrier of the input signal. 32 is an absolute value circuit, 33 and 34 are D latches for shifting data at clock intervals, and 35 is a maximum value circuit (1).
Then, the largest one of the outputs of the absolute value circuit 32, the D latch 33, and the D latch 34 is selected and output. 36 is a D latch,
The data input is the output of the maximum value detection circuit (1) 35.

Connected to the burst gate pulse input terminal 16 of the sync separation / reproduction circuit 15 in FIG. 1 is a delay circuit 37, which synthesizes a horizontal sync pulse rising at the center phase of the burst. The output of the delay circuit 37 is input to the trigger terminal of the D latch 36. Reference numeral 38 denotes a comparator which outputs 1 when the output of the D latch 36 is larger than the value of the fixed value setting terminal 39, and outputs O at other times. Numeral 40 is a counting circuit which counts the output pulses of the delay circuit 37 when the output of the comparator 38 is 1, and resets the counted value by the signal of the vertical synchronizing pulse input terminal 17. 41,42
Is a D latch, which shifts the count data of the counting circuit 40 in a vertical cycle. 43 is a maximum value detection circuit (2) which is a counter circuit 40 and D
The largest one of the outputs of the latches 41 and 42 is selected and output. 44 is a noise detection output terminal, a maximum value detection circuit (2)
43 outputs.

FIG. 3 is a waveform diagram of each part in FIGS. 1 and 2. FIG. 3 shows the waveform a of the signal waveform at the composite video signal input terminal 1 with the horizontal synchronizing signal and the burst signal being enlarged. The solid line shows the signal waveform of a certain frame,
The dotted line is superimposed as the signal waveform of the previous frame. The phase relationship of the burst part is inverted. Therefore,
During the burst period of the output signal of the adder 14, which takes the sum of the input and output of the frame memory 7, the burst signal component disappears and becomes a noise component. A waveform b is an example of the output of the adder 14, that is, a signal waveform of the noise detection signal input terminal 30. The case where noise is riding is described. A waveform c is an example of an output waveform of the band-pass filter 31 when the waveform b is input. A noise component of about ± 0.5 MHz around the color subcarrier frequency is extracted. A waveform d is an example of an output waveform of the absolute value circuit 32 when the waveform c is input. The waveform e is an example of the output waveform of the maximum value detection circuit (1) 35, which is an output in which the width of the peak value of the waveform d is widened. If the rising edge of the output pulse of the delay circuit 37 is the time indicated by p in the waveform e, the D latch 36 holds the data at this time for one horizontal period. If the data set in the fixed value setting terminal 39 of the comparator 38 is, for example, the value of M of the waveform e, the output of the comparator 38 is 1 during this horizontal period. In the counting circuit 40, the counting is advanced by one. In other words, the counting circuit 40 counts how many noisy horizontal periods per field. Maximum value detection circuit (2)
At 43, the value with the largest count value in the three-field period is selected and output from the noise detection output terminal 44. This makes the first
By controlling the value of K of the (1-K) multiplying circuit 4 and the K multiplying circuit 8 in the figure, a noise elimination circuit by automatic noise detection is configured.

As described above, according to this embodiment, the burst portion of the composite video signal can stop the cyclic operation and detect the noise amount during the burst period by taking a simple frame sum.
A stable detection operation can be performed irrespective of the movement of the image.

In this embodiment, it is assumed that the frame memory for three-dimensional Y / C separation of the IDTV is shared, and that the color signal system is different from the Y signal system. For example, color components remaining in the video output of this embodiment are not considered because they are removed by three-dimensional Y / C separation. Conversely, if it is desired to store color components, it is necessary to provide a chroma inverter on the return path from the frame memory.

As described above, according to the present invention, noise included in an input composite video signal can be accurately detected by using a frame memory for noise removal, and the amount of noise removal can be determined based on the detection result. By automatically controlling the coefficient unit,
A noise elimination circuit that can obtain a video signal with little noise can be configured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a noise removing circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of the noise detecting circuit, FIG.
FIG. 4 is a waveform diagram of each part of the circuits of FIGS. 1 and 2, FIG. 4 is a block diagram of a noise removing circuit in a conventional example, and FIG. 5 is a block diagram of the noise detecting circuit. 1 ... composite video signal input terminal, 2 ... video signal output terminal, 4 ... (1-K) multiplying circuit, 5 ... adder, 7 ...
Frame memory, 8 K-fold circuit, 9 Noise detection circuit, 12, 13 Switch, 14 Adder, 15 Synchronous separation / reproduction circuit, 16 Burst gate pulse output terminal, 17
... vertical sync pulse output terminal, 30 ... noise detection signal input terminal, 31 ... band-pass filter, 32 ... absolute value circuit, 35 ... maximum value detection circuit (1), 36 ... D latch, 38
… Comparator, 39… Fixed value / setting terminal, 40… Counter circuit, 43… Maximum value detection circuit (2), 44… Noise detection output terminal.

Claims (2)

(57) [Claims] 1. An input terminal for a composite video signal, a frame memory for storing one frame period of the input composite video signal, an adder for summing inputs and outputs of the frame memory, and an output of the adder. Calculating a sum of the input composite video signal and the output of the frame memory at a ratio determined by the coefficient detector, a coefficient unit controlled by the noise detection circuit, and outputting the sum to the frame memory. Device, a synchronization separation circuit connected to the input terminal of the composite video signal, a switching circuit controlled by a horizontal pulse output corresponding to the color burst position of the synchronization separation circuit to bypass the arithmetic unit, And a video signal output terminal connected to the output. 2. A band-pass filter connected to the output of the adder, an absolute value circuit connected to the output of the band-pass filter, and a first maximum value detection circuit connected to the output of the absolute value circuit. A latch that samples and holds the output of the first maximum value detection circuit in a horizontal cycle, a comparator that compares the latch output with a constant value, and counts in accordance with the comparator output, and the value is reset in a vertical cycle. A count circuit for counting horizontal pulses, and a second maximum value detection circuit connected to an output of the count circuit, wherein the coefficient device is controlled by an output of the second maximum value detection circuit. Item 2. The noise removal circuit according to Item 1.