JP2754548B2 - Shift register - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit configuration of a shift register.

[Summary of the Invention]

The present invention has an effect that the structure of the shift register is simplified by using a circuit in which the field effect transistors of complementary polarity are connected in positive feedback (thyristor connection) as the register cells of the shift register. It is.

[Conventional technology]

The circuit configuration of a conventional shift register is shown in FIG. 5 of “Television Society Journal Vol. 41, No. 11 (1987) Bipolar IC image sensor using thyristor shift register”. An application example of a shift register to an image sensor is shown. A bipolar transistor is used as a component of the shift register, and a phototransistor is used as a sensor element. In recent years, a contact type image sensor that reads optical information by bringing a document and an image sensor into close contact with each other on a one-to-one basis has been devised. However, an extremely long image sensor (for example, 297 mm for an A3 size) is required.

[Problems to be solved by the invention]

However, in the above-described prior art, since a transistor is formed using a single crystal silicon substrate as a raw material, there is a problem that a long image sensor cannot be easily formed. Therefore, an amorphous silicon thin film that can be laminated at a low temperature on an inexpensive large-area substrate (for example, Pyrex glass) is used. It is known that a photodiode or a field effect transistor can be formed by using an amorphous silicon thin film. Therefore, an object of the present invention is to provide a circuit configuration of an amorphous silicon thin film shift register formed together with a photodiode by applying the above-described technology.

[Means for solving the problem]

The present invention provides a shift register including a plurality of cells sequentially transferring a start pulse, wherein each of the cells includes at least a first field-effect transistor of a first conductivity type and a second field-effect transistor of a second conductivity type. A drain of the first field-effect transistor and a first resistor are connected in series to form a first series circuit, and a drain of the second field-effect transistor and a second resistor are connected in series To form a second series circuit, the drain output of the second field-effect transistor is input to the gate of the first field-effect transistor, and the first electric field is connected to the gate of the second field-effect transistor. The drain output of the effect transistor is input, and the start pulse or the output of the preceding cell is input to the gate, and the output corresponding to the input is output. A third field effect transistor that supplies a gate of the first field effect transistor or the second field effect transistor of a stage cell to control transfer of the start pulse to the next stage cell, The cells of the plurality of stages include a cell that connects the first series circuit and the second series circuit between a power supply terminal and an input terminal of a first phase clock, and a cell that connects the power supply terminal and a second phase clock. And a cell for connecting the first series circuit and the second series circuit to an input terminal alternately.

(Operation)

According to the above configuration of the present invention, the first and second field-effect transistors are connected so as to provide a positive feedback, and thus have a storage function and can be used as a register cell. One set of field effect transistors
Since the register cells are configured, the configuration of the shift register is facilitated.

〔Example〕

FIG. 1 is a circuit diagram of a shift register according to an embodiment of the present invention.

The highest potential of the voltage applied to the start pulse input terminal SP, the positive phase clock input terminal CL, and the negative phase clock input terminal is applied to the power supply terminal VDD.

FIG. 2 shows an operation waveform time chart of the embodiment of FIG. Waveforms SP and CL shown in FIG. 2 are applied to the start pulse input terminal SP, the positive phase clock input terminal CL, and the negative phase clock input terminal, respectively. The field effect transistors T100 to T115 are N-channel enhancement type field effect transistors. R11 to R18 are resistors. The field effect transistors T120 to T123 are P-channel enhancement type field effect transistors. At terminals 100 to 107, waveforms 100 to 107 shown in FIG. 2 are obtained.

FIG. 3 is a circuit diagram of a register cell of the shift register of the present invention. The field effect transistor T31 is a P-channel enhancement type field effect transistor, and the field effect transistor T30 is an N-channel enhancement type field effect transistor.

Next, the storage function of the register cell will be described with reference to FIG. A positive power supply is connected to the terminal 301, and a negative power supply is connected to the terminal 300. Here, the field effect transistors T30 and T31 are off. Next, when the switch S312 (or S311) is turned on, the field-effect transistor T31 (or T30) is turned on,
Accordingly, the field effect transistor T30 (or T31)
Turns on. Here, the field effect transistors T30 and T31 are turned on, and then the switch S312 (or S311) is turned on.
Is turned off, the on state of the field effect transistors T30 and T31 is maintained. This is because the switch S312 (or T311) and the field effect transistor T30 (or T31) are in parallel. Next, there are two methods for turning the on-state of the field-effect transistor into the off-state. One is terminal 301, terminal 3
This is a method of turning off the power supply connected to 00, setting it to 0, or inverting the polarity. Second, when the switch S313 (or S310) is turned on, the field-effect transistor S31 (or T30) is turned off, and accordingly, the field-effect transistor T30 (or T31) is turned off. Since the field-effect transistors T30 and T31 are now turned off, the gate voltages of the field-effect transistors T30 and T31 are maintained by the resistors R30 and R31. The off state of the effect transistors T30 and T31 is maintained. This is because the switch S313 (or S310) and the resistor R31 (or R30) are in parallel. As described above, the register cell can store two states depending on the on-state or off-state of the field-effect transistors T30 and T31. by.

FIG. 4 is a circuit diagram of a register cell of the shift register of the present invention, taking into account the influence of capacitance. Capacitors C42 and C43 are drain capacitances of the field effect transistors T30 and T31. The capacitors C40 and C41 are the sum of the gate capacitance of the field effect transistors T30 and T31 and the capacitor added for stabilizing the circuit operation.

Next, the principle of stabilizing the circuit operation of the storage function of the register cell will be described with reference to FIG. Positive power supply at terminal 301, terminal 300
To the negative power supply. The field effect transistors T30 and T31 are initially off. When a power supply is connected between the terminals 301 and 300, a charging current i flows to the capacitor C42 (or C43) via the resistor R31 (or R30). A voltage drop i × R31 (or i × R30) occurs in the resistor R31 (or R30). Since the initial value of the charges stored in the capacitors C42 and C43 is 0, the initial value of the voltage drop of the resistors R31 and R30 is
It is equal to the power supply voltage E applied between 1,300. The voltage drop V ₃₁ of the resistor R31 from above, It is represented by Voltage drop V ₃₁ is a field effect transistor T
Since the threshold voltage Vth ₃₁ is obviously larger than the threshold voltage Vth _{31, the} field effect transistor T ₃₁ turns on unlike the case described in FIG. 3 when the time constant C ₄₂ × R ₃₁ is higher than the response speed of the field effect transistor T ₃₁ . Therefore, the field effect transistor T30 is also turned on accordingly. To prevent this, set the time constant C ₄₂ × C ₃₁ to the field effect transistor T3.
What is necessary is just to make it smaller than the response speed of 1. Time constant C ₄₂ × C ₃₁
To reduce the capacitor C ₄₂ is unique as a drain capacitance of the field effect transistor T30 is to reduce the resistance R31 does not changed. However, the resistor R31 (or R3
Decreasing 0) is not preferable because current consumption increases. The current consumption I when the register cell is turned on is It is because it is expressed.

Therefore, capacitors C40 and C41 are newly provided. The operation principle will be described. Voltage drop V ₃₁ of the resistor R31 in the case of providing the capacitor C41 is Becomes Smaller voltage drop V ₃₁ of the resistor R31 than the threshold voltage Vth31 of the field-effect transistor T31 is, since the field-effect transistor T31 is not turned on, Relationship is required. Similarly, a field-effect transistor T3
Regarding the threshold voltage Vth30 of 0, Relationship is needed.

FIG. 5 is a cross-sectional view of one embodiment in which the register cell of the shift register of the present invention is formed of an amorphous silicon thin film. Insulating substrate 500 (pyrex glass, quartz, SiO ₂
, Etc.), an amorphous silicon thin film 501 (otherwise, polysilicon, etc.) is formed and etched into a desired pattern. A gate electrode 503 is formed on the gate insulating film 502 and is etched into a desired pattern. Next, an interlayer insulating film 504 is formed, and the contact holes are etched. Next, a metal wiring film 505 is formed and etched into a desired pattern. Through the above steps, a field effect transistor is formed between the terminal 506, the terminal 507, and the gate electrode 503 in FIG. 5, and at the same time, a resistor and a capacitor are formed between the terminal 507 and the terminal 508.

The circuit diagram of FIG. 1, which is an embodiment based on the principle, means, structure, and method of production clarified in the description of FIGS. 3, 4, and 5, is shown in the time chart of FIG. It is explained together with. Since the waveform always has the opposite logic to the waveform CL, only the waveform CL will be described below. When the waveform SP is set to the high level while the waveform CL is at the low level, the field-effect transistors T100 and T101 are turned on.
Is low level (hereinafter, abbreviated as waveform 100). Next, when the waveform CL changes to a high level, the field-effect transistors T100 and T101 turn off, and the field-effect transistor T120 turns on accordingly, so that the waveform 101 is maintained at a high level, and a voltage drop occurs in the resistor R12. Since the effect transistors T102 and T103 are turned on and a voltage drop occurs in the resistor R11, the low level of the waveform 100 is maintained. Accordingly, the field effect transistors T104 and T105 are turned on by the voltage drop of the resistor R12, so that a voltage drop occurs in the resistor R13, and the waveform 102 becomes a low level. Next, when the waveform CL changes to the low level (the waveform SP is set to the low level), the field-effect transistors T100 and T102 are turned off, so that the waveform 100 becomes the high level. The waveform 101 is maintained at a high level. Along with them, a field effect transistor T1
04 turns off, and accordingly, the field effect transistor T121 turns on, so that the waveform 103 is maintained at a high level and the resistance R14
Since a voltage drop occurs in the field effect transistor T106,
When T107 is turned on and a voltage drop occurs in the resistor R13, the low level of the waveform 102 is maintained. Along with that, resistor R14
Since the field effect transistors T108 and T109 are turned on by the voltage drop, a voltage effect occurs in the resistor R15, and the waveform 104 becomes low level.

The operation as a shift register is performed by repeating the above operation. The order of connection of the field-effect transistors connected in series, for example, T102 and T103 or T104 and T105 may be reversed as long as the source and the drain are connected in series. The field effect transistors T102 and T105 or T106 and T109 can be used as a single field effect transistor having a common source, drain and gate. That is, this is equivalent to short-circuiting between the source electrodes of the field-effect transistors T103 and T104 or T107 and T108. Field effect transistors T101, T102, T105, T106, T10
9, a diode can be used as an alternative to T110, T113, and T114. At this time, the polarity of the diode is connected to the cathode on the side of the clock input terminal CL.

FIG. 6 is a circuit diagram of another embodiment of the shift register of the present invention. FIG. 7 is an operation waveform time chart of the shift register shown in FIG. The power supply terminal VDD is supplied with the highest potential of the voltage applied to the start pulse input terminal, the positive-phase clock input terminal CL, and the negative-phase clock input terminal.

The waveform and CL shown in FIG. 7 are applied to the start pulse input terminal, the positive phase clock input terminal CL, and the negative phase clock input terminal, respectively. The field effect transistors T611 to T617 are N-channel enhancement type field effect transistors. R61 to R68 are resistors. The field effect transistors T600 to T607 are P-channel enhancement type field effect transistors. Waveforms 600 to 607 shown in FIG. 7 are obtained at the terminals 600 to 607. The difference from the embodiment of FIG. 1 lies in that the number of elements constituting one cell of the shift register is small, and the pulse width obtained as can be seen by comparing the waveform 102 in FIG. 2 with the waveform 603 in FIG. , FIG. 2 shows one cycle of the clock, and FIG.
This is a point corresponding to a half cycle in the figure.

FIG. 8 is a circuit diagram of an embodiment in which the shift register of the present invention is applied to an image sensor. Shift register 801
Turns on / off the field effect transistor 802 in time series, and operates the photodiode 803 in the charge accumulation mode. A recharge current to the photodiode 803 is output from the terminal 804 in time series under the control of the shift register 801.

Since the contact type image sensor described in the conventional example is very long, how to reduce the width per chip is a decisive factor in mass productivity. Therefore, one such as the present invention
This means that a shift register having a small number of elements per register cell is required. Further, the number of wirings having the same length as the chip, such as a power supply wired on the chip, also determines the width of the chip. The embodiment shown in FIG. 8 requires only one power supply, two clocks, and one signal line of the sensor, which is a total of four. Further, in the image sensor, since only one field effect transistor 802 is selected, a logic configuration of positive logic or negative logic is selected so that only the field effect transistor of the corresponding register cell is turned on. By doing so, the current consumption can be reduced significantly.

〔The invention's effect〕

As described above, according to the present invention, in each cell of each stage of the shift register, the gates of the first and second field-effect transistors complementary to each other are connected to the drain output of the other transistor. Is fed back, so that each cell forms a shift register having a storage function, the number of elements in each cell is reduced, and a shift register with a simple configuration can be provided.

Each cell includes a third field-effect transistor that controls the transfer of a start pulse to a cell having a storage function, and each cell has one of two clock input terminals having different phases to control the operation of the shift register. One of the cells is connected to one of the clock input terminals, and the other is connected to the other clock input terminal. Thus, the start pulses are sequentially transferred according to the clock. Therefore, only two wires for the clock and the power supply are required in common for each cell, so that not only the number of elements but also the number of wires can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a shift register of the present invention. FIG. 2 is an operation waveform time chart of the shift register of FIG. FIG. 3 is a circuit diagram of a register cell of the shift register of the present invention. FIG. 4 is a circuit diagram of a register cell of the shift register of the present invention. FIG. 5 is a cross-sectional view of one embodiment in which the register cell of the shift register of the present invention is formed of an amorphous silicon thin film. FIG. 6 is a circuit diagram showing another embodiment of the shift register of the present invention. FIG. 7 is an operation waveform time chart of the shift register of FIG. FIG. 8 is a circuit diagram showing an embodiment in which the shift register of the present invention is applied to an image sensor. VDD Power supply terminal SP Start pulse input terminal CL Normal phase clock input terminal Negative phase clock input terminal T100 to T115 Field effect transistors R11 to R18 Resistance T120 to T123 Field effect transistors 100 ... 107 Terminals T30, T31 Field-effect transistors 300-303 Terminals S310-S313 Switches R30, R31 Resistors C40-C43 Capacitors 500 Insulating substrate 501 Amorphous silicon thin film 502 ... Gate insulating film 503 ... Gate electrode 504 ... Interlayer insulating film 505 ... Metal wiring film 506,507,508 ... Terminal ... Start pulse input terminal T611-T617 ... Field-effect transistor R61-R68 ... Resistance T600 ~ T607 ... Field effect transistor 600 ~ 607 ... Terminal 801 ... Shift register 802 ... Field effect transistor 803 ... Photodiode 804 ... Terminal

Claims (1)

(57) [Claims] 1. A shift register comprising a plurality of cells sequentially transferring a start pulse, wherein each of the cells is at least a first field-effect transistor of a first conductivity type and a second field-effect transistor of a second conductivity type. And a drain of the first field-effect transistor and a first resistor are connected in series to form a first series circuit;
Forming a second series circuit by connecting the drain of the field-effect transistor and the second resistor in series, inputting the drain output of the second field-effect transistor to the gate of the first field-effect transistor, The drain output of the first field-effect transistor is input to the gate of the second field-effect transistor, and the start pulse or the output of the preceding cell is input to the gate, and the output corresponding to the input is output to the next. A third field effect transistor that supplies a gate of the first field effect transistor or the second field effect transistor of a stage cell to control transfer of the start pulse to the next stage cell, The cells of the plurality of stages respectively connect the first series circuit and the second series circuit between a power supply terminal and an input terminal of a first phase clock. A cell and a cell for connecting the first series circuit and the second series circuit between the power supply terminal and the input terminal of the second phase clock are provided alternately. Shift register.