JP2751918B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2751918B2 JP2751918B2 JP8123602A JP12360296A JP2751918B2 JP 2751918 B2 JP2751918 B2 JP 2751918B2 JP 8123602 A JP8123602 A JP 8123602A JP 12360296 A JP12360296 A JP 12360296A JP 2751918 B2 JP2751918 B2 JP 2751918B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- electrode
- ground electrode
- bonding wire
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01072—Hafnium [Hf]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置、特に
周波数１ＧＨｚ超、出力１Ｗ超の高周波高出力半導体素
子の内部整合回路用キャパシタに用いられる、ＭＩＭ
（Metal-Insulator-Metal）チップキャパシタの容量電
極およびボンディングワイヤの配置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIM used for a capacitor for an internal matching circuit of a semiconductor device, in particular, a high-frequency high-power semiconductor element having a frequency exceeding 1 GHz and an output exceeding 1 W.
(Metal-Insulator-Metal) This relates to the arrangement of the capacitance electrodes and bonding wires of a chip capacitor.
【０００２】[0002]
【従来の技術】従来より、ＭＩＭチップキャパシタは、
例えば周波数１ＧＨｚ超、出力１Ｗ超の高周波高出力半
導体素子の内部整合回路用キャパシタとして用いられて
いる。図３は、この種の従来のキャパシタの一例を示す
ものである。2. Description of the Related Art Conventionally, MIM chip capacitors have been
For example, it is used as a capacitor for an internal matching circuit of a high-frequency high-output semiconductor device having a frequency exceeding 1 GHz and an output exceeding 1 W. FIG. 3 shows an example of such a conventional capacitor.
【０００３】図３（ａ）、（ｂ）に示すように、基本的
に、容量電極１とグラウンド電極２で誘電体３を挟むこ
とによってキャパシタが構成されている。また、グラウ
ンド電極２の裏面には基板４が設けられ、さらに基板４
の裏面には裏面電極５が設けられている。そして、この
キャパシタは、容量電極１、グラウンド電極２それぞれ
に接続されたボンディングワイヤ６、７によって外部の
回路に接続されるようになっている。As shown in FIGS. 3A and 3B, a capacitor is basically formed by sandwiching a dielectric 3 between a capacitance electrode 1 and a ground electrode 2. A substrate 4 is provided on the back surface of the ground electrode 2.
The back surface electrode 5 is provided on the back surface. The capacitor is connected to an external circuit by bonding wires 6 and 7 connected to the capacitance electrode 1 and the ground electrode 2, respectively.
【０００４】そこで、このキャパシタを外部回路に接続
したときに、ボンディングワイヤ６を通じてキャパシタ
に流入する高周波電流は、接続点６ａからグラウンド電
極２中を流れ、接続点７ａを通り、ボンディングワイヤ
７へと導かれる。その際、接続点６ａから７ａの間は薄
い電極内部を電流が流れるため、接続点６ａ〜７ａ間に
寄生抵抗８が生じることになる。すると、この寄生抵抗
８により、キャパシタの性能の指標であるＱ値が悪化
し、１０ＧＨｚ以上での使用が困難になってしまう。例
えば、寄生抵抗値の具体例としては、容量３０ｐＦ時で
抵抗値が２．４ｍΩ程度であり、その際、周波数１０Ｇ
Ｈｚ以上でＱ値は１０を下回り、使用限界となる。Therefore, when this capacitor is connected to an external circuit, a high-frequency current flowing into the capacitor through the bonding wire 6 flows through the ground electrode 2 from the connection point 6a and passes through the connection point 7a to the bonding wire 7. Be guided. At this time, a current flows inside the thin electrode between the connection points 6a and 7a, so that a parasitic resistance 8 occurs between the connection points 6a and 7a. Then, the parasitic resistance 8 deteriorates the Q value, which is an index of the performance of the capacitor, and makes it difficult to use the capacitor at 10 GHz or more. For example, as a specific example of the parasitic resistance value, the resistance value is about 2.4 mΩ when the capacitance is 30 pF, and at that time, the frequency is 10 G
Above Hz, the Q value falls below 10, which is the usage limit.
【０００５】[0005]
【発明が解決しようとする課題】すなわち、従来のキャ
パシタの第１の問題点は、寄生抵抗の発生によりキャパ
シタ内部で損失が生じることである。その理由は、高周
波電流がキャパシタを通過する際、寄生抵抗によるジュ
ール熱としてエネルギーが失われるからである。That is, the first problem of the conventional capacitor is that a loss occurs inside the capacitor due to generation of parasitic resistance. The reason is that when a high-frequency current passes through a capacitor, energy is lost as Joule heat due to parasitic resistance.
【０００６】また、第２の問題点は、寄生抵抗の値が下
限を持っているため、損失をある値以下に抑えることが
できないことである。その理由は、平行に張ったボンデ
ィングワイヤの最近接距離はボンディング装置の性能で
決まり、ある下限値が存在する。従来のキャパシタで
は、ボンディングワイヤの位置関係は図２（ａ）に示す
ようになるため、ボンディングワイヤ６、７間の間隔を
Ｌとすると、接続点６ａ〜７ａ間距離は√２・Ｌ程度と
なる。そして、寄生抵抗値は第１近似的には接続点間距
離に比例するため、この距離の下限により寄生抵抗値の
下限が存在するからである。A second problem is that since the value of the parasitic resistance has a lower limit, the loss cannot be suppressed below a certain value. The reason is that the closest distance of the parallel bonding wires is determined by the performance of the bonding apparatus, and there is a certain lower limit. In the conventional capacitor, the positional relationship between the bonding wires is as shown in FIG. 2A. Therefore, when the distance between the bonding wires 6 and 7 is L, the distance between the connection points 6a to 7a is about √2 · L. Become. This is because the parasitic resistance value is, to a first approximation, proportional to the distance between the connection points, and the lower limit of this distance has a lower limit of the parasitic resistance value.
【０００７】本発明は、上記の課題を解決するためにな
されたものであって、接続点間距離を従来より小さくす
ることで寄生抵抗値を低減し、寄生抵抗による熱損失を
小さくし得るＭＩＭキャパシタを提供し、本キャパシタ
を内蔵する回路の効率を向上させることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. An MIM capable of reducing a parasitic resistance value by reducing a distance between connection points and a heat loss due to the parasitic resistance can be reduced. An object of the present invention is to provide a capacitor and improve the efficiency of a circuit incorporating the capacitor.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置は、誘電体を挟む容量電極と
グラウンド電極を有し、これら容量電極、グラウンド電
極の各々にボンディングワイヤが接続されたキャパシタ
であって、誘電体とその上に位置する容量電極がグラウ
ンド電極上で複数個に分割され、これら分割された容量
電極にボンディングワイヤが接続されるとともに、グラ
ウンド電極に接続されるボンディングワイヤが、グラウ
ンド電極上の隣接する容量電極間の領域で接続されてい
ることを特徴とするものである。また、本発明の他の半
導体装置は、誘電体とその上に位置する容量電極にグラ
ウンド電極を露出させる複数の窓部が設けられ、それら
窓部内のグラウンド電極にボンディングワイヤが接続さ
れるとともに、容量電極に接続されるボンディングワイ
ヤが、容量電極上の隣接する窓部間の領域で接続されて
いることを特徴とするものである。さらに、前記各ボン
ディングワイヤの容量電極またはグラウンド電極との接
続点を一直線上に配置するとよい。To achieve the above object, a semiconductor device of the present invention has a capacitor electrode and a ground electrode sandwiching a dielectric, and a bonding wire is connected to each of the capacitor electrode and the ground electrode. A connected capacitor, in which a dielectric and a capacitor electrode located thereon are divided into a plurality on a ground electrode, and a bonding wire is connected to the divided capacitor electrode and connected to the ground electrode. The bonding wire is connected in a region between adjacent capacitor electrodes on the ground electrode. Further, another semiconductor device of the present invention is provided with a plurality of windows for exposing a ground electrode to a dielectric and a capacitor electrode located thereon, and a bonding wire is connected to the ground electrode in the windows, A bonding wire connected to the capacitor electrode is connected in a region between adjacent windows on the capacitor electrode. Further, the connection point of each bonding wire with the capacitance electrode or the ground electrode may be arranged on a straight line.
【０００９】[0009]
【発明の実施の形態】以下、本発明の第１の実施の形態
を図１を参照して説明する。図１は、本実施の形態のＭ
ＩＭチップキャパシタ（半導体装置）の構成を示す図で
あって、図中符号１１は容量電極、１２はグラウンド電
極、１３は誘電体、１４は基板、１５は裏面電極、１
６、１７はボンディングワイヤ、である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows M
FIG. 2 is a diagram showing a configuration of an IM chip capacitor (semiconductor device), in which reference numeral 11 is a capacitance electrode, 12 is a ground electrode, 13 is a dielectric, 14 is a substrate, 15 is a back electrode, 1
Reference numerals 6 and 17 are bonding wires.
【００１０】図１（ａ）、（ｂ）に示すように、基本的
に、容量電極１１とグラウンド電極１２で誘電体１３を
挟むことによってキャパシタが構成されている。そし
て、誘電体１３とその上に位置する容量電極１１がグラ
ウンド電極１２上で複数個（本実施の形態では２個）に
分割されている。なお、容量電極１１およびグラウンド
電極１２の材料としてはＡｕ、Ａｌ、Ｓｉ−Ｃｕ等が用
いられ、厚さは１〜２μｍ程度である。また、誘電体１
３としてはシリコン窒化膜、シリコン酸化膜等が用いら
れ、厚さは０．４〜１．６μｍ程度である。そして、グ
ラウンド電極１２の裏面には基板１４が設けられ、さら
に基板１４の裏面には裏面電極１５が設けられている。
さらに、図１（ａ）に示す平面的な寸法としては、各容
量電極１１が２００μｍ□ 、誘電体１３が２２０μｍ
□ 、グラウンド電極１２が７００μｍ×２４０μｍ程
度である。As shown in FIGS. 1A and 1B, a capacitor is basically formed by sandwiching a dielectric 13 between a capacitance electrode 11 and a ground electrode 12. The dielectric 13 and the capacitor electrode 11 located thereon are divided into a plurality (two in this embodiment) on the ground electrode 12. Note that Au, Al, Si—Cu, or the like is used as a material of the capacitor electrode 11 and the ground electrode 12, and the thickness is about 1 to 2 μm. In addition, dielectric 1
3, a silicon nitride film, a silicon oxide film or the like is used, and the thickness is about 0.4 to 1.6 μm. The substrate 14 is provided on the back surface of the ground electrode 12, and the back surface electrode 15 is provided on the back surface of the substrate 14.
Further, the planar dimensions shown in FIG. 1A are such that each capacitance electrode 11 is 200 μm square. , Dielectric 13 is 220 μm
□ And the ground electrode 12 is about 700 μm × 240 μm.
【００１１】各容量電極１１およびグラウンド電極１２
にはボンディングワイヤ１６、１７がそれぞれ接続され
ている。そして、各容量電極１１に対するボンディング
ワイヤ１６の接続点１６ａは、各容量電極１１の中央に
位置し、グラウンド電極１２に対するボンディングワイ
ヤ１７の接続点１７ａは、隣接する容量電極１１間の領
域に位置して、各接続点１６ａ、１７ａが一直線上に配
置されている。そして、このキャパシタは、各ボンディ
ングワイヤ１６、１７によって外部の回路に接続される
ようになっている。なお、ボンディングワイヤ１６、１
７の材料としてはＡｕ、Ａｌ、Ｃｕ等が用いられ、径が
２５〜５０μｍ程度、ボンディングワイヤ１６、１７間
の寸法Ｌが１６０μｍ以上程度である。Each capacitance electrode 11 and ground electrode 12
Are connected to bonding wires 16 and 17, respectively. The connection point 16a of the bonding wire 16 to each capacitance electrode 11 is located at the center of each capacitance electrode 11, and the connection point 17a of the bonding wire 17 to the ground electrode 12 is located in the region between the adjacent capacitance electrodes 11. Thus, the connection points 16a and 17a are arranged on a straight line. The capacitor is connected to an external circuit by bonding wires 16 and 17. The bonding wires 16, 1
As a material of No. 7, Au, Al, Cu or the like is used, the diameter is about 25 to 50 μm, and the dimension L between the bonding wires 16 and 17 is about 160 μm or more.
【００１２】上記構成のキャパシタにおいて、容量電極
１１上のボンディングワイヤ１６を通って流入する高周
波電流は、キャパシタを通過し、グラウンド電極１２を
シート状に流れ、接続点１７ａからグラウンド電極１２
上のボンディングワイヤ１７へと流れる。その際、ボン
ディングワイヤ１６から流れ込んだ電流が接続点１６ａ
から１７ａへと流れるとき、電極の層抵抗により寄生抵
抗が生じる。そして、この寄生抵抗によりキャパシタ内
部で損失が生じるが、この損失が大きければ大きい程、
このキャパシタを使用する回路において大きな効率の低
下を招いてしまう。In the capacitor having the above-mentioned structure, the high-frequency current flowing through the bonding wire 16 on the capacitance electrode 11 passes through the capacitor, flows through the ground electrode 12 in a sheet shape, and flows from the connection point 17 a to the ground electrode 12.
It flows to the upper bonding wire 17. At this time, the current flowing from the bonding wire 16 is applied to the connection point 16a.
When the current flows from the gate to 17a, parasitic resistance occurs due to the layer resistance of the electrode. Then, a loss occurs inside the capacitor due to the parasitic resistance.
In a circuit using this capacitor, the efficiency is greatly reduced.
【００１３】しかしながら、本実施の形態のキャパシタ
によれば、容量電極１１を分割して隣接する容量電極１
１間の領域でボンディングワイヤ１７をグラウンド電極
１２に接続する構成とし、しかも各ボンディングワイヤ
１６ａ、１７ａの接続点が一直線上に並ぶようにしたた
め、容量電極１１への接続点１６ａとグラウンド電極１
２への接続点１７ａの間の距離をボンディング装置の性
能限界である１００μｍ程度（本実施の形態では１６０
μｍ程度）にまで近付けることができる。上述したよう
に、従来のキャパシタの場合、容量電極への接続点とグ
ラウンド電極への接続点の間の距離は、√２・Ｌ＝√２
×１６０＝２２６μｍであった。このように、本実施の
形態のキャパシタは従来のものに比べて接続点間距離を
７０％程度にまで低減できることでキャパシタ内部の寄
生抵抗を低減することができる。その結果、寄生抵抗に
よる熱損失の小さいＭＩＭチップキャパシタが実現で
き、本キャパシタを内蔵する回路の効率向上を図ること
ができる。However, according to the capacitor of the present embodiment, the capacitance electrode 11 is divided into
The bonding wire 17 is connected to the ground electrode 12 in the region between the two, and the connection points of the bonding wires 16a, 17a are arranged in a straight line.
2 is about 100 μm, which is the performance limit of the bonding apparatus (160 mm in this embodiment).
μm). As described above, in the case of the conventional capacitor, the distance between the connection point to the capacitance electrode and the connection point to the ground electrode is √2 · L = √2
× 160 = 226 μm. As described above, the capacitor of the present embodiment can reduce the parasitic resistance inside the capacitor by reducing the distance between connection points to about 70% as compared with the conventional capacitor. As a result, an MIM chip capacitor with small heat loss due to parasitic resistance can be realized, and the efficiency of a circuit incorporating the capacitor can be improved.
【００１４】以下、本発明の第２の実施の形態を図２を
参照して説明する。図２は、本実施の形態のＭＩＭチッ
プキャパシタ（半導体装置）の構成を示す図であるが、
本実施の形態が第１の実施の形態と異なる点は容量電極
および誘電体の形状のみであるため、共通の構成要素に
ついては図１と同一の符号を付し、詳細な説明は省略す
る。Hereinafter, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the MIM chip capacitor (semiconductor device) of the present embodiment.
This embodiment is different from the first embodiment only in the shape of the capacitor electrode and the dielectric. Therefore, common components are denoted by the same reference numerals as those in FIG. 1 and detailed description is omitted.
【００１５】図２（ａ）、（ｂ）に示すように、誘電体
２３とその上に位置する容量電極２１に複数（本実施の
形態では２つ）の窓部２４、２４が設けられ、これら窓
部２４、２４の部分でグラウンド電極１２が露出してい
る。また、各窓部２４内のグラウンド電極１２に対する
ボンディングワイヤ１７の接続点１７ａは、各窓部２４
の中央に位置し、容量電極２１に対するボンディングワ
イヤ１６の接続点１６ａは、容量電極２１上の隣接する
窓部２４間の領域に位置して、各接続点１６ａ、１７ａ
が一直線上に配置されている。As shown in FIGS. 2A and 2B, a plurality of (two in this embodiment) windows 24 are provided in the dielectric 23 and the capacitor electrode 21 located thereon. The ground electrode 12 is exposed at these windows 24, 24. The connection point 17a of the bonding wire 17 to the ground electrode 12 in each window 24 is
And the connection point 16a of the bonding wire 16 with respect to the capacitance electrode 21 is located in the region between the adjacent windows 24 on the capacitance electrode 21, and the connection points 16a, 17a
Are arranged on a straight line.
【００１６】本実施の形態のキャパシタの場合も、従来
のキャパシタに比べて接続点１６ａ、１７ａ間距離を低
減できることでキャパシタ内部の寄生抵抗を低減するこ
とができる。その結果、寄生抵抗による熱損失の小さい
ＭＩＭチップキャパシタが実現できる、という第１の実
施の形態のキャパシタの同様の効果を奏することができ
る。Also in the case of the capacitor of the present embodiment, the parasitic resistance inside the capacitor can be reduced by reducing the distance between the connection points 16a and 17a as compared with the conventional capacitor. As a result, the same effect as that of the capacitor of the first embodiment, in which an MIM chip capacitor with small heat loss due to parasitic resistance can be realized, can be obtained.
【００１７】なお、本発明の技術範囲は上記実施の形態
に限定されるものではなく、本発明の趣旨を逸脱しない
範囲において種々の変更を加えることが可能である。例
えば各電極および誘電体の材料、具体的な寸法等に関し
ては上記実施の形態に限らず適宜設計することができ
る。The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the materials, specific dimensions, and the like of each electrode and the dielectric are not limited to the above-described embodiments, and can be appropriately designed.
【００１８】[0018]
【発明の効果】以上、詳細に説明したように、本発明の
半導体装置によれば、ボンディングワイヤの容量電極へ
の接続点とグラウンド電極への接続点の間の距離をボン
ディング装置の性能限界に近付けることができる。すな
わち、本発明の半導体装置では従来のものに比べて接続
点間距離を低減できるため、内部の寄生抵抗を低減する
ことができる。その結果、寄生抵抗による熱損失の小さ
い半導体装置が実現でき、これを内蔵する回路の効率向
上を図ることができる。特に、各ボンディングワイヤの
接続点を一直線上に配置した場合、ボンディング装置の
性能を半導体装置の特性に最もよく生かすことができ
る。As described above in detail, according to the semiconductor device of the present invention, the distance between the connection point of the bonding wire to the capacitance electrode and the connection point to the ground electrode is limited to the performance limit of the bonding device. You can get closer. That is, in the semiconductor device of the present invention, the distance between connection points can be reduced as compared with the conventional device, so that the internal parasitic resistance can be reduced. As a result, a semiconductor device having small heat loss due to parasitic resistance can be realized, and the efficiency of a circuit incorporating the semiconductor device can be improved. In particular, when the connection points of the bonding wires are arranged on a straight line, the performance of the bonding apparatus can be best utilized in the characteristics of the semiconductor device.
【図１】本発明の第１の実施の形態であるＭＩＭチップ
キャパシタを示す、（ａ）平面図、（ｂ）（ａ）のＡ−
Ａ線に沿う縦断面図、である。FIG. 1A is a plan view showing an MIM chip capacitor according to a first embodiment of the present invention, and FIG.
It is a longitudinal cross-sectional view which follows the A line.
【図２】本発明の第２の実施の形態であるＭＩＭチップ
キャパシタを示す、（ａ）平面図、（ｂ）（ａ）のＢ−
Ｂ線に沿う縦断面図、である。FIGS. 2A and 2B show a MIM chip capacitor according to a second embodiment of the present invention, wherein FIG.
It is a longitudinal section along the B line.
【図３】従来のＭＩＭチップキャパシタの一例を示す、
（ａ）平面図、（ｂ）（ａ）のＣ−Ｃ線に沿う縦断面
図、である。FIG. 3 shows an example of a conventional MIM chip capacitor.
(A) is a plan view, and (b) is a longitudinal sectional view taken along the line CC of (a).
１，１１，２１ 容量電極 ２，１２ グラウンド電極 ３，１３，２３ 誘電体 ４，１４ 基板 ５，１５ 裏面電極 ６，７，１６，１７ ボンディングワイヤ ６ａ，１６ａ （ボンディングワイヤと容量電極との）
接続点 ７ａ，１７ａ （ボンディングワイヤとグラウンド電極
との）接続点 ８ 寄生抵抗 ２４ 窓部1,11,21 Capacitance electrode 2,12 Ground electrode 3,13,23 Dielectric 4,14 Substrate 5,15 Back electrode 6,7,16,17 Bonding wire 6a, 16a (Between bonding wire and capacitor electrode)
Connection points 7a, 17a Connection point (between bonding wire and ground electrode) 8 Parasitic resistance 24 Window
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 27/04 Ｈ０１Ｌ 27/04 Ｅ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 27/04 H01L 27/04 E
Claims (3)
を有し、これら容量電極、グラウンド電極の各々にボン
ディングワイヤが接続されたキャパシタであって、 誘電体とその上に位置する容量電極がグラウンド電極上
で複数個に分割され、これら分割された容量電極にボン
ディングワイヤが接続されるとともに、前記グラウンド
電極に接続されるボンディングワイヤが、前記グラウン
ド電極上の隣接する容量電極間の領域で接続されている
ことを特徴とする半導体装置。1. A capacitor having a capacitor electrode and a ground electrode sandwiching a dielectric, and a bonding wire connected to each of the capacitor electrode and the ground electrode, wherein the dielectric and the capacitor electrode located thereon are grounded. A plurality of electrodes are divided on the electrode, a bonding wire is connected to the divided capacitor electrode, and a bonding wire connected to the ground electrode is connected in a region between adjacent capacitor electrodes on the ground electrode. A semiconductor device characterized in that:
を有し、これら容量電極、グラウンド電極の各々にボン
ディングワイヤが接続されたキャパシタであって、 誘電体とその上に位置する容量電極にグラウンド電極を
露出させる複数の窓部が設けられ、それら窓部内のグラ
ウンド電極にボンディングワイヤが接続されるととも
に、前記容量電極に接続されるボンディングワイヤが、
前記容量電極上の隣接する窓部間の領域で接続されてい
ることを特徴とする半導体装置。2. A capacitor having a capacitor electrode and a ground electrode sandwiching a dielectric, wherein a bonding wire is connected to each of the capacitor electrode and the ground electrode. A plurality of windows for exposing the electrodes are provided, a bonding wire is connected to a ground electrode in the windows, and a bonding wire connected to the capacitance electrode is
The semiconductor device is connected in a region between adjacent windows on the capacitor electrode.
おいて、 前記各ボンディングワイヤの容量電極またはグラウンド
電極との接続点が一直線上に配置されていることを特徴
とする半導体装置。3. The semiconductor device according to claim 1, wherein a connection point of each of the bonding wires with a capacitor electrode or a ground electrode is arranged on a straight line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8123602A JP2751918B2 (en) | 1996-05-17 | 1996-05-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8123602A JP2751918B2 (en) | 1996-05-17 | 1996-05-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09306935A JPH09306935A (en) | 1997-11-28 |
| JP2751918B2 true JP2751918B2 (en) | 1998-05-18 |
Family
ID=14864681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8123602A Expired - Fee Related JP2751918B2 (en) | 1996-05-17 | 1996-05-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2751918B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015192037A (en) * | 2014-03-28 | 2015-11-02 | 株式会社東芝 | MIM capacitor |
| JP6895116B2 (en) * | 2017-04-03 | 2021-06-30 | 三菱電機株式会社 | Thin film capacitor, manufacturing method of thin film capacitor |
| WO2022260141A1 (en) * | 2021-06-11 | 2022-12-15 | 住友電工デバイス・イノベーション株式会社 | Passive element and electronic device |
-
1996
- 1996-05-17 JP JP8123602A patent/JP2751918B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09306935A (en) | 1997-11-28 |
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