JP2750890B2 - Semiconductor substrate manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor substrate for manufacturing a semiconductor integrated circuit device and the like, and generally relates to SOI (Silicon On Insula).
The present invention relates to a method for manufacturing a semiconductor substrate similar to a structure called a tor) structure. The production method of the present invention particularly relates to a method called a recrystallization method.

The semiconductor substrate of the present invention is a highly integrated LSI, a high withstand voltage device,
It can be used in many fields such as radiation-resistant devices and three-dimensional integrated circuits.

The semiconductor single crystal film to be grown is other than silicon, for example,
Even in the case of a compound semiconductor such as GaAs, the semiconductor single crystal film to be grown in the present invention is not limited to silicon, as is generally called an SOI structure.

(Prior Art) The SOI structure has been proposed so far by growing a semiconductor film on a dielectric film or a dielectric substrate.

The SOI structure forming technology includes a recrystallization method, an epitaxial growth method, an insulating layer embedding method, a bonding method, and the like. SOI
"SOI structure forming technology" for a general description of the structure forming technology
(Published by Sangyo Tosho Co., Ltd., 1987).

Among the recrystallization methods, in the laser beam recrystallization method, a polycrystalline or amorphous film formed on an underlayer such as an insulating film is melted with the energy of a laser beam, and crystal growth is performed while moving the melted portion. Is performed.

The following attempts have been made to improve the temperature distribution in a polycrystalline or amorphous film by laser beam irradiation to obtain a single crystal film.

(A) A method for improving a temperature distribution in a spot of a laser beam by using an optical system or a plurality of laser light sources.

(B) A method in which an antireflection film or a light absorbing film is provided on the surface of the sample film, and the absorption of the incident laser beam is changed to improve the temperature distribution.

(C) A method of improving the temperature distribution by changing the local heat dissipation by changing the structure of the sample.

(Problems to be Solved by the Invention) Although a single crystal can be partially obtained by these methods, a single crystal having a large area has not been obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor substrate capable of obtaining a large-area single crystal film by a simple process.

(Means for Solving the Problems) In the semiconductor substrate formed by the present invention, a semiconductor single crystal film is formed on a base, and at least a part of the region between the semiconductor single crystal film and the base is formed. A refractory metal film is provided.

The underlayer is, for example, a dielectric such as SiO ₂ or Si ₃ N ₄ .

 The semiconductor single crystal film is made of Si, GaAs, GaP or the like.

The refractory metal film includes, in addition to films such as W, Ti, Mo, and Pt, refractory metal alloy films such as silicide thereof.

In the method of the present invention, an amorphous or polycrystalline semiconductor film is deposited on a base via a high melting point metal film, a cooling medium of a liquid organic compound is provided on the semiconductor film, and the semiconductor film is irradiated with energy. Then, the crystal is grown while moving the molten portion.

Irradiation energy is given in the form of a laser beam or other light beam, an electron beam, a heat ray, or the like.

Liquid organic compounds that do not evaporate to relatively high temperatures are preferred as cooling media. As such an organic compound, for example, polyethylene glycol, polyethylene ether, polyethylene ester, polypropylene oxide and the like which are generally known as a surfactant can be used.

(Function) The refractory metal film can be used as a conductor in a semiconductor device.

When energy is applied to the amorphous or polycrystalline film formed on the lower ground, the movement of the cooling medium facilitates the growth of a large single crystal. At that time, the energy is reflected by the high melting point metal film, and the influence of heat on the base is less likely.

(Embodiment) FIG. 1 shows an example of a semiconductor substrate manufactured by the present invention.

A silicon oxide film (SiO ₂ ) 4 having a thickness of about 1 μm is formed on a single crystal silicon substrate 2, and a tungsten film 5 having a thickness of about 800 ° is formed thereon as a refractory metal film. The tungsten film 5 is patterned. A single-crystal silicon film 14 having a thickness of about 5000 mm is formed thereon.

FIG. 2 shows a semiconductor substrate in which a tungsten film 5 is formed on the entire surface of a silicon oxide film 4 and a single crystal silicon film 14 is formed thereon.

A single crystal GaAs film can be formed instead of the single crystal silicon film 14 in FIG. 1 or FIG.

FIG. 3 shows a method of manufacturing the semiconductor substrate of FIG. 1 and a step of performing element isolation using the substrate.

(A) 2 is a single crystal silicon substrate having a plane orientation of (100), the surface of which is oxidized to a silicon oxide film 4 of about 1 μm.
To form A tungsten film 5 having a thickness of about 800 mm is deposited on the silicon oxide film 4 as a refractory metal film by a sputtering method or the like, and is patterned by photolithography and etching. A polycrystalline silicon film 6 is deposited on the polycrystalline silicon film 6 to a thickness of about 5000 LP by LPCVD, and a silicon nitride film (Si ₃ N ₄ ) 8 is formed on the polycrystalline silicon film 6 to a thickness of about 800 に よ り by the CVD method. . A polyethylene glycol 10 is formed as a cooling medium on the silicon nitride film 8, and an optical glass plate 12 is placed thereon so that the polyethylene glycol 10 becomes a layer having a uniform thickness. Degree.

A laser beam 13 of an argon ion laser is condensed by a lens from the optical glass plate 12 and irradiates the polycrystalline silicon film 6, and the silicon substrate 2 or the laser beam 13 is moved to form a molten portion 7 of the polycrystalline silicon film 6. Then, the single crystal 14 is grown.

The laser beam irradiation condition is such that when a continuous wave argon ion laser is used, the light output is about several W to 20 W, and for example, a laser beam of 3 W is used. The laser beam diameter on the polycrystalline silicon film 6 is about 20 to 100 μm, and the scanning speed is about several cm to 25 cm / sec. Thereby, the polycrystalline silicon film 6 grows into a single crystal silicon film.

Thereafter, the glass plate 12, the polyethylene glycol 10, and the silicon nitride film 8 are removed. Thus, a semiconductor substrate is formed.

The steps of forming an element isolation region will be described with reference to FIGS.

(B) The surface of the grown single crystal silicon film 14 is thermally oxidized to form a silicon oxide film 16 having a thickness of 250 to 500 mm, and a silicon nitride film (Si ₃ to form a N ₄₎ 18.

Next, the silicon nitride film 18 is patterned by photolithography and etching, which are usual means for patterning the silicon nitride film. The silicon oxide film 16 exposed from the opening of the pattern of the silicon nitride film 18 is over-etched by a wet etching method, and the silicon oxide film 16 is etched down to the lower side of the silicon nitride film 18.

Next, the single crystal silicon film 14 is etched using an alkaline anisotropic etching solution. This etching is (11
1) Travel diagonally along the surface. In this anisotropic etching, the (111) plane is located at the tip of the eaves of the silicon nitride film 18.
Repeat until a and b are exceeded.

(C) Next, using the silicon nitride film 18 as a mask, the single crystal silicon film 14 is etched until the silicon oxide film 4 is reached. As a result, a groove 20 is formed in the single crystal silicon film 14.

(D) Selective oxidation is performed using the silicon nitride film 18 as a mask to form a thick silicon oxide film 22 having a thickness of about 0.3 to 1 μm.
Is formed in the groove 20, and the surface of the groove 20 is covered with a silicon oxide film.

After that, the silicon nitride film 18 used as the mask is removed.

(E) A silicon nitride film 24 having a thickness of about 1000 ° is again formed on the entire surface. The silicon nitride film 24 is for preventing further oxidation from proceeding toward the inside of the single crystal silicon film 14 in a later oxidation step, and for preventing crystal defects from occurring in the single crystal silicon film 14. is there. However, when the demand for the single crystal silicon film 14 is not severe, the formation of the silicon nitride film 24 can be omitted.

The silicon nitride film 24 is etched so that the tungsten film 5 is exposed in the groove 20, and thereafter, the polycrystalline silicon 26 is embedded in the groove 20. Phosphorus or the like is diffused into the polycrystalline silicon 26 to reduce the resistance.

According to the substrate thus separated from the element, the single crystal silicon film 14 in the region where the tungsten film 5 is spread
And the potential of the groove 20 can be made equal. For example, when the single crystal silicon film 14 is a well for forming a MOS transistor, the potential of this well can be taken out from the groove 20, and for example, when a bipolar transistor is manufactured on the single crystal silicon film 14, The potential can be extracted from the groove 20.

When the potential is not taken out from the groove 20, polycrystalline silicon 26 is buried in the groove 20 and oxidized to form a silicon oxide film on the exposed portion. Thereby, the single crystal silicon film 14 can form a silicon island completely separated by the isolation between the lower silicon oxide film 4 and the groove 20.

In order to fill the trench 20 for isolation, a dielectric or polymer material such as SiO ₂ or Si ₃ N ₄ can be used other than the polycrystalline silicon 26.

Normal MO is applied to the silicon island thus formed.
When elements are formed by the S process or the bipolar process, a high-speed device with small junction capacitance can be realized.

In FIG. 3 (A), in order to cover the polyethylene glycol 10 more uniformly, a silicon nitride film 8 is formed.
A silicon oxide film of about 1000 ° may be formed thereon by, for example, the LPCVD method, and the polyethylene glycol 10 may be coated thereon. This is because the polyethylene glycol 10 has better wettability on a silicon oxide film than on a silicon nitride film.

The optical glass plate 12 is for making the thickness of the polyethylene glycol 10 uniform, and can be omitted.

As shown in FIG. 2, a semiconductor substrate having a high melting point metal film formed on the entire surface can be manufactured in the same manner as in FIG. 3 (A).

Next, a method for forming a single crystal GaAs film on a dielectric film will be described.

As in FIG. 3A, a silicon oxide film 4 is formed on the single crystal silicon substrate 2 to a thickness of about 1 μm.
Next, a GaAs film is formed on the silicon oxide film 4 by a vapor deposition method.
It is formed to a thickness of 00 °. Thereafter, a silicon nitride film 8 is formed on the GaAs film, a polyethylene glycol layer 10 is formed thereon as a cooling medium, and an optical glass plate 12 is provided thereon. Then, the GaAs film is melted and irradiated with an argon ion laser beam 13 to perform crystal growth.

According to this example, the insulating film 4 is formed on the single crystal silicon substrate 2.
A three-layer structure in which a single-crystal GaAs film is formed via the substrate can be obtained. For example, by forming an element by a normal MOS process or a bipolar process on the lowermost single crystal silicon substrate, and forming an optical device such as a light emitting diode or a laser diode on the uppermost single crystal GaAs film,
An electronic device in which an I / O device and a peripheral circuit are integrated can be realized.

At present, it is difficult to increase the diameter of a GaAs single crystal. However, according to this method, a single crystal is formed on a large-diameter single crystal silicon substrate.
GaAs can be formed.

In the embodiment, a laser beam recrystallization method is shown as a manufacturing method, but the present invention can be similarly applied when other energy such as an electron beam is used.

In a semiconductor integrated circuit device, for example, a MOS transistor is formed on a semiconductor substrate such as a silicon single crystal substrate. Although it is necessary to take out the potential of the well, the place where the well potential is taken out is usually provided on the surface of the substrate on which the semiconductor element is formed.

FIG. 4 shows a conventional MOS transistor formed by an LSI process as an example.

Reference numeral 70 denotes an N-type silicon single crystal substrate, on which a P well 71 is formed. A source 72 and a drain 73 are formed in the P well 71 by an N ⁺ diffusion region, and a gate electrode 75 is formed on the channel region via a gate oxide film 74.

On the other hand, a P ⁺ diffusion region 76 of the same conductivity type as the well 71 is formed to extract the potential of the well 71. Reference numeral 77 denotes an element isolation field oxide film, and an element isolation field oxide film 77 is provided between the MO transistor and the well potential extracting diffusion region. 78 is an interlayer insulating film, 79 is Al
And Al-Si alloy wiring.

4, the semiconductor device has a conductivity type opposite to that of FIG. 4, that is, the substrate 70 is P-type, the well 71 is N-type, and the source 72 and the drain 73 are P-type.
^{Also in the case where the +} type and well potential extracting diffusion region 76 is the N ⁺ type, a field oxide film 77 for element isolation is provided in the same manner.

In such a semiconductor device, an isolation region is provided between the diffusion region 76 for extracting a well potential and the semiconductor element.
Since the region 77 is required, the well potential extracting region 77 is required, and the area occupied by the well potential extracting portion is increased, which is an obstacle to increasing the degree of integration of the semiconductor device.

In addition, there is an inconvenience in the circuit design that the design must be made in consideration of the diffusion region 76 for extracting the well potential.

Further, the N well is connected to Vcc (5 V), the P well or the P substrate is connected to Vss (0 V), and in the case of a semiconductor integrated circuit in which a logic circuit and a memory circuit are mixed, either the logic circuit or the memory circuit is used. Some sacrifice of characteristics.

Therefore, an example of improving the degree of integration and simplifying the circuit configuration to facilitate the design and realizing a semiconductor device having a high degree of freedom with respect to the potential of a well or a substrate using the semiconductor substrate manufactured according to the present invention will be described. This is shown in FIG. 5 to FIG.

In FIG. 5 to FIG. 7, the single crystal silicon film formed on the insulating base via the high melting point metal film or the high melting point metal alloy film is separated by the groove having the dielectric film on the side wall to form a well. A semiconductor element is formed in the well, and the refractory metal film or refractory metal alloy film of the well extends into the separation groove, and a conductor is embedded in the groove to take out the potential of the well. The insulating underlayer is, for example, a silicon single crystal substrate on which a dielectric film such as SiO ₂ or Si ₃ N ₄ is formed, or a dielectric plate. Refractory metals are W, Ti, Mo, Pt, etc.
Refractory metal alloys are replaced, for example, by their silicides. The conductor embedded in the groove is a low-resistance metal capable of making ohmic contact with a high-melting-point metal or an alloy thereof, or single-crystal or amorphous silicon whose resistance has been reduced by adding impurities.

The high-melting metal film or the high-melting metal film present under the well in which the semiconductor element is formed functions as a low-resistance buried layer, and the buried layer extends to the inside of the trench of the element isolation region and forms a conductor in the trench. Since the connection is established, the potential of the well can be taken out from the groove in the element isolation region. There is no diffusion region for taking out a well potential, which was conventionally required.

In FIG. 5, reference numeral 2 denotes a single crystal silicon substrate, on the surface of which a silicon oxide film 4 having a thickness of 5000 to 6000 ° is formed. On the silicon oxide film 4, a tungsten film 5 having a thickness of 800 to 1000 ° is formed and patterned. On the silicon oxide film 4 with the tungsten film 5 interposed, a single crystal silicon film 14 is formed to a thickness of 5000 to 8000 °. The single crystal silicon film 14 is separated by an element isolation groove, and the side surface of the groove is covered with a dielectric film 30 such as a silicon oxide film or a silicon nitride film, and a conductor 26 is embedded in the groove. As the conductor 26, for example, polycrystalline silicon to which an impurity is introduced to reduce the resistance can be used. The tungsten film 5 extends into the element isolation groove and is in contact with the conductor 26.

A source 34 and a drain 36 are formed in the single crystal silicon film 14 separated by the grooves by impurity diffusion. When the single crystal silicon film 14 is P type, the source 34 and the drain 36 are N ⁺ type, and when the single crystal silicon film 14 is N type, the source 34 and the drain 36 are P ⁺ type. A gate electrode 40 is formed on the channel region via a gate oxide film 38. 42 is an interlayer insulating film, 44 is a metal wiring such as Al or Al-Si, and the metal wiring 44 is also connected to the conductor 26 in the groove.

Next, a method of manufacturing the semiconductor device of FIG. 5 will be described.

The step of forming the single crystal silicon film 14 is the same as the method shown in FIG.

Single-crystal silicon film in the area where the trench to be the isolation area is formed
14 is etched by RIE to form a groove. A dielectric film 30 such as a silicon oxide film or a silicon nitride film is formed on the inner wall of the groove and on the single crystal silicon film. The dielectric film in the region where the element is to be formed is thereafter removed. Even if an oxide film is formed on the tungsten film 5, the oxide film is removed by etching such as RIE to remove the dielectric film in the element formation region.

After the isolation groove is filled with polycrystalline silicon containing impurities or with polycrystalline silicon containing no impurities, impurities are deposited and diffused or implanted. Thus, the tungsten film 5 and the low-resistance polycrystalline silicon 26 are connected in the groove.

After that, a semiconductor element is formed on the single crystal silicon film 14 according to a normal LSI process. Then, by forming a contact from above the polycrystalline silicon 26 buried in the isolation trench, the potential of the single crystal silicon 14 can be taken out.

In FIG. 6, a tungsten film 5-1 is formed as a first refractory metal film on the silicon oxide film 4-1.
A silicon oxide film 4-2 is formed thereon and patterned. On the silicon oxide film 4-2, a tungsten film 5-2 is further formed and patterned as a second refractory metal film.

14-1 and 14-2 are single crystal silicon films, which are separated from each other by element isolation grooves. Impurities are introduced into the single-crystal silicon film regions 14-1 and 14-2, so that the region 14-1 is N-type and the region 14-2 is P-type.

A source 34p and a drain 36p are formed in the single crystal silicon film region 14-1 by the P ⁺ type diffusion region, and a source 34n and a drain 36n are formed in the single crystal silicon film region 14-2 by the N ⁺ type diffusion region. I have. A gate electrode 40 is formed on each channel region, a P-channel MOS transistor is formed in the region 14-1, and an N-channel MOS transistor is formed in the region 14-2.

The single-crystal silicon film regions 14-1 and 14-2 are connected to each other by a tungsten film 5-1 and are connected to, for example, a + 5V power supply terminal via an impurity-doped polycrystalline silicon 26-1 in an isolation trench. . On the other hand, the single crystal silicon film region 14
The potential of -2 is connected to the ground terminal via the impurity-doped polycrystalline silicon 26-2 in the isolation trench through the tungsten film 5-2.

As shown in FIG. 6, the single-crystal silicon film regions 14-1, 14-2
The refractory metal films or refractory metal alloy films 5-1 and 5-2 provided underneath are formed into a two-layer structure with a dielectric film 4-2 interposed therebetween, so that the wells 14 of the same potential are scattered. -1,14-2
Can be collectively taken out to the outside.

In FIG. 7, for example, a tungsten film is deposited as a high melting point metal film on the silicon oxide film 4 on the single crystal silicon substrate 2 and the pattern is formed as indicated by symbols 5-3, 5-4, and 5-5, respectively. Has been Tungsten film 5-3,
The monocrystalline silicon film formed on 5-4,5-5 is LOCOS
The field areas 14-3, 14-4,
14-5. 46 is a field oxide film for LOCOS isolation. 26-3, 26-4, and 26-5 are polycrystalline silicon buried in trenches for isolation and doped with impurities to reduce the resistance. Tungsten films 5-3 are respectively formed in the respective isolation trenches. , 5-4,5-5.

Each of the separated field areas 14-3, 14-4, 14-5 has
A desired element is formed by the MOS process. 34
Reference numerals -3,34-4,34-5 denote a source, 36-3,36-4,36-5 a drain, 40 a gate electrode, 42 an interlayer insulating film, and 44 a metal wiring.

The elements formed in the respective field regions 14-3, 14-4, and 14-5 are formed from the respective tungsten films 5-3, 5-4, and 5-5 from the respective polycrystalline silicons 26-3, 26-4, and 26. The potential can be extracted through -5. Therefore, for example, when three types of transistors are formed, different substrate potentials can be set for each transistor. For example, if three types of transistors, that is, a memory transistor, an N-channel MOS transistor, and a P-channel MOS transistor, are configured, an optimal substrate potential can be set for each transistor, and optimization can be individually performed. . In this way, by making the substrate potential of each element independent, a flexible circuit configuration can be adopted.

In FIG. 7, the LOCOS isolation and the trench isolation are used together in the isolation region. However, only the trench isolation may be used as shown in FIG. 5 or FIG.

In the above embodiments, a single crystal silicon substrate is used as the substrate 2. However, a dielectric substrate such as a ceramic may be used, and a dielectric film such as a silicon oxide film may be deposited on the surface of the substrate by a CVD method or the like.

In FIGS. 5 to 7, the element isolation region can be used to extract the potential of the well, so that it is not necessary to provide a diffusion region for extracting the potential of the well as in the prior art, and the density can be increased. become.

Further, the circuit design is simplified because the circuit pattern is simplified.

FIG. 8 shows a conventional semiconductor device called an OST structure (see Japanese Patent Publication No. 62-40858).

80 is a silicon substrate, 81 is a field oxide film, 82 is N ⁺
A type buried layer 83 is an N ⁻ type epitaxial layer. 84 is a base, 85 is an emitter, and 86 is a collector contact.

In order to reduce the junction capacitance and the parasitic capacitance in the isolation part separating the transistors, a groove penetrating the buried layer 82 is formed in the isolation part, and the surface of the groove is covered with the silicon oxide film 87. At the same time, the trench is filled with polycrystalline silicon 88. 89 is P
⁺ Type channel cut.

In the transistor shown in FIG. 8, since an N ⁺ type diffusion region is used as the buried layer 82, a junction capacitance exists between the transistor and the silicon substrate 80.

Therefore, by making the buried layer a high melting point metal film (including high melting point metal alloy such as high melting point metal silicide),
FIGS. 9 and 10 show an example in which a semiconductor substrate manufactured according to the present invention is applied to a semiconductor device having a higher switching speed with a smaller junction capacitance as a parasitic capacitance. However, illustration of an interlayer insulating film, a metal wiring, a passivation film, and the like is omitted in both figures.

In FIG. 9, a silicon oxide film 4 having a thickness of about 1 .mu.m is formed on a silicon substrate 2, and a tungsten film 5, which is a refractory metal film, is formed on the silicon oxide film 4 to a thickness of 800 to 1000 mm. A single-crystal silicon film 14 having a thickness of about 5000 ° is formed from above the tungsten film 5, and the base 48 and the emitter 5 are formed on the single-crystal silicon film 14.
0 and the single crystal silicon film 14 as a collector.
A transistor having a contact 52 is formed.

A groove reaching the silicon oxide film 4 is formed in the isolation portion, and the surface of the groove is covered with the silicon oxide film 30, and polycrystalline silicon 26 not doped with impurities is formed in the groove.
a is filled.

Collector contact 52 is in contact with tungsten film 5, which is a buried layer.

FIG. 10 differs from FIG. 9 in that the collector contact 52
Does not exist, and the tungsten film 5 as the buried layer is exposed in the trench of the isolation portion. The polycrystalline silicon 26 filling the trenches of the isolation portion is polycrystalline silicon doped with impurities to reduce the resistance. A contact hole is formed on the polycrystalline silicon. By contacting the tungsten film 5 with the polycrystalline silicon 26, a collector contact can be made at the isolation portion.

In the semiconductor device of FIG. 10, the area required for one transistor is reduced, and the degree of integration can be increased.

A method of manufacturing the semiconductor device shown in FIG. 9 will be described with reference to FIG.

(A) The method shown in FIG. 3A is used to form a single crystal silicon film over an insulator.

(B) Next, the isolation portion formation planned area 54,
The collector contact forming region 56 and the base forming region 58 are each masked with a silicon nitride film,
A field oxide film 46 having a thickness of 1 to 1.5 μm is formed by a selective oxidation method.

(C) Next, a silicon nitride film 60 is formed on the entire surface by CVD.
Formed to a thickness of 0.1 to 0.2 μm, and a PSG film 62
The thickness is about m.

The silicon nitride film 60 and the PSG film 62 are removed by photolithography and etching to open a window in the region 54 where the isolation portion is to be formed.

(D) Next, the isolation portion forming region 54 is etched through the window by RIE using (CCl ₄ + BCl ₃ ) gas to form a groove 63 reaching the silicon oxide film 4.

 After that, the PSG film 62 is removed by wet etching.

(E) Next, the surface of the groove 63 is selectively oxidized to form the silicon oxide film 30, and the groove 63 is filled by growing polycrystalline silicon 26 a which is not doped with impurities. As a material for filling the groove, an insulator or a polymer material such as SiO ₂ or Si ₃ N ₄ can be used in addition to polycrystalline silicon.

The surface of the polycrystalline silicon 26a is selectively oxidized using the silicon nitride film 60 to cover the surface of the polycrystalline silicon 26a. The silicon oxide film formed at this time is connected to the field oxide film 46. After that, the silicon nitride film 60 is removed.

After that, it will be based on the conventional bipolar process,
Form emitter and collector contacts.

When the semiconductor device shown in FIG. 10 is manufactured, the collector contact forming region 56 is not provided, but the tungsten film 5 is patterned so as to extend to the isolation portion forming region 54 instead. Phosphorus or the like is diffused in order to lower the resistance of the polycrystalline silicon 26 filling the trench of the isolation portion. Then, a contact hole is formed in the silicon oxide film on the polycrystalline silicon 26 in order to make the polycrystalline silicon 26 contact the collector.

In the semiconductor device having the OST structure shown in FIG. 9 or FIG. 10, the isolation part has an insulated groove structure,
Further, since the high melting point metal film is used as the buried layer, the junction capacitance and the parasitic capacitance are further reduced, and the switching speed of the semiconductor device can be increased.

(Effect of the Invention) According to the method of the present invention, a large-area single crystal film can be formed by a recrystallization method by the action of a liquid organic compound and a cooling medium. Thereby, a three-dimensional integrated circuit device or the like can be realized.

[Brief description of the drawings]

1 and 2 are end views showing a semiconductor substrate formed according to the present invention, respectively. FIGS. 3 (A) to 3 (E) are process end views showing a manufacturing method of one embodiment, and FIG. Is an end view showing a conventional semiconductor device, FIG. 5 is an end view showing an example of a semiconductor device formed according to the present invention, and FIGS. 6 and 7 are other examples of a semiconductor device formed according to the present invention, respectively. FIG. 8 is an end view showing a conventional semiconductor device having an OST structure, and FIGS. 9 and 10 are end views showing still another example of a semiconductor device formed according to the present invention.
11A to 11E are process end views showing the method for manufacturing the semiconductor device in FIG. 2 Single crystal silicon substrate, 4,4-1,4-2 Silicon oxide film, 5,5-1,5-2 Tungsten film, 6 Polycrystalline silicon film, 8 Silicon nitride Film, 10: polyethylene glycol layer, 14, 14-1 to 14-5: single crystal silicon film.

Continued on the front page (31) Priority claim number Japanese Patent Application No. 63-199146 (32) Priority date August 9, 1988 (33) Priority claim country Japan (JP) (56) References JP 58-93222 (JP, A) JP-A-62-39068 (JP, A) JP-A-61-44785 (JP, A) JP-A-1-227423 (JP, A)

Claims (1)

(57) [Claims] An amorphous or polycrystalline semiconductor film is deposited on a base through a high melting point metal film, a cooling medium of a liquid organic compound is provided on the semiconductor film, and the semiconductor film is irradiated with energy. And producing a semiconductor substrate by crystallizing while moving the molten portion.