JP2746724B2 - Display image signal processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing device for converting an image signal transmitted by high compression encoding into a display image.

(Prior Art) In a conventional display image signal processing device, a method of adding a signal conversion circuit to a received and decoded image signal according to a conversion item is generally used.

FIG. 3 is a block diagram of an example of a conventional display image processing circuit. In the figure, 1 is an image signal input terminal, 2 is an encoding device, 3
Is a transmission path, 4 is a decoding device, 5 is a decoded image signal terminal, 6
Denotes a post filter, 7 denotes an image holding circuit, 8 denotes a two-screen combining circuit, and 9 denotes a display output terminal. Here, the display image processing circuit 10 is composed of 6 to 8.

The image signal input from the image signal input terminal 1 is subjected to high compression encoding by the encoding device 2 and sent out to the transmission path 3. The signal received from the transmission path is decoded by the decoding device 4 and output to the decoded image signal terminal 5 as a decoded image signal. Although the output of the decoded image signal terminal 5 can be used as a display image, a high-quality and functional image can be displayed by performing the following signal processing.

That is, the post filter 6 removes coding noise generated in the course of the coding process, and by using this post filter, a higher quality image can be displayed.
The circuit 7 for holding the received image stores the received image at a specified point in time and displays it again when necessary. The two-screen combining circuit 8 combines the received image with another image to form a display image. As the other image, the above-mentioned held image, the self-image transmitted from the self-device, or the like can be used.

(Problems to be Solved by the Invention) In the conventional display image signal processing device described above, since a dedicated signal processing unit is prepared for processing the display image, a large signal increases as the processing becomes complicated. It was necessary to prepare a processing unit. Also, when the processes are cascaded, the processing time is added, which causes a delay in the display image.

(Object of the Invention) An object of the present invention is to realize a display image signal processing apparatus for converting an image signal transmitted by high-compression encoding into a highly functional display image using a simple circuit.

(Means for Solving the Problems) In order to solve the above problems and achieve the object, the present invention provides a signal processing apparatus for converting an image signal transmitted by high compression encoding into a display image, wherein noise is removed from an input image. The post-filter is configured to selectively receive data from a decoding device or a frame memory that stores one frame of image data. The coordinate conversion circuit that performs coordinate conversion of the input image includes the decoding device, A pattern conversion circuit configured to selectively input data from a frame memory or an external memory is configured to receive image data of the decoding device, a character code from an external memory, and the like. The display image output and the frame memory input data are converted by the post filter or the coordinate conversion circuit or the pattern conversion circuit. The frame memory is controlled by a writing control signal, the input selection signal of the post filter, the input selection signal of the coordinate conversion circuit, and the display image output. The most main feature is that the selection signal of the frame memory input and the write control signal of the frame memory are provided as a control code from the display image control circuit for each block area of the display image. .

(Operation) According to the present invention, modules such as a frame memory, a post filter, and a coordinate conversion circuit are arranged in parallel by the above means.
The data flow between the modules can be changed according to a control signal designating the display image configuration while sharing the frame memory.

Therefore, the image signal transmitted with the high compression code can be converted into a highly functional display image with a simple circuit configuration.

(Embodiment) FIG. 1 shows a block diagram of an embodiment of the apparatus of the present invention. The same block functions as those in FIG.

In the illustrated display image processing circuit 10 ', 11 is a post filter, 12 is a coordinate conversion circuit, 13 is a pattern conversion circuit, 14 is a frame memory, 15 and 16 are input selection circuits, 17 is an output selection circuit, and 18 is an external memory. And 19 are display image control circuits.

The decoded image signal is obtained at the decoded image signal terminal 5 as in the conventional circuit example. This signal terminal 5 is connected to the input selection circuits 15, 1
Connected to 6. The input selection circuit 15 selects the decoded image signal or the output of the frame memory 1 by the control signal C1 and inputs the selected signal to the post filter 11. In this post filter, a low-pass filter is applied to an input image adaptively to suppress noise.

On the other hand, the input selection circuit 16 selects the decoded image signal, the output of the frame memory 14, or the output of the external memory 18 by the control signal C2 and inputs the selected signal to the coordinate conversion circuit 12. The coordinate conversion circuit 12 modifies the read address of the input data or the write address to the frame memory based on the control signal C0, and performs coordinate conversion such as enlargement / reduction / movement between input / output images.

The pattern conversion circuit 13 inputs a character code or the like from the external memory 18 and converts it into pattern data based on the control signal C0.

The output selection circuit 17 is a post filter 11, a coordinate conversion circuit 12,
Alternatively, the output of the pattern conversion circuit 13 is selected by the control signal C3 and output to the display output terminal 9. Similarly, the selected signal is input to the frame memory 14. The frame memory 14 basically generates a one-frame delay, but the writing condition is controlled by the control signal C4. That is, the frame memory 14 can hold an image by prohibiting writing.

The control signals C0, C1, C2, C3, and C4 are generated by the display image control circuit 19 corresponding to the configuration of the display image. Therefore, a map specifying an image to be displayed is set in the display image control circuit 19 corresponding to each block when the display image is decomposed into 16 × 16 pixel blocks. This display image control circuit creates control signals C0, C1, C2, C3, C4 based on this map. The set of maps shall be created based on the man-machine interface between the user of the image and the circuit.

For example, in a block displaying a decoded image, C1 specifies a decoded image signal, and C3 specifies a post filter.

In the block for reducing and displaying the image in the external memory 18, C2 specifies the external memory, and C3 specifies the coordinate conversion circuit. The enlargement / reduction / movement parameters used in the coordinate conversion circuit 12 are designated in the map, and the display image control circuit 19 notifies the coordinate conversion circuit 12 by the signal control C0.

In a block for holding a received image at a certain time and continuously reducing the display, C2 specifies the frame memory 14, C3 specifies the coordinate conversion circuit 12, and C4 specifies write protection.
Specify 14

In a block for displaying the result of the pattern conversion circuit 13, C3 designates the pattern conversion circuit 13, and the pattern conversion circuit 13 converts the data in the external memory 18 into a pattern based on the control signal C0 and outputs the pattern.

The operation of this circuit will be described with reference to FIG. In the figure, A and B indicate two areas of the display image.
A map is set in the display image control circuit 19 so that different types of images are displayed for each area.
There are combinations as shown in the table in FIG.

That is, in some cases (a), the decoded image is displayed in the area A, and the past received image held in the frame memory 18 is reduced and displayed in the area B. At the next time (a), this is reversed and the past received image held in the frame memory 18 is stored in the area A, and the currently received decoded image is stored in the area B.
To be reduced to. This switching is performed by rewriting the aforementioned map data. The number of regions is A,
B is not limited to two and can be increased to the number of blocks as needed.

Although the display image signal control apparatus has been described based on the operation of the signal processing circuit, each processing circuit may be realized by a processor that performs digital signal processing. That is, the gist of the present invention is to control the data flow of one frame memory, post-filter processing, coordinate conversion processing, and the like according to the configuration of a display image.

Although the configuration example in which the pattern conversion circuit 13 is included in the signal processing has been described, this may be another processing such as an output image of a personal computer.

Although detailed description is omitted in the embodiment, the coordinate conversion circuit
Reference numeral 12 creates read / write addresses of input / output data in accordance with coordinate conversion parameters. When performing coordinate conversion of the data in the frame memory 14 and the external memory 18, the read address may be modified. In order to convert the coordinates of the decoded image, the write address of the frame memory is modified and the decoded image is written in a window that displays the reduced size of the decoded image. At this time, the display output needs to be fixed in the frame memory. To realize this function, only in this case, the output selection circuit 17 selects different data for the display output and the frame memory input.

(Effect of the Invention) As described above, according to the present invention, it is possible to obtain a highly functional display image using a simple circuit, and thus a display image for converting an encoded and transmitted image signal into a display image. Can be used as a signal processing device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 1 is a diagram for explaining the operation of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional display image processing circuit. 1 ... image signal input terminal, 2 ... encoding device, 3 ... transmission line, 4 ... decoding device, 5 ... decoded image signal terminal, 9
…… Display output terminal, 10 ′ …… Display image processing circuit, 11 ……
Post filter, 12 ... Coordinate conversion circuit, 13 ... Pattern conversion circuit, 14 ... Frame memory, 15, 16 ... Input selection circuit, 17 ... Output selection circuit, 18 ... External memory, 19 ...
Display image control circuit.

Claims (1)

(57) [Claims] In a signal processing device for converting an image signal transmitted by high compression encoding into a display image, a post filter for removing noise from an input image is provided by a decoding device or a frame memory for storing one frame of image data. A coordinate conversion circuit configured to selectively input data; a coordinate conversion circuit that performs coordinate conversion of the input image; and a data conversion circuit configured to selectively input data from the decoding device, a frame memory, or an external memory. A pattern conversion circuit configured to receive image data of the decoding device, a character code from an external memory, or the like; and a display image output and a frame memory input data, the post-filter or the coordinate conversion circuit or the pattern. The processing result of any one of the conversion circuits is selected and created. The frame memory is controlled by a write control signal. The post filter input selection signal, the coordinate conversion circuit input selection signal, the display image output and frame memory input selection signal, and the frame memory write control signal A display image signal processing device configured to be provided as a control code from a display image control circuit for each of the divided areas.