JP2743778B2 - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JP2743778B2 JP2743778B2 JP5176603A JP17660393A JP2743778B2 JP 2743778 B2 JP2743778 B2 JP 2743778B2 JP 5176603 A JP5176603 A JP 5176603A JP 17660393 A JP17660393 A JP 17660393A JP 2743778 B2 JP2743778 B2 JP 2743778B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating material
- lead
- lead frame
- semiconductor device
- bus bar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置用リードフ
レームに関し、特に、インナーリード表面の一部に絶縁
材が塗布されたリードフレームに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame in which an insulating material is applied to a part of an inner lead surface.
【０００２】[0002]
【従来の技術】一般に、半導体装置に使用されるリード
フレームは、インナーリードの前方にタブと呼ばれる部
分を有し、そのタブに半導体素子を載置して固定するよ
うに形成されている。タブとインナーリードとの間には
若干の隙間が形成されており、半導体素子の電極とイン
ナーリードとの結線は、その隙間を跨いでボンディング
ワイヤにより行われている。最近、半導体集積回路の大
容量化に伴って半導体素子の寸法が大きくなり、前記隙
間を形成する余裕がなくなると共に、樹脂封入に必要な
長さをインナーリードの部分に確保することが困難にな
ってきている。2. Description of the Related Art In general, a lead frame used for a semiconductor device has a portion called a tab in front of an inner lead, and is formed so that a semiconductor element is placed and fixed on the tab. A slight gap is formed between the tab and the inner lead, and the connection between the electrode of the semiconductor element and the inner lead is made by a bonding wire across the gap. Recently, as the capacity of a semiconductor integrated circuit increases, the size of a semiconductor element increases, so that there is no room for forming the gap, and it is difficult to secure a length necessary for resin encapsulation in an inner lead portion. Is coming.
【０００３】このような問題を解決するために、タブを
省略し、インナーリードに絶縁フィルムを介して直接半
導体素子を固定する提案がなされている。ところで、上
記のような半導体装置用リードフレームは、装置構成の
必要上、バスバー（電源接続用の母線部分）をインナー
リードの前方（半導体チップ側）に配設する必要があ
る。このようなリ−ドフレームを使用した半導体装置に
おいては、インナーリードと半導体素子の電極とを接続
するボンディングワイヤが、バスバーに接触し、短絡す
ることが考えられる。この短絡を防止するために電源ス
テ−ジに絶縁材を配置させている。この絶縁材として
は、絶縁性の高い接着剤が多く用いられ、この接着剤を
塗布する方法としては、溶媒を混入してワニス状として
絶縁の必要なバスバー上に塗布する方法が採られてい
る。In order to solve such a problem, it has been proposed to omit a tab and directly fix a semiconductor element to an inner lead via an insulating film. By the way, in the semiconductor device lead frame as described above, it is necessary to arrange a bus bar (a bus portion for power supply connection) in front of the inner lead (semiconductor chip side) due to the necessity of the device configuration. In a semiconductor device using such a lead frame, it is conceivable that a bonding wire connecting an inner lead and an electrode of a semiconductor element contacts a bus bar and is short-circuited. In order to prevent this short circuit, an insulating material is arranged on the power stage. As this insulating material, an adhesive having a high insulating property is often used, and as a method of applying this adhesive, a method of mixing a solvent and applying it as a varnish to a bus bar requiring insulation is adopted. .
【０００４】[0004]
【発明が解決しようとする課題】上記のようなリードフ
レームにおいては、絶縁材がワニス状で塗布されるた
め、絶縁の必要のない部分に絶縁材が流れるという問題
があった。このことを防止するために塗布するワニス状
絶縁材を比較的少量にすることで対応しようとすると、
絶縁が必要な部分に絶縁材を均一に塗布するのが困難
で、塗布形状が非常に不安定となり、絶縁材を十分な厚
さとすることができないという問題があった。In the above-described lead frame, since the insulating material is applied in the form of a varnish, there is a problem that the insulating material flows to portions where insulation is not required. In order to prevent this, it is necessary to use a relatively small amount of varnish-like insulating material applied.
There is a problem that it is difficult to uniformly apply an insulating material to a portion where insulation is required, the applied shape becomes extremely unstable, and the insulating material cannot be formed to a sufficient thickness.
【０００５】本発明は、上記事情に鑑みなれたものであ
り、その目的は、絶縁材の流れを防止し、絶縁材の塗布
範囲を正確に決定することができ、絶縁材を十分に厚く
することのできる半導体装置用リードフレームを提供す
ることにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to prevent the flow of an insulating material, to accurately determine an application range of the insulating material, and to make the insulating material sufficiently thick. To provide a lead frame for a semiconductor device that can be used.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、本発明に係る半導体装置用リードフレームは、ボン
ディングワイヤとの接触防止が必要なバスバーが一体的
に形成されたインナーリードのボンディングワイヤ側の
当該バスバーの表面に絶縁材を設けた半導体装置用リー
ドフレームであって、前記バスバーが一体的に形成され
たインナーリードのボンディングワイヤ側に当該インナ
ーリードの幅方向の両側面において開放された絶縁材の
流れを防止するための流れ防止用溝を設けたことを特徴
としている。In order to achieve the above object, a lead frame for a semiconductor device according to the present invention comprises a bus bar which is required to prevent contact with a bonding wire.
Of the inner lead formed on the bonding wire side
A lead frame for a semiconductor device having an insulating material provided on a surface of the bus bar , wherein the bus bar is integrally formed.
The inner wire to the bonding wire side of the inner lead.
A flow preventing groove for preventing the flow of the insulating material opened on both side surfaces in the width direction of the lead;
【０００７】ここで、前記流れ防止用溝が、前記ボンデ
ィングワイヤ側のインナーリードのワイヤボンディング
部の一端または両端に設けられるのが好ましい。Here, it is preferable that the flow preventing groove is provided at one end or both ends of a wire bonding portion of the inner lead on the bonding wire side.
【０００８】[0008]
【作用】本発明の半導体装置用リードフレームによれ
ば、絶縁材の流れを防止するための流れ防止用溝が形成
されているので、インナーリード表面に載せられたワニ
ス状絶縁材は、その表面張力により流れ防止用溝のエッ
ジに沿って、その周部を形成し、所定部以外への流れ出
しがなく、絶縁材の塗布範囲が決定される。According to the lead frame for a semiconductor device of the present invention, since the flow preventing groove for preventing the flow of the insulating material is formed, the varnish-like insulating material placed on the surface of the inner lead is removed from the surface thereof. The peripheral portion is formed along the edge of the flow preventing groove by the tension, and there is no flow to a portion other than the predetermined portion, and the application range of the insulating material is determined.
【０００９】[0009]
【実施例】以下、本発明の半導体装置用リードフレーム
を、添付の図面に示す好適実施例に基づいて詳細に説明
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead frame for a semiconductor device according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.
【００１０】図１および図２は、それぞれ本発明の半導
体装置用リードフレームの一実施例の模式的部分斜視図
および部分断面図である。FIGS. 1 and 2 are a schematic partial perspective view and a partial sectional view, respectively, of an embodiment of a lead frame for a semiconductor device according to the present invention.
【００１１】図１および図２に示すように、半導体装置
用リードフレーム１は、エッチングなどによって形成さ
れたもので、インナーリード２がリードフレーム１の中
央部方向に収束するように伸長しているものである。イ
ンナーリード２には、信号伝達用リード３と電源用リー
ド（接地用リードも含む）４とがある。電源用リード４
は、その先端に、信号用リード３の伸長方向と略直交す
る方向にバスバー５が一体的に形成されている。As shown in FIGS. 1 and 2, the semiconductor device lead frame 1 is formed by etching or the like, and the inner leads 2 extend so as to converge toward the center of the lead frame 1. Things. The inner leads 2 include a signal transmission lead 3 and a power supply lead (including a grounding lead) 4. Power supply lead 4
A bus bar 5 is integrally formed at a tip end thereof in a direction substantially perpendicular to a direction in which the signal lead 3 extends.
【００１２】インナーリード３および電源用リード４の
片面には、絶縁フィルム６を介して半導体素子７が取り
付けられている。半導体素子７には、インナーリード２
側に複数の電極８が形成されている。電極８と、インナ
ーリード２のワイヤボンディング部２ａとは、それぞれ
ボンディングワイヤ９の端部が固着され接続されてい
る。A semiconductor element 7 is mounted on one side of the inner lead 3 and the power supply lead 4 via an insulating film 6. The semiconductor element 7 has an inner lead 2
A plurality of electrodes 8 are formed on the side. The ends of the bonding wires 9 are fixedly connected to the electrodes 8 and the wire bonding portions 2a of the inner leads 2, respectively.
【００１３】バスバー５のボンディングワイヤ９側の表
面には、ボンディングワイヤ９との電気的接続を防止す
るための絶縁材１０が固着されている。絶縁材１０とし
ては、絶縁性の高い接着剤が好適に用いられる。この絶
縁材１０は、塗布時には溶剤と混合してワニス状として
使用されるものである。このようなワニス状絶縁材（接
着剤）としては、例えば熱可塑性ポリエーテルアミドイ
ミドを溶剤であるＮＭＰ（Ｎ−メチル−２−ピロリド
ン）で溶かしたもの、絶縁性および接着性を有するポリ
アミドイミド系のもの、およびこれらに添加物として平
均粒径１０μｍのＳｉ０2 を混入したものなどを使用す
ることができる。このように、絶縁材１０はワニス状に
してバスバー５上に塗布されるので、ワニスの表面張力
によって流れ防止用溝１１のエッジ１１ａで堰止められ
（図３（ａ）参照）容易に流れ防止用溝１１を越えるこ
とはできない。したがって、バスバー５およびバスバー
５が一体的に形成された電源用リード４のワイヤボンデ
ィング部２ａまでワニス状絶縁材１０が流れ出すことは
ない。したがって、この絶縁材１０の塗布範囲を、流れ
防止用溝１１のエッジ１１ａまでに制限することができ
る。An insulating material 10 for preventing electrical connection with the bonding wire 9 is fixed to the surface of the bus bar 5 on the side of the bonding wire 9. As the insulating material 10, an adhesive having high insulating properties is preferably used. The insulating material 10 is used as a varnish by mixing with a solvent at the time of coating. As such a varnish-like insulating material (adhesive), for example, a thermoplastic polyether amide imide dissolved in a solvent NMP (N-methyl-2-pyrrolidone), or a polyamide imide based material having insulating and adhesive properties ones, and it can be used like those in that mixed with Si0 2 having an average particle size of 10μm as an additive. As described above, since the insulating material 10 is applied to the bus bar 5 in the form of a varnish, the insulating material 10 is blocked by the edges 11a of the flow preventing grooves 11 due to the surface tension of the varnish (see FIG. 3A) and easily prevents the flow. The groove cannot be exceeded. Therefore, the varnish-like insulating material 10 does not flow out to the wire bonding portion 2a of the bus bar 5 and the power supply lead 4 in which the bus bar 5 is integrally formed. Therefore, the application range of the insulating material 10 can be limited to the edge 11 a of the flow preventing groove 11.
【００１４】流れ防止用溝１１は、絶縁材塗布工程にお
いてワニス状接着剤が所定部以外に流れ出すのを防止す
るためのもので、電源用リード４の、絶縁を必要とする
部分とワイヤボンディング部２ａとの間に形成れたもの
である。この流れ防止用溝１１は、電源用リード４およ
びバスバー５のボンディングワイヤ９側に形成されたも
ので、それぞれのリードの幅方向に全幅に渡って形成さ
れている。この流れ防止用溝１１の形状は特に限定され
るものではなく、例えば図３（ａ）に示すように断面形
状がＶ字型のものを用いることができる。The flow preventing groove 11 is for preventing the varnish-like adhesive from flowing out of a predetermined portion in the insulating material applying step, and is provided between the portion of the power supply lead 4 which requires insulation and the wire bonding portion. 2a. The flow preventing groove 11 is formed on the bonding wire 9 side of the power supply lead 4 and the bus bar 5 and is formed over the entire width in the width direction of each lead. The shape of the flow preventing groove 11 is not particularly limited. For example, a groove having a V-shaped cross section as shown in FIG. 3A can be used.
【００１５】上記のような構成がモールドレジン１３に
よって封入され、半導体装置１２となるものである。The above structure is sealed in the mold resin 13 to form the semiconductor device 12.
【００１６】上述の半導体装置用リードフレーム１は、
例えばエッチングにより形成することができるが、この
時、前記流れ防止用溝１１は、例えばハ−フエッチとし
て形成することができる。The above-described lead frame 1 for a semiconductor device comprises:
For example, it can be formed by etching. At this time, the flow preventing groove 11 can be formed as, for example, a half-etch.
【００１７】上記のような半導体装置用リードフレーム
１によれば、流れ防止用溝１１が形成されているので、
絶縁材１０を形成するためにワニス状接着剤を塗布する
工程において、塗布範囲が防止用溝１１のエッジ１１ａ
によって決定され、そのためワイヤボンディング部２ａ
に流れる心配がなく、塗布工程の迅速化に貢献するこが
できる。また、塗布範囲が、予め流れ防止用溝１１によ
って絶縁材を必要とする箇所だけに決定されているた
め、絶縁材１０を十分な厚みとすることが容易となり、
リードフレーム１の信頼性の向上を図ることができる。According to the lead frame 1 for a semiconductor device as described above, since the flow preventing groove 11 is formed,
In the step of applying the varnish-like adhesive to form the insulating material 10, the application range is the edge 11 a of the prevention groove 11.
And therefore the wire bonding portion 2a
This can contribute to speeding up the coating process without worrying about flowing. In addition, since the application range is determined in advance only at locations where the insulating material is required by the flow preventing grooves 11, it is easy to make the insulating material 10 a sufficient thickness,
The reliability of the lead frame 1 can be improved.
【００１８】なお、上述したように流れ防止用溝として
は、特に制限的ではなく、図３（ａ）に示す断面形状が
Ｖ字型の流れ防止用溝１１の他に、図３（ｂ）および
（ｃ）に示すように、断面形状がＵ字型の流れ防止用溝
１４でもよく、また、開口部の幅Ｗが内部の幅より狭く
なっているオーバーハング状の流れ防止用溝１５でもよ
い。ワニス状絶縁材の堰止め効果としては、流れ防止用
溝幅Ｗ、あるいはその深さｄよりもインナーリード表面
と溝の内壁とのなす角（コーナ角度）θの影響が大きい
ので、コーナ角θが大きい程、その効果は大である。し
たがって、図３（ｂ），（ｃ）に示す流れ防止用溝１
４，１５の方が、図３（ａ）に示す断面形状がＶ字型の
流れ防止用溝１１に比べ、インナーリード表面と溝の内
壁とのなす角度θが大きく、ワニス状絶縁材の流出を防
止する効果が大きい。As described above, the flow preventing groove is not particularly limited. In addition to the flow preventing groove 11 having a V-shaped cross section shown in FIG. As shown in (c), the flow preventing groove 14 having a U-shaped cross section or the overhanging flow preventing groove 15 in which the width W of the opening is smaller than the inner width may be used. Good. The varnish-like insulating material has an effect of blocking the flow preventing groove width W or the depth d of the angle (corner angle) θ between the inner lead surface and the inner wall of the groove. The greater the value, the greater the effect. Therefore, the flow preventing groove 1 shown in FIGS.
4 and 15, the angle θ between the inner lead surface and the inner wall of the groove is larger than that of the flow-preventing groove 11 having a V-shaped cross section shown in FIG. The effect of preventing is great.
【００１９】また、上述したリードフレーム１は、電源
用リード４の先端にバスバー５が一体的に形成されたも
のであるが、本発明はこれに限定されるものではなく、
例えば、接地用リードあるいは信号用リードの先端にバ
スバーが一体的に形成されたリードフレームにも適用可
能である。In the lead frame 1 described above, the bus bar 5 is integrally formed at the tip of the power supply lead 4, but the present invention is not limited to this.
For example, the present invention is also applicable to a lead frame in which a bus bar is integrally formed at the tip of a ground lead or a signal lead.
【００２０】[0020]
【発明の効果】以上詳細に説明したように、本発明に係
る半導体装置用リードフレームによれば、バスバーが一
体的に形成されたインナーリードのボンディングワイヤ
側に当該インナーリードの幅方向の両側面において開放
された絶縁材の流れ防止用溝が形成されているので、絶
縁材の塗布範囲を正確に決定することができ、また、絶
縁材を厚くする事も可能になる。これにより、半導体装
置用リードフレームの絶縁材塗布の信頼性および作業性
ならびにリードフレーム自体の信頼性の向上を図ること
ができる。As described above in detail, according to the semiconductor device lead frame of the present invention, one bus bar is provided.
Body-formed inner lead bonding wire
Open on both sides in the width direction of the inner lead
Since the groove for preventing the flow of the insulating material is formed, the application range of the insulating material can be accurately determined, and the thickness of the insulating material can be increased. Thus, the reliability and workability of applying the insulating material to the lead frame for a semiconductor device and the reliability of the lead frame itself can be improved.
【図１】 本発明に係る半導体装置用リードフレームの
一実施例の部分概略斜視図である。FIG. 1 is a partial schematic perspective view of one embodiment of a lead frame for a semiconductor device according to the present invention.
【図２】 本発明に係る半導体装置用リードフレームの
一実施例の部分断面図である。FIG. 2 is a partial cross-sectional view of one embodiment of a lead frame for a semiconductor device according to the present invention.
【図３】 （ａ），（ｂ）および（ｃ）は、それぞれ本
発明に係る半導体装置用リードフレームの流れ防止用溝
の一実施例の断面図である。FIGS. 3A, 3B, and 3C are cross-sectional views of an embodiment of a groove for preventing flow of a lead frame for a semiconductor device according to the present invention.
１ 半導体装置用リードフレーム ２ インナーリード ２ａ ワイヤボンディング部 ３ 信号用リード ４ 電源用リード ５ バスバー ６ 絶縁フィルム ７ 半導体素子 ８ 電極 ９ ボンディングワイヤ １０ 絶縁材 １１，１４，１５ 流れ防止用溝 １２ 半導体装置 １３ モールドレジン DESCRIPTION OF SYMBOLS 1 Lead frame for semiconductor devices 2 Inner lead 2a Wire bonding part 3 Signal lead 4 Power supply lead 5 Bus bar 6 Insulating film 7 Semiconductor element 8 Electrode 9 Bonding wire 10 Insulating material 11, 14, 15 Flow prevention groove 12 Semiconductor device 13 Mold resin
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小 山 秀 幸 茨城県土浦市木田余町3550番地 日立電 線株式会社 システムマテリアル研究所 内 (72)発明者 川 村 敏 雄 茨城県日立市助川町３丁目１番１号 日 立電線株式会社 電線工場内 (56)参考文献 特開 平５−13654（ＪＰ，Ａ) 特開 平４−199559（ＪＰ，Ａ) ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Hideyuki Koyama 3550 Kida Yomachi, Tsuchiura City, Ibaraki Prefecture Within Hitachi Systems, Ltd. 3-1-1, Hitachi Cable Co., Ltd. Inside the electric wire factory (56) References JP-A-5-13654 (JP, A) JP-A-4-199559 (JP, A)
Claims (2)
とがワイヤボンディングされており、ボンディングワイ
ヤとの接触防止が必要なバスバーが一体的に形成された
インナーリードのボンディングワイヤ側の当該バスバー
の表面に絶縁材を設けた半導体装置用リードフレームで
あって、前記バスバーが一体的に形成されたインナーリ
ードのボンディングワイヤ側に当該インナーリードの幅
方向の両側面において開放された絶縁材の流れを防止す
るための流れ防止用溝を設けたことを特徴とする半導体
装置用リードフレーム。An electrode of a semiconductor element is wire-bonded to a tip of an inner lead, and a bus bar which requires prevention of contact with a bonding wire is integrally formed.
A lead frame for a semiconductor device, wherein an insulating material is provided on the surface of the bus bar on the bonding wire side of the inner lead , wherein the bus bar is integrally formed.
The width of the inner lead on the bonding wire side of the
A lead frame for a semiconductor device, wherein a flow preventing groove for preventing a flow of an insulating material opened on both side surfaces in a direction is provided.
イヤ側のインナーリードのワイヤボンディング部の一端
または両端に設けられる請求項１に記載の半導体装置用
リードフレーム。2. The lead frame for a semiconductor device according to claim 1, wherein the flow preventing groove is provided at one or both ends of a wire bonding portion of the inner lead on the bonding wire side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5176603A JP2743778B2 (en) | 1993-07-16 | 1993-07-16 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5176603A JP2743778B2 (en) | 1993-07-16 | 1993-07-16 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0738044A JPH0738044A (en) | 1995-02-07 |
| JP2743778B2 true JP2743778B2 (en) | 1998-04-22 |
Family
ID=16016460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5176603A Expired - Fee Related JP2743778B2 (en) | 1993-07-16 | 1993-07-16 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2743778B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10034006A1 (en) * | 2000-07-07 | 2002-01-24 | Infineon Technologies Ag | Carrier matrix with bond channel for integrated semiconductors and process for their production |
| JP2007330036A (en) * | 2006-06-07 | 2007-12-20 | Seiko Epson Corp | Oscillating object, piezoelectric actuator, electronic equipment, and method of manufacturing of oscillating object |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04199559A (en) * | 1990-11-28 | 1992-07-20 | Mitsubishi Electric Corp | Semiconductor device |
| JP2670392B2 (en) * | 1991-07-05 | 1997-10-29 | 日立電線株式会社 | Semiconductor integrated circuit device |
-
1993
- 1993-07-16 JP JP5176603A patent/JP2743778B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0738044A (en) | 1995-02-07 |
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