JP2741813B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a bipolar transistor and a Bi transistor having a MOS transistor on the same semiconductor substrate.
It relates to CMOS.

[0002]

2. Description of the Related Art FIG. 8 is a sectional view of a conventional bipolar transistor 100. As shown in FIG. An epitaxial layer 3 is formed on a semiconductor substrate 1.
, A floating collector 2 is formed at the boundary, and an intrinsic base region 1 formed above the epitaxial layer 3 is formed.
8. Together with the emitter region 21, the bipolar transistor 100 is formed. The floating collector 2 has a collector wall 6 penetrating the epitaxial layer 3.
Is connected.

An external base region 17 connected to an intrinsic base region 18 is connected to an upper portion of the epitaxial layer 3,
In the external base region 17, the base extraction electrode 1 is provided from above.
5 is connected. The base extraction electrode is insulated from the epitaxial layer 3 by the selectively formed insulating film 5.

An emitter extraction electrode 20 is connected to the emitter region 21 from above.
The base extraction electrode 1 is formed by the side wall 19 made of an insulator.
5 is insulated. When forming such a bipolar transistor 100, first, the epitaxial layer 3
After forming the insulating film 5 on the entire surface above the desired resist pattern 13 as shown in FIG. 9 is formed on this, then FIG.
As shown in FIG. 10 , the insulating film 5 is anisotropically etched using the resist pattern 13 as a mask, and a desired opening is formed. Thereby, the cross section 14 of the insulating film 5 appears. Thereafter, the regions 17, 18, 21 and the electrodes 15, 20 are formed.

[0005] Such a bipolar transistor is
It is also used in BiCMOS devices having MOS transistors.

[0006]

Since the opening of the insulating film on the base region of the conventional bipolar transistor is formed as described above, the cross section 14 of the insulating film 5 is substantially perpendicular to the semiconductor substrate 1. Therefore, there is a problem that the coverage of the opening of the base lead electrode 5 formed after the opening is deteriorated, and the base resistance is increased. In addition, the intrinsic region formed in the later
Anisotropic etching of the joint area on the substrate surface
Damage due to etching near the junction
And the base leakage current caused by this causes
There was a problem that transistor characteristics deteriorated.

On the other hand, forming a BiCMOS device having a bipolar transistor 100 as shown in FIG. 8 also causes other problems. A BiCMOS device is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-253654. For example, as shown in FIG. 14 , to form a BiCMOS device 300 including a bipolar transistor 100 and a MOS transistor 200, the following steps can be performed.

First, a conductive layer opposite to the semiconductor substrate 1 is provided below the region where the bipolar transistor 100 is formed on the semiconductor substrate 1, and the buried layer 2 and the epitaxial layer 3 are formed by epitaxial growth. And MO
A well 4 is formed below the region where the S transistor 200 is formed.
Is formed, and the insulating film 5 is selectively formed by the LOCOS method or the like. After further forming the collector wall 6,
A gate insulating film 7 is formed, and a gate electrode 8 is formed. Using this as a mask, a low-concentration source / drain 9 is formed by ion implantation, an insulating film is formed over the entire surface of the semiconductor substrate, and the insulating film is anisotropically etched by the thickness to form a gate electrode 10. 8 is formed on the end face.
Further, high-concentration source / drain 11 is formed by ion implantation.
To complete the MOS transistor 200 (FIG. 1)
1 ).

At this time, the insulating film 5 separates the MOS transistor 200 from the element, and protects the epitaxial layer 3 in the region where the bipolar transistor 100 is to be formed from damage when the side wall 10 is formed.

Next, the insulating film 5 is etched using the resist pattern 13 to expose the epitaxial layer 3.
Thus, after the opening H appears, the same conductive pattern ion implantation as that of the semiconductor substrate 1 is performed by using the same resist pattern 13 to form the intrinsic base region 18 (FIG. 12 ). At this time, the insulating film 5 has a cross section 14.

Subsequently, the resist pattern 13 is removed,
After polycrystalline silicon is formed on the entire surface of the structure obtained in the above steps, ion implantation of the same conductivity type as that of the semiconductor substrate 1 is performed, an insulating film 16 is further formed, and a resist pattern corresponding to the base electrode is formed. (Not shown) using an insulating film 16
And etching of polycrystalline silicon. The remaining polycrystalline silicon becomes the base electrode 15. Then, heat treatment is performed to remove impurities from the base electrode 15 to the epitaxial layer 3.
To form an external base region 17 (FIG. 1 ).
3 ).

Further, a side wall 19 is formed on the end surfaces of the base electrode 15 and the insulating film 16 in the same manner as the formation of the side wall 10. Then, polycrystalline silicon is formed above the base regions 17 and 18, conduction type ion implantation opposite to that of the semiconductor substrate 1 is performed, and etching is performed using a resist pattern (not shown) corresponding to the emitter electrode. The remaining polycrystalline silicon becomes the emitter electrode 20. Then, by performing a heat treatment, the impurities implanted into the emitter electrode 20 are diffused into the intrinsic base region 18 to form the emitter region 21 (FIG. 14 ).

When the BiCMOS device 300 is constructed as described above, if the base electrode 15 is formed by over-etching, the surface of the epitaxial layer 3 is etched, the depth of the intrinsic base 18 becomes shallower, and Emitter-collector breakdown voltage B of transistor 100
A problem arises in that VCEO deteriorates and the element characteristics fluctuate depending on the amount of overetching. If the base electrode 15 and the emitter electrode 20 are over-etched when formed, the surface of the high-concentration source / drain 11 is etched, and the sheet resistance and the increase in leakage between the source / drain 9, 11 and the well 4 are reduced. The problem of causing Furthermore, if the gate electrode 8 is formed of a material that is etched when forming the electrodes 15 and 20 such as polycrystalline silicon, the thickness of the gate electrode 8 is similarly reduced, thereby increasing the sheet resistance.

[0014] The present invention has been made to solve the above problems, as well as improving the coverage of the base electrode of the bipolar transistor, and good transistor can be prevented from increasing base resistance Characteristics
Aims at obtaining a semiconductor device and a manufacturing method thereof Ru can be obtained.

The present invention can stabilize the device characteristics of a bipolar transistor even if overetching occurs when forming a base electrode without increasing the number of masks, and can form a base electrode and an emitter electrode. It is an object of the present invention to provide a semiconductor device and a manufacturing method suitable for manufacturing the semiconductor device, which prevent the source / drain surfaces and the gate electrode of a MOS transistor from being etched from being over-etched during the etching.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate having one main surface, a base region exposed on the main surface, and a base electrode formed on the base region.
A bipolar transistor having an emitter electrode extending on a base electrode, and a bipolar transistor formed on a base region and opened at a predetermined portion on the base region.
A first insulating film and a main surface on which the first insulating film permits exposure;
Source and drain regions formed on the main surface and exposed
And a gate formed above a main surface via a gate insulating film.
Gate electrode and at least a source region, a drain region and a gate region.
MOS transistor having a second insulating film covering a gate electrode
And the base electrode extends on the second insulating film.
You .

A semiconductor device according to a second aspect of the present invention has a
A La-type transistor, a third insulating film covering the base electrode,
The third insulating film is formed above the base region where the exposure is allowed.
And an emitter region .

According to a third aspect of the present invention, there is provided a semiconductor device comprising:
The film is opened at a predetermined portion on the base region.
Near the boundary with the base region,
Inclined toward the center of the base area and rounded
I have .

A method for manufacturing a semiconductor device according to claim 4.
(A) a semiconductor substrate having a well region on one main surface side
Forming a first insulating film on the main surface of
In the upper region where the first insulating film allows exposure,
Forming an OS transistor; and (b) a semiconductor substrate.
In the region on the impurity layer located on the main surface side,
The insulating film is selectively removed, and an opening is formed in a predetermined first portion.
Exposing the main surface, and (c) adding a bipolar
Forming a base region of the transistor.
The MOS transistor has a source region exposed on the main surface and a MOS transistor.
And the drain region and the gate insulating film above the main surface
And a gate electrode to be formed.
1) At least a source region, a drain region, and a gate electrode
And forming a second insulating film covering the base region;
(B-2) Step (b) of selectively removing the first insulating film
Steps performed after -1) and (b-3) First part
Selectively removing the second insulating film in
Step (c) is exposed in the (c-1) first part.
Conductive first semiconductor layer opposite to the impurity layer and covering the main surface
Forming a third insulating film covering the first semiconductor layer
And (c-2) in a predetermined second portion of the first portion,
The first semiconductor layer and the third insulating film are selectively removed to form an opening.
(C-3) heat treatment to form a first semiconductor layer
To the main surface of the first portion from the conduction type opposite to the impurity layer.
Diffusing one impurity; and (c-4) opening the first
A second impurity of the same conductivity type as the impurity layer is deposited through the two portions.
(C-5) at least the second step
A third impurity of a conductivity type opposite to the impurity layer through the main surface
And a step of introducing

A method of manufacturing a semiconductor device according to claim 5.
In the step (b-2), the isotropic etching is used to form the first
This is a step of selectively removing the insulating film .

[0021]

[0022]

[0023]

According to the semiconductor device of the present invention, the first insulating film comprises:
A region where a bipolar transistor is to be formed is a MOS transistor.
Protects from damage during transistor formation,
The edge film forms a bipolar region of the impurity region of the MOS transistor.
Protects from damage during the formation of the la-type transistor.

Further in the semiconductor device of the present invention, base -
Near the boundary with the base region, toward the center of the base region
The first insulating film, which is inclined in the direction
Improve the coverage of the electrode. Also, etching damage
Since it does not enter, good transistor characteristics can be obtained.

The method for manufacturing a semiconductor device according to the present invention is suitable for manufacturing the semiconductor device according to the present invention.

[0026]

FIG. 1 shows a cross section of a bipolar transistor 101 according to a reference example of the present invention. 8 differs from the transistor 100 shown in FIG. 8 only in the shape of the cross section 14 a of the insulating film 5. Epitaxial layer 3 including external base region 17
In the vicinity of the surface, the section 14a is inclined in the direction from the insulating film 5 toward the emitter region 21 and is rounded.
Therefore, the coverage of the base electrode 15 with respect to the external base region 17 is improved, and an increase in base resistance can be suppressed.

The transistor 10 having the above-mentioned cross section 14a
1 can be obtained by performing isotropic etching at the time of opening the insulating film 5. Hereinafter, a first embodiment of the present invention will be described. After a desired resist pattern 13 is provided on the insulating film 5 as shown in FIG. 9, the insulating film 5 is dug down halfway by anisotropic etching as shown in FIG. After that, the insulating film 5 is etched by isotropic etching to expose the surface of the epitaxial layer 3. By opening the insulating film 5 in this manner, as shown in FIG. 3, a rounded cross section 14a can be obtained near the boundary with the epitaxial layer 3, and etching damage is prevented. Can be.

Thereafter, by introducing impurities and forming electrodes in the same manner as in the conventional case, the transistor 101 can be obtained. In the above embodiment, the insulating film 5 is used.
Although anisotropic etching is used in the initial stage of the etching, isotropic etching may be performed from the beginning. However, on this occasion
The opening above the insulating film than the opening in the resist pattern
Part becomes larger by the thickness of the insulating film on at least one side.
I will.

4 to 7 show a method of manufacturing a BiCMOS device 301 according to a second embodiment of the present invention in the order of steps.

As described with reference to FIG. 8 , a buried layer 2, an epitaxial layer 3, a well 4, and an insulating film 5 are formed on a semiconductor substrate 1, and a MOS is formed in the well 4.
The transistor 200 is formed. Thereafter, an insulating film 12 is formed on the entire surface of the structure obtained so far (FIG. 4).

Next, the insulating film 12 and the insulating film 5 are etched using the resist pattern 13 to expose the epitaxial layer 3. Thereby, an opening H appears (FIG. 5).

Subsequently, the resist pattern 13 is removed, and polycrystalline silicon 15 is formed on the entire surface of the structure obtained by the above-described steps. Then, the same conductive type ion implantation as that of the semiconductor substrate 1 is performed, and the insulating film is further formed. 16 is formed, and the insulating film 1 is formed using a resist pattern (not shown) corresponding to the base electrode.
6 and the polycrystalline silicon 15 are etched. The remaining polycrystalline silicon 15 becomes a base electrode. And
By performing the heat treatment, impurities are diffused from the base electrode 15 into the epitaxial layer 3 to form the external base region 17. Thereafter, the same conductive type ion implantation as that of the semiconductor substrate 1 is performed on the entire surface of the substrate to form an intrinsic base region 18 (FIG. 6). At this time, since the insulating film 12 serves as a mask, it is not necessary to newly provide a mask pattern. Thereafter, the emitter region 21 and the emitter electrode 20 are formed in the same manner as described with reference to FIG. 14 (FIG. 7). In the steps described with reference to FIGS. 6 and 7, the MOS transistor is protected by the insulating film 12, so that the MOS transistor is over-etched when the base electrode 15 is formed, ion-implanted when the region 18 is formed, and when the electrode 20 is formed. Not affected by etching.

In the above process, the intrinsic base region 18 is formed after the external base region 17 is formed. However, after the base electrode 15 is formed, the intrinsic base region 18 may be formed by performing ion implantation on the entire surface. . At this time, ion implantation
It does not matter whether the resist pattern 13 used to form the base electrode 15 is present or not. Further, the heat treatment used for forming the external base region 17 may be performed together with the heat treatment for forming the emitter 21. In this case, the external base region 17 is formed when the emitter region 21 is formed.

Further, in the above-described process, the ion implantation is not performed when the opening H appears, but the ion implantation may be performed at this time (regardless of the presence or absence of the resist pattern 13). In this case, the impurity layer formed through opening H has a function of connecting external base region 17 and intrinsic base region 18, and intrinsic base region 18 must be formed after base electrode 15 is formed. .

Although the MOS transistor 200 has the LDD structure having the low-concentration source / drain 9 and the high-concentration source / drain 11, the etching of the gate electrode 8 may damage the substrate surface. Has one kind of source / drain
The same effect can be obtained even with the Drain structure.

[0036]

Further, in the second embodiment, the regions 17, 18
Although a method of opening the insulating film 5 left above is not particularly shown, for example, when anisotropic etching is used, damage may be caused in the base region by this etching, and the characteristics of the bipolar transistor 100 may be deteriorated. There is. In order to avoid this, it is preferable to use etching that is hardly damaged, for example, isotropic etching as in the reference example. However, if the etching is performed using only isotropic etching, the opening becomes considerably larger than the resist pattern. Therefore, it is desirable to combine with the anisotropic etching (FIGS. 2 and 3).

[0038]

As described above, according to the semiconductor device of the present invention, the first insulating film is formed of a bipolar transistor.
MOS transistor is provided in the area where
Protection from damage during star formation is provided. Change
Then, a second insulating film is formed on the impurity region of the MOS transistor.
To form a bipolar transistor
Protection from time damage is provided. In addition, since the coverage of the base electrode of the bipolar transistor is improved,
An increase in base resistance can be suppressed .

According to the method of the present invention, there is provided a manufacturing method suitable for manufacturing the semiconductor device of the present invention.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a reference example of the present invention.

FIG. 2 is a sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view showing a conventional technique.

FIG. 9 is a sectional view showing a conventional technique in the order of steps.

FIG. 10 is a sectional view showing a conventional technique in the order of steps.

FIG. 11 is a cross-sectional view showing a technique serving as a background of the present invention in the order of steps.

FIG. 12 is a cross-sectional view showing a technique serving as a background of the present invention in the order of steps.

FIG. 13 is a cross-sectional view showing a technique serving as a background of the present invention in the order of steps.

FIG. 14 is a cross-sectional view showing a technique as a background of the present invention in the order of steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 5, 12, 16 Insulating film 8 Gate electrode 9 Low concentration source / drain region 11 High concentration source / drain region 14a Cross section 17 External base region 18 Intrinsic base region

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshiyuki Ishigaki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSI Research Institute (56) References JP-A-4-162534 (JP, A )

Claims (5)

(57) [Claims] 1. A semiconductor substrate having one main surface, base exposed to the main surface - has a source region, said and base electrodes are formed on the base region, an emitter electrode on the base electrode extending Mashimashi and has bar Ipoh - and La-type transistor, the base - is formed on source region, the base - predetermined on source region
A first insulating film that is open at a portion of the first surface, and a first insulating film that is formed on the main surface where the first insulating film allows exposure.
Is a source region and a drain region which is exposed to the main surface, before
A gate formed above the main surface via a gate insulating film
An electrode and at least the source region and the drain region
And a second insulating film covering the gate electrode
And a transistor, wherein the base electrode extends over the second insulating film . 2. The bipolar transistor further includes a third insulating film covering the base electrode, and an emitter region formed above the base region where the third insulating film allows exposure. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the first insulating film is formed on the base region.
A cross section that is open and presented at the predetermined portion
Near the boundary with the base region,
Sloped towards the center of the area and rounded,
The semiconductor device according to claim 1 . 4. (a) A well region is provided on one principal surface side
Forming a first insulating film on the main surface of the semiconductor substrate;
A region on the well region of the surface, the first insulating film
Forms MOS transistors in areas where exposure is allowed
And (b) an impurity located on the main surface side of the semiconductor substrate.
Selective removal of the first insulating film in a region on the material layer
Opening the first surface to expose the main surface
A step, the bipolar transistor in (c) said first portion base
Forming a region , wherein the MOS transistor has a source region exposed on the main surface.
Region and a drain region, and a gate insulating film above the main surface
And a gate electrode formed therethrough. The step (b) comprises: (b-1) at least the source region and the drain region
Insulation covering the region, the gate electrode and the base region
Forming a film; and (b-2) performing the selective removal of the first insulating film;
A step performed after the step (b-1); and (b-3) selecting the second insulating film in the first portion.
And a step of removing, the step (c), covering the main surface was exposed in (c-1) the first part
Forming a conductive first semiconductor layer opposite to the impurity layer and a third insulating film covering the first semiconductor layer;
If, in a given second portion in (c-2) said first portion,
Selectively removing the first semiconductor layer and the third insulating film;
And (c-3) performing a heat treatment to remove the first semiconductor layer from the first semiconductor layer.
Conduction type opposite to the impurity layer to the main surface in the first portion
And (c-4) diffusing the first impurity through the opened second portion.
A second impurity of the same conductivity type as the layer is introduced into the base region;
And that step, (c-5) through said at least said second portion impurity
Introducing a third impurity of a conductivity type opposite to the layer to the main surface
And a method for manufacturing a semiconductor device comprising: 5. The method according to claim 1, wherein said step (b-2) uses isotropic etching to selectively form said first insulating film.
5. The semiconductor device according to claim 4, wherein
Production method.