JP2737673B2 - Monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitoring apparatus, and more particularly, to a monitoring apparatus which monitors a change in an on / off signal by sampling a plurality of on / off signals collectively.

[0002]

2. Description of the Related Art Conventionally, a signal having a binary value such as on / off (hereinafter simply referred to as an "on / off signal") indicates two states, and a change in the state (hereinafter referred to as "state change" as appropriate). A monitoring device that counts and monitors the number of times (abbreviated) is known. For example, this type of monitoring device is used to count the number of times the power device breaker is turned on and off (that is, the number of times the breaker changes shape), and if the number of changes is three or more, the breaker contacts are replaced. Used.

Conventionally, in the data processing section of this type of monitoring apparatus with a state change counter, a state change counter is provided for each on / off signal by hardware for a high-speed counter, and the number of state changes is calculated. Cuts out individual signals from on / off signals periodically and collectively input by software and counts the number of changes.

[0004]

Since counting by hardware requires a state change counter circuit for each ON / OFF signal, the circuit scale becomes large, and in the state change counter circuit, a group must be provided for each counter upper limit. No.

In the case of counting by software, since individual signals are cut out and their changes are counted, the counting process takes a long time to perform high-speed counting, and the processing time becomes longer as the number of on / off signals increases.

It is an object of the present invention to provide a monitoring device having a small circuit scale and capable of counting at high speed.

[0007]

In order to solve the above-mentioned problems, in a monitoring apparatus according to the present invention, a data processing unit detects a change in each bit of an ON / OFF signal input collectively and uses the change signal. By performing a logical data operation, a bit array for each number of state changes is output. That is, the data processing unit compares the current input bit array storing the currently collectively input ON / OFF signal, the previous input bit array storing the previously collectively input ON / OFF signal, the current batch input, and the previous batch input. A change bit array indicating a signal change for each bit, and all signals are reset at the time of initialization.
Time changing bit array and N or more changing bit arrays individually signal-set by the changing bit array;
2,. . . , N−1, all signals are reset at the time of initialization, and thereafter, each time a batch input is performed, the signals are first individually reset by a changed bit array, and then individually by (N−M−1) times changed bit array and changed bit array. , And a 0-times changing bit array in which all signals are set at initialization and then individually reset by the changing bit array each time batch input is performed. .

The number of state changes of the external device corresponding to a bit which is "1" in the change bit array is N or more times. Similarly, in the change bit arrangement of (N−M) times or more and the change bit arrangement of 0 times, the number of state changes of the external device corresponding to the bit of “1” is (N−M) times and 0 times, respectively. .

[0009]

The change bit array representing the change of the ON / OFF signal is used to increment the change bit array for N times or more, the bit array for (N−M) times or more, and the change bit array for 0 times by a logical operation. Since the on / off signals are processed collectively, the circuit configuration can be reduced in size and the calculation can be performed at high speed.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a monitoring device showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of a data processing unit. The embodiment described below is a case where N in claim 1 is "2" and M = 1.

In FIG. 1, a monitoring device 1 includes an input unit 2 and
It has a zero-time variable output unit 3, a one-time variable output unit 4, a two or more-time variable output unit 5, and a data processing unit 6, and the input unit 2 has an on-off input signal 1 to an on-off input signal 16 Up to 16 ON / OFF signals are input collectively. Each on / off signal is
The state of the corresponding external device (for example, ON / OFF of the breaker) is shown.

The 0-time variable output section 4 outputs an on-off output signal 1 to an on-off output signal 16, the one-time variable output section 4 outputs a signal from an on-off output signal 17 to an on-off output signal 32, and more than twice. The status change output unit 5 converts the code of the 16-bit on / off signal and outputs the data to the communication line, and the data processing unit 6 includes the input unit 1 and the zero-time status change output unit 3, the once-time status change output unit 4, twice. The above is connected to the state change output unit 5.

The output signal from the zero-time change output section 3 indicates an external device whose number of times of change is zero. For example, if the ON / OFF output signal 1 is “1”, it means that the number of state changes of the external device that has output the ON / OFF input signal 1 is 0. In this specification, setting a signal to “1” is referred to as “set” as appropriate, and setting it to “0” is referred to as “reset” as appropriate.

The one-time change output section 4 indicates an external device having one change in the number of times. For example, if the on / off output signal 18 is "1", the number of times of the change of the external device which has output the on / off input signal 2 is indicated. Means once. If the output of the status change output unit 5 is 2 or more, the number of status changes of the corresponding external device is 2 or more. The output of the shape change output unit 5 twice or more is transmitted through the communication line, but may be output in the same manner as the output change unit 3 of zero time and the change output unit 4 of one or more times.

As shown in FIG. 2, the data processing unit 6 includes a current input bit register 11, a previous input bit 12, a changed bit register 13, a two or more times changed bit register 14, and a once changed bits. Register 1
It has a 5,0-fold bit register 16. Also,
As operation units, an input operation unit 21, a copy operation unit 22, a comparison operation unit 23, a first signal set operation unit 24, a second signal set operation unit 25, a first signal reset operation unit 26,
2nd signal reset operation unit 27, 1st output operation unit 2
8, a second output calculator 29, and a third output calculator 30.

Next, the operation of the embodiment will be described. When the initialization signal 31 is activated, the input operation unit 21 collectively receives the ON / OFF signals from the input unit 2 and stores the ON / OFF signals in the input bit register 11 this time. All the signals of the bit register 15 are reset, and all the signals of the zero-fold bit register are set.

Thereafter, the following data processing is sequentially performed at each sampling timing. First, the copy operation unit 22
Copies the contents of the current input bit register 11 to the previous input bit register 12, the input arithmetic unit 21 collectively receives the on / off signals from the input unit 2, stores it in the current input bit register 11, and the comparison arithmetic unit 23 inputs the current input bit register 11. The value of the exclusive OR of the content of the bit register 11 and the content of the previous input bit register 12 is stored in the change bit register 13. That is, in the change bit register 13, “1” is set to a bit whose current input signal is different from the previous input signal.

Next, the first signal set operation unit 24 calculates the contents of the one-time change bit register 15 and the change bit register 13
Is calculated, and the value of the logical sum of the result and the content of the bit change register 14 more than once is stored in the bit change register 14 more than once.

Next, the first signal reset calculator 26 negates the contents of the change bit register 13 and stores the logical product of the change bit register 15 in the change bit register 1.
5 is stored. Next, the second signal set calculator 25 stores the contents of the 0-bit change bit register 16 and the change bit register 1.
3 and the one-time variable bit register 15
Is stored in the once-variable bit register 15.

Further, the second signal reset calculator 27 calculates the negation of the contents of the change bit register 13 and the logical product value of the zero-time change bit register 16 to obtain the zero-time change bit register 1.
6 is stored.

Finally, the first output calculator 28, the second output calculator 29, and the third output calculator 30 collectively output on / off signals to the output units 5, 4, and 3, respectively.

As described above, an output of “1” in the output signal of the zero-time change output unit 3 indicates that the change is zero, and the output signal of the one-time change output unit 4 indicates “0”. “1” indicates that the shape change is performed once, and the output signal of the twice-change output unit 5 indicates that “1” indicates that the shape change is performed twice or more. Therefore, by referring to these output units, it is possible to immediately grasp the number of state changes and take appropriate measures. According to this device, quick count processing can be performed with a small-scale circuit configuration.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a second embodiment. In this embodiment, the data processing unit 6 of the first embodiment is configured using a computer (indicated by 60 in FIG. 3). In addition,
3, the same components as those in FIG. 2 are denoted by the same reference numerals.

In FIG. 3, reference numeral 61 denotes a central processing unit (CP
U), which corresponds to the arithmetic units 21 to 27 of the first embodiment. A storage unit 62 stores programs / data, and stores a bit array corresponding to the bit registers 11 to 16 of the first embodiment. That is, in the storage unit 62, six bit arrays of a current input bit array, a previous input bit array, a changed bit array, a two or more changed bit array, a one-time changed bit array, and a zero-time changed bit array are set. Have been. 63 is an input control unit for connecting the input unit 2 to the data bus 67, and 64 to 66 are output control units for connecting each output unit to the data bus 67.

Next, the operation of the second embodiment will be described with reference to the flowcharts of FIGS. First, the central processing unit 61
Check whether the initialization signal 31 has been activated (40
1), after activation, a reset process is performed (402). If it is not activated, it is checked whether it is the sampling timing of the input signal (403), and if it is the sampling timing, the counting process is performed (404).

FIG. 5 shows a reset processing subroutine. In the reset processing, first, an on / off signal is input from the input unit 2 and is set in the present input bit array in the storage unit 62 (501). Then, all bits of the bit change array are reset twice (502), all bits of the bit change bit array are reset (503), and all bits of the bit change bit array are set (504).

FIG. 6 shows a count processing subroutine. After the above reset processing, the present input bit array is copied to the previous input bit array (601), and an on / off signal is input from the input unit 2 to the current input bit array. It is set (602). Next, the exclusive OR of the current input bit array and the previous input bit array is set in the change bit array (60).
3). Next, the logical product of the one-time changing bit array and the changing bit array and the logical sum of the two or more changing bit arrays are set to the two or more changing bit arrays (604). Then, the logical product of the negation of the changing bit array and the one-time changing bit array is set to a one-time changing bit array (605), and the logical product of the zero-time changing bit array and the changing bit array is set to The logical sum with the variable bit array is set to a one-time variable bit array (60
6). Subsequently, the logical product of the negation of the changing bit array and the 0-times changing bit array is set to the 0-times bit array (607).

Next, the zero-time variable bit array is output to the zero-time variable output unit 3 (608), and the one-time variable bit array is output to the one-time variable output unit 4 (609). The state change bit array is output to the state change output unit 5 twice or more (610).

By the above operation, the data of the number of times of state change of 0 times, 1 time, 2 times or more is obtained from each of the output units 3, 4, 5 respectively.

In the above embodiment, the number of state changes is 0, 1
Data processing was performed twice or more times (N = 2,
M = 1), but it is needless to say that desired state change frequency data can be obtained.

[0031]

As described above, according to the present invention,
Since the data processing unit collectively performs the count operation on the on / off signals, a state change counter circuit for each on / off signal is not required as hardware. Further, since the algorithm of the data processing unit is simplified, the processing time is shortened, and the counting process can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a monitoring device according to the present invention.

FIG. 2 is a block diagram illustrating a circuit configuration of a data processing unit in FIG. 1;

FIG. 3 is a block diagram of a data processing unit according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the second embodiment.

FIG. 5 is a flowchart showing the contents of a reset process of FIG. 4;

FIG. 6 is a flowchart showing the contents of a count process of FIG. 4;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 monitoring device 2 input unit 3 0-time change output unit 4 1-time change output unit 5 1 or more-time change output unit 6 data processing unit

Claims (1)

(57) [Claims] 1. An input unit for repeatedly inputting a plurality of on / off signals collectively; and 0, 1 time,. . . ,
An output unit that collectively outputs an on-off signal indicating a signal change of (N-1) times and N times or more, and a data processing unit that processes data input collectively from the input unit and sends data to the output unit The data processing unit comprises: a current input bit array for storing on / off signals input collectively this time; a previous input bit array for storing on / off signals input collectively last time; and a current batch input and a previous batch input. A change bit array representing a signal change for each bit by comparison, and all signals are reset at initialization, and thereafter, each time a batch input is made, the signal is individually set by the change bit array (N-1) times and the change bit array. Bit array with more than one change, M is 1, 2,. . . , N−1, all signals are reset at the time of initialization, and thereafter, each time a batch input is performed, the signals are first individually reset by a changed bit array, and then individually by (N−M−1) times changed bit array and changed bit array. (N-M) times changing bit array, which is set as a signal, and a 0 times changing bit array, which is set all signals at initialization and then individually reset by the changing bit array each time a batch input is performed. A monitoring device characterized by the above-mentioned.