JP2734565B2 - Delay circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly, to a continuously variable delay circuit formed on a semiconductor used for an LSI or the like.

[Prior art] In digital circuits or limiter amplifier circuits,
In some cases, a delay circuit is required to match the timing of the signal. The conventional method is to use NA as shown in Fig. 12.
Some ND gates 1 are connected in series, and the amount of delay is adjusted by changing the number.

[Problems to be solved by the invention]

The conventional delay circuit described above has a fixed delay amount, and can take only a value of the delay amount that is an integral multiple of the basic delay time. Further, there is a disadvantage that adjustment cannot be performed when the delay amount changes due to process variation or the like. When used in a communication device or the like, it is sometimes required to make the delay time variable in accordance with the state of the transmission path, and the conventional method cannot cope with the delay time.

[Means for solving the problem]

The delay time compensation circuit of the present invention is formed on a semiconductor,
A delay circuit having a delay element insertion loss compensation circuit, wherein: (A) a resistive element formed on the semiconductor epi layer; (B) an epi layer for applying a reverse bias to a PN junction between the resistive element and the epi layer A variable voltage source connected between the electrode and the ground; and (C) the resistance element includes the insertion loss compensation circuit connected to an input side (or an output side).

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The transistor 1, the resistor 2, and the voltage source 3 are constituted by a grounded emitter amplifier circuit, and a signal is input from a terminal a and output from a terminal b.

The resistance element 2 used here is of a type in which a resistance and insulation between the epi layers are obtained by applying a PN junction reverse bias voltage such as a diffusion resistance, an ion implantation resistance or a pinch resistance formed on a semiconductor between the resistance and the epi layer. Of
The schematic structures of these resistors are respectively shown in FIGS.
As shown in FIG.

The electrical equivalent circuit of these resistance elements 1 is shown in FIG. The PN junction indicated by the diode 2 has a parasitic capacitance Cj in a reverse-biased state, and an equivalent circuit of the AC characteristic is shown in FIG.

The value of Cj depends on the reverse bias voltage applied to the PN junction, and its characteristics generally have the characteristics shown in FIG. The time constant τ of this resistance element is expressed as τ = CjR / 2. Here, R is the resistance value of the resistance element.

The value of the time constant τ can be changed by the reverse bias voltage of the PN junction using the above-described voltage-dependent characteristic of Cj. That is, τ decreases as the reverse bias voltage increases, and τ increases as the reverse bias voltage decreases. This resistance element is
When used in the emitter grounded amplification seaway shown in the figure,
The amount of delay in the rise and fall times of the signal depends on the value of τ.
It changes as shown in the figure.

As described above, the delay time of the input / output signal can be adjusted by changing the voltage source voltage connected to the epi layer electrode and controlling the reverse bias voltage of the PN junction of the resistance element.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
In the case of a grounded-base amplifier circuit in which a signal is input from an emitter (terminal a) and output from a collector (terminal b),
As in the case of FIG. 1, the input / output delay time can be controlled by the voltage applied to the epi layer electrode.

3 (a) and 3 (b) are circuit diagrams showing a third embodiment of the present invention, in which a signal is input from the base side (terminal a),
In the case of an emitter follower circuit that outputs from the emitter (terminal b), here, the signal input from the terminal a is delayed by the resistance value of the resistance element 2 inserted between the terminal and the base and the parasitic capacitance Cj thereof. The signal is input to the transistor base and output from the emitter. Therefore, also in this case, the input / output delay time can be controlled by the voltage applied to the epi layer electrode.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.
In the case of a differential amplifier circuit in which a signal is input between the bases (between terminals a1 and a2) and output from the collectors (terminals b1 and b2), the voltage applied to the epi-layer electrode is the same as in FIG. Thus, the input / output delay time can be controlled.

In addition to the above-described first to fourth embodiments, it is conceivable that the delay time compensating circuits are connected in multiple stages in various combinations to widen the range in which the delay time can be compensated.

〔The invention's effect〕

As described above, the present invention has an effect that the input / output signal delay time can be continuously changed by controlling the potential of the epi layer electrode.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIGS.
(B) is a circuit diagram showing a third embodiment of the present invention, FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention, FIG. 5 is a cross-sectional view showing a structure of a diffusion resistor, and FIG. Is a sectional view showing the structure of the ion implantation resistor, FIG. 7 is a sectional view showing the structure of the pinch resistor, FIG. 8 is an electrical equivalent circuit diagram of the resistance element (when the junction is represented by a diode), and FIG. Is the electrical equivalent circuit diagram of the resistance element (when the junction is represented by a capacitor).
FIG. 10 is a graph showing the reverse bias voltage dependence of the PN junction capacitance, FIG. 11 is an input / output voltage waveform diagram of the circuit of the present invention, and FIG.
FIG. 1 is a circuit diagram showing an example of the related art. 1 ... transistor, 2 ... resistance element, 3 ... voltage source,
4 ... voltage source (variable), a ... input terminal, b ... output terminal, c ... epilayer electrode.

Claims (1)

(57) [Claims] 1. A delay circuit formed on a semiconductor and having a delay element insertion loss compensation circuit, comprising: (A) a resistance element formed on an epi layer of the semiconductor; (B) a resistance element and the epi layer A variable voltage source connected between the epi-layer electrode and the ground for applying a reverse bias to the PN junction of (c), wherein the resistance element is connected to an input side (or an output side); A delay circuit comprising: