JP2734330B2 - Leakage current defect detection method for CMOS logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a defect in a CMOS logic circuit, and more particularly to a method for detecting an abnormal leak current.

[0002]

2. Description of the Related Art In general, CMOS circuits are widely used in the information industry and OA equipment to consumer equipment because of their low current consumption when driven. Therefore, in order to improve the reliability of the CMOS circuit, a leakage current is strictly tested in a CMOS-LSI test. Usually, a sample (IC) showing an abnormal value of the leakage current is accompanied by a defect in the logical operation, and is therefore removed by a function test of the logical operation. However, some of the defective products have a problem in which the leakage current shows an abnormal value although the logical operation is normal.

In measuring the leakage current of a conventional CMOS logic circuit, an LS called a function pattern (FP) is used.
A logic operation test signal pattern input from the input terminal of I is used. This FP is composed of test patterns on the order of thousands to tens of thousands, and depending on the size of the circuit,
The P number varies greatly. More specifically, this FP is a check pattern for determining whether an electric circuit is normal or abnormal based on whether an expected value output from an output terminal is correct when a certain signal group is input from an input terminal of an LSI. Then, the internal circuit is set to a signal propagation state corresponding to the FP. In particular, the check of the leak current measures the value of the current flowing in the signal propagation state of the internal circuit set for the input signal, and when the value is higher than the standard value, it is determined that the current is abnormal.

FIGS. 5A and 5B are a logic circuit diagram for explaining a failure mode in which a conventional logic operation is normal and an abnormal leakage current flows, and a diagram showing its truth value. As shown in FIGS. 5A and 5B, it is assumed that this circuit is a two-input NAND circuit, and that the gate electrode of the transistor T2 is disconnected in this circuit. At this time, the transistor T2 is fixed in a normally-on state. Therefore, from the power supply voltage VDD to the ground GN
The leakage current flowing through D is "L", I
2 occurs when "H" is input. However, the output truth value is "L", and normal logic operation is performed.

For example, assuming that the impedance of each of the transistors T1 to T4 is equal to Z for simple calculation, the output Vout in the above-described input setting state is calculated as follows: Vout = 1 / 3.VDD. However, the output truth value at the output terminal O1 is "L".

[0006] Even if the gate electrode of the transistor T1 is disconnected, a leak current occurs, and the output is normal as in the case of the transistor T2.

FIG. 6 is a diagram showing a check characteristic of the FP in FIG. As shown in FIG. 6, a conventional FP comprises a test program 1 (hereinafter, referred to as an area 1) and a test program 2
(Hereinafter, referred to as area 2) and test program 3 (hereinafter, referred to as area 2).
(Referred to as region 3). First,
Area 1 is an area where a signal is input from an input terminal to reset and initialize the entire electric circuit. At this stage, since the internal logic circuit is forcibly set to the state where the operation starts, the output of each FP is undefined. Therefore, here, the expected output value is not set for each FP. Also,
Simultaneous ON to internal logic circuit to force input signal
Setting the state may cause a leak current, but this leak current is ignored. Next, region 2,
Area 3 is an area in which an expected value of an output is checked while a signal is input from an input terminal to the internal logic circuit in which the operation start state is set in the above-described area 1 to perform a logical operation. The area 2 is an area for inputting a simple input signal and roughly checking whether or not the circuit function of the entire electric circuit is normal. If the general check is passed, the process moves to the area 3 and the internal logic circuit is checked in detail. For this reason,
The number of test patterns in the area 3 is several hundred to several thousand times the number of test patterns in the area 2. However, this method saves test time because the detailed circuit operation is checked after the rough circuit operation is checked.

In FIG. 6, the horizontal axis represents the FP number, and the vertical axis represents the gate count rate checked for each FP. That is, in checking for each FP in the area 2 and the area 3, the count number of the gates constituting the internal logic circuit is expressed as a percentage. In short, looking at the signal output from the input terminal through the gate of the internal logic circuit, the input to the gate is "H" or "H".
The check count number is halved because one signal of L level is applied.For example, in a MOS inverter circuit including a pair of P-channel transistors and N-channel transistors, a signal of "H" level is applied to the inverter input terminal. At this time, the N-channel transistor is turned on and the P-channel transistor is turned off, so that the count number for one inverter circuit at that time is halved.

[0009] An actual basic logic circuit is composed of a multi-stage series shape or a multi-parallel shape of transistors, and a mixture of these shapes is mixed. Therefore, the number of check counts for the signal input to the basic logic circuit is further reduced, and is usually about 35%. Therefore, the count number of the internal logic circuit checked for each FP hardly changes and is constant at about 35%.

As described above, conventionally, the total F
For P, abnormal leak current of the internal logic circuit is detected.

The actual detection of abnormal leakage current is performed while the FP is running using an LSI tester, but by detecting the current flowing from the power supply pin VDD to the ground pin GND in a stable operation state (static operation state). .
Moreover, the measurement by detecting such a leak current is L
After the FP signal is input to the input terminal of the SI, the signal must propagate until it propagates to the entire internal logic circuit and the logic of each circuit settles down. That is, in the logic transition process, an accurate through-current measurement cannot be performed because an alternating through current flows from VDD to GND.
Normally, each FP requires a standby time of 1 ms or more after being input.

[0012]

In the above-described conventional method for detecting an abnormal leak current, the abnormal leak current is detected for all FPs, so that a defective product can be detected and removed, but the measurement time is greatly reduced. And is not suitable for mass production.

For example, in the conventional measurement for detecting the leak current, the measurement time for each FP requires a standby time of about 1 ms. Therefore, when the measurement is performed by a program including 30,000 patterns, it takes 30 seconds. Requires measurement time.

However, in the test items other than the measurement of the general leak current, since each of the test items is at most 3 seconds or less, the measurement time of 30 seconds is extremely long and is not suitable for mass production. Become.

An object of the present invention is to provide a method of detecting a leak current defect of a CMOS logic circuit suitable for mass production by detecting a leak current defect occurring on the CMOS logic circuit almost completely with a small test pattern. is there.

[0016]

According to the present invention, there is provided a method for detecting a leakage current defect in a CMOS logic circuit, comprising: a first test program for setting initialization and resetting of an electric circuit ; Following the second test program and the second test program for checking the main operation in the operation of the electric <br/> magnetic circuit, for each part circuits constituting the whole of the electric circuit
To check each of the on and off states of the transistor in detail
It has a third logical operation program and a test program for, in the operation test of the CMOS logic circuit,
The detection of the leak current defect is configured to be performed using only the second test program.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a view schematically showing an FP for explaining an embodiment of the present invention. As shown in FIG. 1, this embodiment uses a logic operation program including three consecutive test programs (areas). First, the test program 1 (area 1) is composed of several tens of patterns, and initializes and resets the internal circuit. The test program 2 (area 2) is composed of several tens to one hundred patterns following the area 1. This area 2 roughly checks whether or not the circuit function of the entire electric circuit is normal using a simple input signal. Furthermore, test program 3 (area 3)
Consists of thousands to tens of thousands of patterns following the area 2. This area 3 performs a detailed check of the electric circuit. In this embodiment, the CMO is performed by using only the pattern of the region 2 among these regions.
An operation test of the S logic circuit is performed to detect a leak current defect. That is, in the detection of the abnormal leak current, continuous measurement is performed using the FP in the area 2 after the initialization and reset on the electric circuit are completed.

FIG. 2 is a check characteristic diagram of the FP in FIG. As shown in FIG. 1, in this embodiment, the number of FP is set on the horizontal axis as in the above-described conventional example.
The difference is that the vertical axis indicates the count rate of a gate newly checked for each FP. That is, region 2, region 3
In the case of newly checking a gate for each FP, the count number of the gates constituting the internal logic circuit is expressed as a percentage. Therefore, the number of basic logic circuits newly counted decreases with the progress of FP in the area 2, and the percentage gradually decreases from 35%. This is because in the area 2 it is necessary to roughly check whether the circuit function of the entire electric circuit is normal or not.
As P progresses, the number of basic logic circuits newly counted increases. On the other hand, when the area 3 is entered, the internal circuits are checked in detail. Here, since most of the internal circuits are checked and counted once, the number of basic logic circuits newly counted is extremely small. Become.

FIG. 3 is a graph showing the cumulative characteristics of the characteristics shown in FIG. As shown in FIG. 3, the cumulative characteristic, that is, the number of additions of the newly counted basic logic circuit rapidly increases as soon as the FP shifts to the area 2, so that the ratio (count integration rate) to the whole increases rapidly. Go up. By the end of this region 2, the increasing tendency becomes gentle. Further, when the FP enters the region 3, the saturation becomes almost saturated, and approaches 100% corresponding to the entire basic logic circuit as much as the FP changes.

In short, 90% or more of the logic circuits are counted in the region 2, so that an abnormal leak current in 90% or more of the logic circuits can be detected.

FIG. 4 is a diagram showing the relationship between the FP and the leakage current value in FIG. 2 or FIG. As shown in FIG. 4, the check of the leak current value in the area 2 is based on the assumption that the logical operation test patterns 4a and 5 exceed the standard value. Of these logical operation test patterns 4a and 5, the logical operation test pattern 4a is reproduced in the logical operation test pattern 4b in the area 3. In short, the logical operation test pattern (FP) 4b in the area 3 is the FP detected in the area 2 because most of the total count of the basic circuit in FIG.
This corresponds to the same leak current generation location corresponding to any of the numbers.

[0022]

As described above, the present invention relates to a CMOS.
An abnormal leak current is detected using only the second area where 90% or more of the logic circuits of the logic circuit are counted, and the number of function patterns is as small as several tens to about one hundred. Therefore, a circuit or an element having an IDD leak current can be efficiently removed, which is effective for mass production.

Further, since the measurement time of the present invention uses about one hundred patterns in the second area, if the measurement time for each function pattern requires a standby time of 1 mS, 1 mS × 100 (p) = 0 It has the effect of being performed in a short time of 1 second. Furthermore, even if the present invention increases the number of test patterns due to the increase in scale,
There is an effect that the leakage current measurement pattern does not become long, and the leakage current defective product can be reliably selected.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating an FP for explaining an embodiment of the present invention.

FIG. 2 is a check characteristic diagram of the FP in FIG. 1;

FIG. 3 is a cumulative characteristic diagram of the characteristics in FIG.

FIG. 4 is a diagram showing a relationship between FP and a leak current value in FIG. 2 or FIG. 3;

FIG. 5 is a diagram showing a logic circuit and a truth value for explaining a conventional failure mode in which a logic operation is normal and an abnormal leakage current flows.

FIG. 6 is a check characteristic diagram of the FP in FIG. 5;

[Explanation of symbols]

 1-3 Test program (area)

Claims (1)

(57) [Claims] An operation of the electric circuit follows a first test program for setting initialization and reset of the electric circuit and the first test program.
Wherein the second test program for checking the Chi main operation following the second test program, each of the transistors of each part circuits constituting the whole of the electric circuit
A logic operation program including a third test program for checking each ON / OFF in detail ;
In the operation test of MOS logic circuit,
For detection, only the second test program is used.
A method of detecting a leakage current defect in a CMOS logic circuit.