JP2732533B2 - Asynchronous control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A first aspect of the present invention relates to an asynchronous control circuit that outputs an asynchronous signal to an asynchronous signal transmission circuit, with the object of providing an asynchronous control circuit that operates normally without deteriorating performance. An asynchronous control circuit that operates in synchronization with a clock and sends an asynchronous signal to an asynchronous signal transmission circuit that operates in synchronization with a second clock having a cycle longer than the cycle of the first clock; Means for dividing a trigger signal that is continuously input in synchronization with the clock at least at intervals longer than one cycle of the second clock and outputting the divided signal as a second trigger signal; Means for outputting to the asynchronous signal transmission circuit an asynchronous signal whose inversion timing has been extended only during the interval.

The present invention relates to an asynchronous control circuit that outputs an asynchronous signal to an asynchronous signal transmission circuit.

In an information processing apparatus, asynchronous control is frequently performed by an external device of a channel, a common bus of a system and an asynchronous processor. Therefore, there is a demand for an asynchronous control circuit capable of controlling the speed even if the asynchronous trigger from the asynchronous control circuit is generated n times in one cycle of the clock synchronized with the other control unit.

[Prior Art] As a conventional asynchronous signal transmission circuit, for example, there is one as shown in FIG.

In FIG. 6, 1 is an asynchronous trigger (hereinafter, TRGI).
And a T-flip-flop that outputs a signal (hereinafter, SSPST) by input of a clock (hereinafter, ICLK) synchronized with TRGI, and 2, 3, and 4 are clocks (hereinafter, SCLK) synchronized with other control units. And a D-flip-flop that outputs a signal (hereinafter, SSPSD), a signal (SSPSE), and a signal (SSPSF), respectively, according to the SSPST input from the T-flip-flop 1, and 5 is the SSPSE from the D-flip-flop 3. D-
This is an exclusive OR circuit that outputs a trigger signal (hereinafter, TRGS) in response to SSPSF input from the flip-flop 4.

Next, FIGS. 7 to 9 show time charts of the asynchronous signal transmission circuit.

In FIG. 7, when TRGI is turned on, SSPST output from T-flip-flop 1 is inverted in the next cycle. This SSPST is synchronized with SCLK, and SSPSE and SSPSF are created by the D-flip-flops 3 and 4. And SSPSE and SSPSF in exclusive OR circuit 5
The TRGS to the interface section is calculated by taking the derivative of

Next, FIG. 8 shows a case where TRGI is turned on four times consecutively.

In this case, since the relationship between the period of SCLK (hereinafter, τs) and the period of ICLK (hereinafter, τi) is τs ≦ τi, TRGS
Is turned on four times normally.

Next, FIG. 9 also shows a case where TRGI is turned on four times consecutively.

In this case, since τs> τi, TRGI is 4
TRGS is turned on twice while it is turned on four times.
Do not turn on.

[Problems to be Solved by the Invention] As described above, in the conventional asynchronous signal transmission circuit, when TRGI from the asynchronous control circuit occurs n times in 1τs, it does not operate properly unless τi ≧ τs. . In general, τi <τs, so that there is a problem that a TRGI that occurs n times in 1τs does not operate normally.

If the operation is still unavoidable, the cycle of the asynchronous control circuit must be delayed so that τi ≧ τs. In this case, there is a problem that the performance is reduced.

The present invention has been made in view of such conventional problems, and has as its object to provide an asynchronous control circuit that operates normally without deteriorating performance.

[Means for Solving the Problems] FIGS. 1A and 1B are explanatory diagrams of the principle of the present invention.

The present invention relates to an asynchronous control circuit that operates in synchronization with a first clock and sends an asynchronous signal to an asynchronous signal transmission circuit that operates in synchronization with a second clock having a period longer than the period of the first clock. Means for dividing a trigger signal continuously inputted in synchronization with the first clock at intervals longer than at least one cycle of the second clock, and outputting the divided signal as a second trigger signal; Means for outputting, to the asynchronous signal transmission circuit, an asynchronous signal whose inversion timing has been extended for the interval based on a second trigger signal.

[Operation] The present invention relates to an asynchronous control circuit that is provided between devices that operate with different clocks and that transmits an asynchronous signal between the devices. Means for dividing the input trigger signal (TRGI) into trigger signals (TRGI ') having an interval longer than at least τs (> τi), and at least τs (> τi) based on the divided trigger signal (TRGI') Means for outputting a signal (SSPST) having the same phase during the period, and for outputting a signal (SSPST) having the same phase during the τi (<τs) period as shown in FIG. An object of the present invention is to solve the problem of the prior art in which a trigger signal (TRGI) continuously input to a device operating with a clock having a period of τi cannot be transmitted to a device operating with a clock having a period of τs.

In the present invention, as shown in FIG.
When one asynchronous trigger has occurred, the asynchronous trigger of 1τi is extended by the asynchronous trigger extension circuit and transmitted to the synchronization circuit.

When TRGI is turned on, SSPST is inverted, synchronized with SCLK, differentiated, and set as TRGS. In the figure, TRGI is continuous four times, but the inversion timing of SSPST, which is the input signal of the synchronization circuit, is controlled to be 3τi later. Here, TRGI is extended to 3τi, but it goes without saying that in this example, it is just 3τi, and any τi may be used. In this example, the condition is extended to 3τi, so that the condition of τi ≧ 1 / 3τs is satisfied. That is, 1
It means that normal operation can be performed if the asynchronous trigger generated during τs is up to three times. In the figure, the SSPST inversion by the second TRGI is 3τi after the timing of the SSPST inversion by the first TRGI. 3rd TRGI, 4th TR
Similarly, for GI, SSPST is inverted 3τi after the previous SSPST inversion.

Therefore, by turning on TRGI four consecutive times, TRGS
Is turned on four times. In this way, without delaying the cycle of the asynchronous control circuit to the cycle of the other control unit,
Asynchronous triggers can be transmitted, and the performance of the system can be improved.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

 2 to 5 are views showing an embodiment of the present invention.

First, the configuration will be described. In FIG. 3, reference numeral 11 denotes a quaternary counter which counts up each time an asynchronous trigger (hereinafter, TRGI) is turned on. ICLK) is input to T-flip-flops 12 and 13 and an AND circuit 14 to generate respective signals (hereinafter, VSL0 and VSL1).

Reference numeral 15 denotes a holding circuit for holding TRGI.
Is composed of AND circuits 16 to 19 to which VSL0 and VSL1 are input and JK flips 20 to 23, and each signal (hereinafter, VI0, VI1, VI2, VI
3) Make.

Next, in FIG. 4, reference numeral 24 denotes a circuit for generating reset signals of VI0, VI1, VI2, and VI3.
The flip-flops 25 and 26 and AND circuits 27 and 28 to 31 output respective signals (hereinafter, VIR0, VIR1, VIR2 and VIR3). A quaternary counter is formed by the flip-flops 25 and 26 and the AND circuit 27, and outputs each signal (hereinafter, WWT, WWTT).

Next, in FIG. 2, reference numeral 32 denotes one cycle of ICLK (hereinafter, τ
This is a circuit for extending the TRGI of i).
Are composed of D-flip-flops 33 to 35 and generate respective signals (hereinafter, WW0, WW1, WW2).

Reference numeral 36 denotes an asynchronous trigger (hereinafter, TR) extended by each input of VI0, VI1, VI2, VI3, WW2, VIR0, VIR1, VIR2, and VIR3.
GI ′), and this circuit 36 is an AND circuit 37
To 43 and OR circuits 44A to 44C.

Reference numeral 45 denotes a T-flip-flop that outputs an inverted signal (hereinafter, SSPST) according to the input of TRGI 'and ICLK.

Accordingly, the circuits 11, 15, 24, 32, 36, and 45 as a whole constitute an asynchronous trigger stretching circuit 46 that stretches TRGI and outputs TRGI '.

Reference numeral 47 denotes D-flip-flops 48 and 49, which are synchronized with the SSPST and other control units (hereinafter referred to as S
CLK) input, each synchronization signal (SSPSD and SSPS)
E) is a synchronizing circuit for outputting, 50 is a D-flip-flop 5
1 and the exclusive OR circuit 52.
This is a differentiating circuit that outputs a trigger signal (hereinafter, TRGS) in response to SCLK input. In this embodiment, the circuit for extending TRGI 'has four stages, and the TRGI of 1τi is extended after 3τi.

The means for outputting the second trigger signal in the claims is constituted by the circuits 11, 15, 24, 32 and 36, and the means for outputting the asynchronous signal is constituted by the T-flip-flop 45.

 Next, the operation will be described.

FIG. 5 is a time chart for explaining the operation. This time chart shows a case where TRGI occurs four times consecutively.

In FIG. 5, first, when TRGI is turned on for the first time, VI0, VI1, VI2, and VI3 are all "0", and thus TRGI becomes TRGI 'as it is. When TRGI 'is turned on, SSPST is inverted in the next cycle, SSPSD is turned on by the input of SCLK, SSPSE is turned on in the next SCLK, thereby TRGS is turned on, and SSPSF is turned on in the next SCLK, TRGS turns off. Thus, the first TRGS is output. Also, TRG
When I 'is turned on, WW0, WW1, WW2 are turned on one after another. In the next cycle after the TRGI turns on, VI0 becomes '1' and VSL1 turns on.

After the first TRGI, the second TRGI turns on,
Since VI0 = '1' in that cycle, TRGI 'does not turn on. In the next cycle after the second TRGI is turned on, VI1 becomes "1", VSL0 is turned on, and VSL1 is turned off.

Subsequently, the third TRGI is turned on. In that cycle, VI0 = '1' and VI1 = '1', so TRGI 'is not turned on. VI in the next cycle after the third TRGI is turned on
2 becomes '1' and VSL1 turns on.

Subsequently, TRGI is turned on for the fourth time, and in that cycle, TRGI 'is turned on because WWD is on. TRGI '
When S is turned on, SSPST is inverted in the next cycle, SSPSD is turned off by input of SCLK, SSPSE is turned on by the next SCLK, thereby TRGS is turned on, SPSSF is turned off in the next SCLK, TRGS turns off. This is the second TR
GS is output. When TRGI 'is turned on, WW0, WW1,
WW2 turns on one after another. In the next cycle after the fourth TRGI turns on, VI3 becomes "1" and VSL0 and VSL1 turn off. When the first WW2 turns on, VIR0 turns on,
In the next cycle, VI0 is reset and the quaternary counter that outputs WWTT and WWT counts up.

WW2 is turned on for the second time three cycles after the cycle when TRGI is turned on for the fourth time, and then VI2 ・ ▲ ▼
= '1', TRGI 'is turned on. When TRGI 'is turned on, SSPST is inverted in the next cycle, SSPSD is turned on by the input of SCLK, SSPSE is turned on in the next SCLK, thereby TRGS is turned on, and SSGSF is turned on in the next SCLK. , TRGS turns off. Thus, the third TRGS is output. When TRGI 'is turned on, WW0, WW1, and WW2 are turned on one after another. VIR1 when WW2 is turned on for the third time
Is turned on, VI1 is reset in the next cycle, and the quaternary counter that outputs WWTT and WWT counts up.

Next, when WW2 is turned on for the third time, VI3
Since ▼ = '1', TRGI 'is turned on. When TRGI 'is turned on, SSPST is inverted in the next cycle, SSPSD is turned off by the input of SCLK, SSPSE is turned on in the next SCLK, thereby TRGS is turned on, and SSPSF is turned on in the next SCLK. Turns off and TRGS turns off. This is the 4th TR
GS is output. When TRGI 'is turned on, WW0, WW
1, WW2 turns on one after another. When WW2 is turned on for the third time, VIR2 is turned on, and in the next cycle, VI2 is reset and the quaternary counter that outputs WWTT and WWT counts up.

Next, when WW2 is turned on for the fourth time, TRGI 'is not turned on because there is no condition for turning on TRGI'. The fourth WW
2 turns on, VIR3 turns on, and in the next cycle VI3
Is reset and the quaternary counter that outputs WWTT and WWT counts up.

Thus, TRGS is also turned on four times by turning on TRGI four times in succession. Therefore, the TRGI from the asynchronous control circuit can be transmitted to other control units as TRGS at high speed without lowering the performance.

[Effects of the Invention] As described above, according to the present invention, by extending the asynchronous trigger, the asynchronous trigger is set to 1τ.
Even when n times occur in s, the asynchronous trigger can be transmitted without delaying the cycle of the asynchronous control circuit in accordance with the cycle of the other control unit, and the performance of the system can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (A) and 1 (B) are diagrams for explaining the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 4 is a diagram showing a reset signal generation circuit, FIG. 5 is a time chart, FIG. 6 is a diagram showing a conventional example, and FIGS. 7 to 9 are time charts. In the figure, 11: quaternary counter, 12, 13: T-flip-flop, 14: AND circuit, 15: holding circuit, 16-19: AND circuit, 20-23: JK flip-flop, 24: reset signal generation circuit, 25, 26: T-flip-flop, 27, 28-31: AND circuit, 32: Circuit, 33-35: D-flip-flop, 36: Circuit, 37-43: AND circuit, 44A-44C: OR circuit, 45 : T-flip-flop, 46: asynchronous trigger enlargement circuit, 47: synchronization circuit, 48, 49: D-flip-flop, 50: differentiation circuit, 51: D-flip-flop, 52: exclusive OR circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazuyasu Nonomura 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd.

Claims (1)

(57) [Claims] An asynchronous control circuit that operates in synchronization with a first clock and sends an asynchronous signal to an asynchronous signal transmission circuit that operates in synchronization with a second clock having a period longer than the period of the first clock. Means for dividing a trigger signal continuously input in synchronization with the first clock at intervals longer than at least one cycle of the second clock, and outputting the divided signal as a second trigger signal; Means for outputting, to the asynchronous signal transmission circuit, an asynchronous signal whose inversion timing has been extended by the interval based on the second trigger signal, the asynchronous control circuit comprising: