JP2730532B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an insulated gate (MO) device having a protection diode.
S-type) field-effect transistors.

[0002]

2. Description of the Related Art In a conventional semiconductor device having a protection element, in a gate MOS type field effect transistor, when a gate electrode is excessively charged due to charge-up due to a manufacturing process, a gate oxide film is electrostatically damaged. Problem. As a method for solving this problem, a method in which a diode is connected to the gate electrode and the electric charge charged in the gate electrode is released to the substrate is disclosed in
It is disclosed in 102,564.

FIGS. 5A and 5B are views showing an example of a conventional semiconductor device having a protection element, wherein FIG. 5A is a plan view, and FIG. 5B is an XY cross-sectional view in FIG.

[0005] As shown in FIG.
A P-well 502 is formed on a silicon substrate 501;
A field oxide film 504 for element isolation is formed on the P well 502 with an opening, and a gate oxide film 505 and an N-type diffusion layer 507 are formed in the opening, and a part of the field oxide film 504 is formed. A gate electrode 506 made of, for example, polysilicon is formed on the gate oxide film 505, and a contact hole 509 is formed on the gate electrode 505, the N-type diffusion layer 507, and the field oxide film 504 by a silicon oxide film 508 serving as an interlayer insulating film. An aluminum wiring 510 is formed on the silicon oxide film 508 and in the contact hole 509.

The gate electrode 505 is connected to an N-type diffusion layer 507 via an aluminum wiring 510 formed in a contact hole 509.

Here, the N type diffusion layer 507 and the P well 50
A protection diode is formed by the PN junction with the second.

In the semiconductor device configured as described above, the protection diode formed by the PN junction between N-type diffusion layer 507 and P well 502 against the charge-up caused by the process after aluminum wiring 510 is formed. Functions, and the gate oxide film 505 is protected. At this time, by setting the breakdown voltage of the protection diode lower than the breakdown voltage of the gate oxide film 505, the charged-up electrode can be released without damaging the gate oxide film 505.

[0008]

However, in the conventional semiconductor device as described above, the withstand voltage of the protection diode is set lower than the withstand voltage of the gate oxide film. When a high voltage close to the withstand voltage of the gate oxide film is applied to the gate electrode to measure the characteristics, the protection diode breaks down and the reliability test cannot be performed.

For this reason, Japanese Patent Application Laid-Open No. 4-158578 discloses a technique in which a connection between a transistor and a diode is formed as a fuse, and the fuse is cut by a laser or an electric means before measurement of characteristics. . According to this technique, measurement under a high voltage becomes possible.

However, when the fuse is cut, there is a possibility that the transistor may be physically and electrically damaged, so that there is a problem that the reliability cannot be evaluated correctly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and is capable of performing a reliability test in which a high voltage is applied without damaging a transistor. The purpose is to provide.

[0012]

In order to achieve the above object, the present invention provides a well region formed on a semiconductor substrate,
A gate electrode formed on the well region via a gate insulating film, and a first conductivity type diffusion layer formed on the well region, wherein the gate electrode and the diffusion layer are formed by a wiring layer. In the connected semiconductor device, the well region includes a first conductivity type well region and a second conductivity type well region, and the gate electrode is connected to the second conductivity type well region, and A layer is connected to the well region of the first conductivity type, and the gate electrode and the wiring layer are formed on at least a part of a boundary between the well region of the first conductivity type and the well region of the second conductivity type. It is characterized by being arranged so that light from the outside can reach.

Further, the semiconductor substrate is a silicon substrate.

Further, the silicon substrate and the second conductivity type are P-type, and the first conductivity type is N-type.

Further, the silicon substrate and the first conductivity type are P-type, and the second conductivity type is N-type.

(Operation) In the present invention configured as described above, the well region formed on the semiconductor substrate includes a well region of the first conductivity type and a well region of the second conductivity type. Since the protection diode having a breakdown voltage higher than the breakdown voltage of the film is formed, it is possible to test the transistor using a high voltage while the protection diode is connected. Further, if light reaches the boundary between the well region of the first conductivity type and the well region of the second conductivity type from the outside during the manufacturing process using plasma, a leak current occurs in the depletion layer formed at the boundary. Even if the gate electrode is charged up due to the plasma process, the charge is released to the substrate and damage to the gate oxide film can be prevented.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1A and 1B are diagrams showing a first embodiment of a semiconductor device according to the present invention, wherein FIG. 1A is a plan view, and FIG. It is a Y sectional view.

As shown in FIG. 1, in the present embodiment, a P well 2 and an N well are formed on a P type silicon substrate 1 which is a semiconductor substrate.
A well 3 is formed, and a field oxide film 4 for element isolation is formed on the P well 2 and the N well 3 with an opening at least one of which is located on the N well 3. A gate oxide film 5 serving as a gate insulating film is formed in the upper opening, a high-concentration N-type diffusion layer 7 is formed in the opening above the N well 3, and a part of the field oxide film 4 and the gate oxide film 5 are formed. A gate electrode 6 is formed on the gate electrode 6, the N-type diffusion layer 7, and the field oxide film 4.
A silicon oxide film 8 serving as an interlayer insulating film is formed having a contact hole 9, and an aluminum wiring 10 serving as a wiring layer is formed on the silicon oxide film 8 and in the contact hole 9.

The gate electrode 6 is connected to the N-type diffusion layer 7 through an aluminum wiring 10 formed in the contact hole 9.

Here, the PN of the N well 3 and the P well 2
The junction forms a protection diode.

At this time, on the surface of the semiconductor device, the N well 3 and the P well 2 are so arranged as not to prevent external light from reaching the boundary between the N well 3 and the P well 2.
It is important not to dispose the gate electrode 6 and the aluminum wiring 10 in at least a part of the portion corresponding to the boundary portion between.

In the semiconductor device configured as described above, the protection diode formed by the PN junction between the N well 3 and the P well 2 against the charge-up caused by the plasma process after the aluminum wiring 10 is formed. By functioning, the gate oxide film 5 is protected.

At this time, the concentrations of the N well 3 and the P well 2 are both 1E17 to 3E17 cm ^-3 , and the withstand voltage of the protection diode formed by these becomes 20 V or more. Therefore, the thickness of the gate oxide film 5 is, for example, 15
If it is less than 0 °, the breakdown voltage of the gate oxide film 5 will be exceeded.

However, since plasma emission occurs during the plasma process, if the gate electrode 6 is positively charged, a reverse voltage is applied to the protection diode formed by the N well 3 and the P well 2. Is applied to form a depletion layer at the well boundary.

FIG. 2 is a plan view showing a state where the gate electrode 6 of the semiconductor device shown in FIG. 1 is positively charged up.

Since the impurity concentration distribution at the well boundary is gentle, the width of the depletion layer 14 formed at the boundary between the N well 3 and the P well 2 is the same as that of the N type diffusion layer shown in the conventional example. Since the width is wider than the width of the depletion layer of the protection diode including the well, a large amount of generation / recombination current is generated as a leakage current when irradiated with plasma emission. For this reason, even when the voltage of the gate electrode 6 is increased, the charged voltage is released to the substrate by the leak current generated in a larger amount than in the related art, and the gate oxide film 5 is not damaged.

FIG. 3 shows the voltage-current characteristics of the protection diode formed by the N well 3 and the P well 2 shown in FIG. 1 with and without light irradiation, and the voltage-current of the gate oxide film 5. It is a figure showing a characteristic. The reverse breakdown voltage of the diode is VD, and the breakdown voltage of the gate oxide film is VX.
Indicated by

At the time of characteristic measurement, if light is not irradiated, VX <VD. Therefore, even if a voltage near the withstand voltage of the gate oxide film 5 is applied to the gate electrode wiring 13, the diode has no effect on the measurement. Do not give.

On the other hand, during the etching of the aluminum electrode 10, the plasma light emission is applied, so that the leakage current increases, and the electric charge charged in the gate electrode is released to the substrate to apply a high voltage to the gate oxide film 5. Never.
Thus, it is possible to prevent the gate oxide film 5 from being damaged by charge-up.

In the charge-up during the plasma process, the charge is often positive, and the protection diode shown in this embodiment has an effect of preventing the positive charge from being charged.

Even if the charge-up is negative, since the protection diode operates in the forward direction, the occurrence of the charge-up is prevented regardless of the light irradiation.

Since plasma emission is blocked by a polysilicon electrode, an aluminum wiring, a tungsten wiring, a nitride film, etc., it is necessary not to dispose the gate electrode 6 and the aluminum wiring 10 above the well boundary of the protection diode. . Since the silicon oxide film 8 used in this embodiment transmits light, there is no problem even if the silicon oxide film 8 exists above the well boundary of the protection diode.

(Second Embodiment) As a second embodiment, an example in which the present invention is applied to a P-type transistor formed on a P-type silicon substrate will be described.

FIGS. 4A and 4B are views showing a second embodiment of the semiconductor device of the present invention, wherein FIG. 4A is a plan view, and FIG. 4B is an XY sectional view in FIG.

In this embodiment, as shown in FIG.
N well and P are different from those shown in the embodiment.
The well is replaced with an N-type diffusion layer 7 (FIG. 1).
P), a P-type diffusion layer 115 is formed instead of
Other configurations are the same.

In the present embodiment configured as described above, the protection diode is formed by the P-well 102 and the N-well 103. However, since the P-type silicon substrate 101 is of the P-type, the protection diode is simply formed. The protection diode cannot be formed by the formation method in which the P well and the N well formed in the above embodiment are exchanged.

Therefore, as shown in FIG.
3 has a structure in which the P well 102 is contained.

The above structure is realized by including the P well 102 in the region of the N well 103.
At this time, the single concentration and depth of the N well 103 need to be larger than the single concentration and depth of the P well 102.

For example, if the concentration of the N well 103 alone is 2E
17 cm ^-3 and a depth of 1 μm, whereas P well 1
If the concentration of 02 alone is 1E17 cm ^-3 and the depth is 0.7, a protection diode with a withstand voltage of about 20 V is formed.

In order to form a well under the above conditions, a method of performing ion implantation with different energies a plurality of times may be used. With this configuration, it is possible to relatively easily realize the appropriate distribution of the well impurity concentration while satisfying the transistor characteristics and the element isolation characteristics.

As described above, according to the second embodiment, the present invention can be applied to a P-type transistor formed on a P-type substrate.

Therefore, when used in combination with the one shown in the first embodiment, the N-type and P-type
The type transistor can be protected from charge-up, and the characteristics can be measured at a high voltage.

[0044]

Since the present invention is configured as described above, it has the following effects.

(1) Since the protection diode is composed of a well junction, a test in which a high voltage is applied to the gate electrode without disconnecting the protection diode after the transistor is manufactured can be performed.

Thus, it is possible to prevent the transistor from being damaged when disconnecting the protection diode.

(2) Since the protection diode is composed of the junction of the N well and the P well, the impurity concentration distribution at the well boundary is gentle, and the generation and recombination of carriers in the well depletion layer is caused by plasma. A large leak current is generated by plasma emission during the process.

As a result, even if the gate electrode is charged due to the process, the charge is released to the substrate and damage to the gate insulating film can be prevented.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a first embodiment of a semiconductor device of the present invention, wherein FIG. 1A is a plan view, and FIG.
It is -Y sectional drawing.

FIG. 2 is a plan view showing a state where a gate electrode of the semiconductor device shown in FIG. 1 is positively charged up.

FIG. 3 shows voltage-current characteristics of a protection diode formed by an N well and a P well shown in FIG. 1 with and without light irradiation, and voltage-current characteristics of a gate oxide film. FIG.

FIGS. 4A and 4B are diagrams showing a second embodiment of the semiconductor device of the present invention, wherein FIG. 4A is a plan view, and FIG.
It is -Y sectional drawing.

5A and 5B are diagrams illustrating a configuration example of a semiconductor device having a conventional protection element, wherein FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along the line XY in FIG.

[Explanation of symbols]

 1,101 P-type silicon substrate 2,102 P-well 3,103 N-well 4,104 field oxide film 5,105 gate oxide film 6,106 gate electrode 7,107 N-type diffusion layer 8,108 silicon oxide film 9,109 Contact hole 10, 110 Aluminum wiring 11, 111 Source electrode 12, 112 Drain electrode 13, 113 Gate electrode wiring 14 Depletion layer

Claims (4)

(57) [Claims] A well region formed on a semiconductor substrate; a gate electrode formed on the well region via a gate insulating film; a first conductivity type diffusion layer formed on the well region; A semiconductor device in which the gate electrode and the diffusion layer are connected by a wiring layer, wherein the well region comprises a first conductivity type well region and a second conductivity type well region; Is connected to the second conductivity type well region, the diffusion layer is connected to the first conductivity type well region, and the gate electrode and the wiring layer are connected to the first conductivity type well region. A semiconductor device provided so that external light reaches at least a part of a boundary portion with a well region of a second conductivity type. 2. The semiconductor device according to claim 1, wherein said semiconductor substrate is a silicon substrate. 3. The semiconductor device according to claim 2, wherein said silicon substrate and said second conductivity type are P-type, and said first conductivity type is N-type. 4. The semiconductor device according to claim 2, wherein said silicon substrate and said first conductivity type are P-type, and said second conductivity type is N-type.