JP2715468B2 - Digital signal playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal reproducing apparatus such as a digital VTR.

[Conventional technology]

When recording a digital signal, for example, a digitized video signal, it is common to divide the digital video signal into a plurality of channels and record it as a multi-track by the same number of heads. This is because the recording bit rate can be reduced by using multi-channels.

In a digital signal reproducing apparatus recorded as a multi-channel as described above, the outputs of a plurality of heads are supplied to a TBC circuit through a reproducing amplifier and a reproducing process circuit, respectively. Error correction is being performed. Then, the signal subjected to the time axis error correction is stored in the corresponding memory block with the data from each one track, and the data from the plurality of memory blocks is converted into the original single channel data by the multiplexer.

By the way, conventionally, an interchanger is provided between a TBC circuit and a plurality of memory blocks in consideration of special reproduction such as high-speed reproduction and slow reproduction. That is, at the time of trick play, the head scans across a plurality of tracks, so that each head output contains data from tracks of other channels. The interchanger detects an ID signal (track number, data block address, etc.) of each head output, and distributes data to corresponding memory blocks in accordance with the ID signal (for example, see Japanese Patent Application Laid-Open No. 57-55515). And JP-A-60-69861 and JP-A-62-234476.

[Problems to be solved by the invention]

The interchanger is a circuit that arranges, in a manner similar to a traffic block, which memory block is to be used to write data that simultaneously arrives from the TBC circuits for the number of channels, and requires a memory and has a complicated circuit configuration.

An object of the present invention is to provide a digital signal reproducing apparatus which does not require the use of a complicated circuit such as the interchanger.

[Means for solving the problem]

According to the present invention, a reproduced digital signal of a plurality of channels reproduced at the same time by a plurality of heads is stored in a plurality of first memories having a capacity capable of storing data reproduced in one scan by a clock signal synchronized with the reproduced digital signal. The data stored in each of the plurality of heads is read out by the reference clock signal within one rotation cycle of the plurality of heads, and the channel of the reproduced digital signal is stored. The multiplexed data is supplied to an address detection circuit, and the multiplexed data is written to a second memory in accordance with the address detected by the address detection circuit. Digital signal reproducing device.

[Action]

When data is read from the first memory, data is multiplexed into data of a smaller number of channels than the original number of channels, so that it is not necessary to provide address detection circuits for the number of original channels, and the configuration is simplified.

〔Example〕

Hereinafter, an embodiment of a digital signal reproducing apparatus according to the present invention will be described with reference to the drawings, taking as an example a case where the present invention is applied to a digital VTR reproducing system.

FIG. 1 shows an example of the configuration of a reproduction system of a digital VTR, and FIG. 2 shows an example of the configuration of a recording system.

 First, the configuration of the recording system shown in FIG. 2 will be described.

In FIG. 2, red (R), green (G) and blue (B) signals of three primary color signals are supplied to input terminals denoted by 1, 2, and 3, respectively. The A / D converter shown at 4 converts the three primary color signals into digital signals. The luminance signal (Y) and the color difference signal (U,
V) is formed. The luminance signal and the color difference signal are represented by (Y:
U: V) has a sampling frequency of (4: 4: 4).

Since the digital component signal of (4: 4: 4) has a large amount of information, it is converted by the rate conversion circuit 6 into a time-division multiplexed signal 7 at a sampling rate of (3: 1: 0). That is, the sampling frequency of the luminance signal is (3/4), the sampling frequency of the chrominance signal is (1/4), and the U and V of the chrominance signal are line-sequential signals. The output signal 7 of the rate conversion circuit 6 is supplied to a blocking circuit 8, and the signal in the order of television scanning is converted into a signal in the order of blocks.

In this embodiment, as shown in FIG. 3, two areas A11 and A12 occupying the same position (4 lines × 4 pixels) on two consecutive frames constitute one block.
The block includes 32 pixels. In addition, in the blocking circuit 8, the blanking period in the input signal is removed, the valid data is made continuous, and a data absence period is formed in the data sequence. One line contains 858 samples, the valid data of which is 720 samples, the number of lines in one frame is 525, and the number of valid lines is 488. And the number of valid data is as follows.

Number of valid data: 720 × 488 × 2 = 702,720 Number of data in two frame periods: 858 × 525 × 2 = 900,720 Blocking circuit 8 is composed of four frame memories, and only valid data of two frame periods is stored in two frame memories. At the same time, the valid data converted into the block order is read from the other two-frame memories.
By setting the read addresses of the two-frame memory to the order of the blocks, the order of the scanning lines can be converted to the order of the blocks. Accordingly, the output signal 9 of the blocking circuit 8 includes a data absence period of 231H (H: horizontal cycle) as in the following equation.

(900,720-702,720) {858} 231H The output signal 9 of the blocking circuit 8 is supplied to the ADRC encoder 10. In the ADRC encoder 10, the maximum value MAX and the minimum value MIN of each block, and the dynamic range
DR is detected, and variable-length coding is performed in accordance with the dynamic range DR. For example, four threshold values TH1, TH2, TH
3, TH4 (TH4 <TH3 <TH2 <TH1) is set. When the dynamic range DR of the block is (0 ≦ DR <TH4), the number of allocated bits is set to 0, and the maximum value MA of the block is set.
Only X and the minimum value MIN are transmitted. When (TH4 ≦ DR <TH3), the number of allocated bits is 1 bit. (TH3
When ≦ DR <TH2), the number of allocated bits is 2 bits. When (TH2 ≦ DR <TH1), the number of allocated bits is 3 bits. When (TH1 ≦ DR <255), the number of allocated bits is 4 bits. As these four thresholds, a threshold Yth for a luminance signal and a threshold Cth for a chrominance signal are used.

As described above, when encoding the variable length ADRC of 0 to 4 bits, the buffering process is performed so that the information amount in the two frame period does not exceed the predetermined value. The buffering calculates the frequency of occurrence of the dynamic range DR in the two-frame period, determines the optimal threshold values TH1 to TH4 from the distribution of the frequency of occurrence of the dynamic range DR, and further prepares the dynamic range DR to prepare for the next processing. Consists of a series of processes for clearing the memory in which the frequency is stored. Using the threshold value determined by this buffering, encoding of the variable length ADRC is performed.

The output signal 9 of the blocking circuit 8 is composed of two frames of valid data converted into the order of blocks, and the ADRC encoder 10 has a dynamic range in the data valid period.
The frequency of DR is collected, and in the above-mentioned data missing section, a process of creating an integrated frequency distribution table, determining a threshold value, and clearing a memory is performed. Next, according to the threshold, the variable length
Perform ADRC encoding.

Also, in the case of a still image block, the ADRC encoder 10 forms an average value of two areas A11 and A12 forming one block, and performs a frame drop process of encoding the average value in place of the two areas. You. As a result of the frame dropping process, the information amount of the image data is reduced to half in the case of a still image block. A motion determination code MDT indicating a still image block or a moving image block is formed.

The output signal of the ADRC encoder 10 includes a code signal (referred to as a bit plane BPL) 11 corresponding to each pixel and additional data 12. The additional data 12 includes a motion determination code MDT for each block, a dynamic range DR, a minimum value MIN, threshold values Yth and Cth of a luminance signal and a color difference signal, a block number, a two-frame identification signal DBFR, and the like. The number of pixels in one block is 16 for a still image and 32 for a moving image.
Therefore, the data amount of the bit plane BPL is 0 bytes at the minimum and 16 bytes at the maximum according to the bit length, as shown in FIG.
It becomes bytes.

The output signals 11 and 12 of the ADRC encoder 10 are supplied to a framing circuit 13 and converted into data having a frame configuration as described later. The output signal 14 of the framing circuit 13 is supplied to an error correction code parity generation circuit 15 and, for example, an error correction code having a product code configuration is encoded.

The output signal 16 of the parity generation circuit 15 is a recording processor 17
In this case, the data is distributed to four channels of data, and the parallel data is converted to serial data. The serial data for each channel is sent to the rotating heads 19A, 19A via the recording amplifiers 18A, 18B, 18C, 18D, respectively.
B, 19C, and 19D.

In the framing circuit 13, the output signal of the ADRC encoder 10
11 and 12 are converted into recording signals of a predetermined format. Hereinafter, an example of framing will be described.

The framing circuit 13 configures the recording data by using a block (referred to as an ADR block), which is a unit of four ADRC encodings, as a sub-block. That is, one ADR block includes a dynamic range DRi (i is an ADR block number), a minimum value MINi, and a bit plane BPLi including a code signal obtained by encoding. The length of the bit plane BPLi is not constant depending on the block due to the variable length coding.

Using the above four ADR blocks as sub-blocks, a synchronous (sync) block of a predetermined length is formed. FIG. 5 shows an example of the configuration of one sync block. A sync pattern (2 bytes) is added to the head of the sync block, and a sync block ID (2 bytes) is added next.
The sync block ID includes a segment ID for identifying a two-frame ID track for identifying every two frame periods, a sync block number, and the like. After this sync block ID, a 1-byte threshold value Yth for a luminance signal and a threshold value Cth for a chrominance signal are located, followed by a 2-byte ADR block number. This ADR
After the block number, a plurality of sub-blocks composed of four ADR blocks are located to form one sync block. The ADR block number indicates the number of the first ADR block among the four ADR blocks.

In this case, the rotary heads HA, HB, HC, and HD are mounted in an in-line arrangement at substantially the same rotation angle position, and four tracks are formed on the tape by one scan. In addition,
In this example, the tape is wrapped around the guide drum over a 180 degree angular range. Then, the head is rotated so that data of two frames is recorded as 20 tracks (accordingly, at a rate of five rotations in two frames).

 Next, the reproduction system shown in FIG. 1 will be described.

Reproduction outputs from the rotary heads HA, HB, HC, and HD are passed through reproduction amplifiers 21A, 21B, 21C, and 21D, respectively, to equalizers 22A, 22B, and 22.
C, 22D. The outputs of the equalizers 22A, 22B, 22C, 22D are
After being supplied to digital waveform shaping circuits 23A, 23B, 23C, and 23D and digitized, D flip-flop circuits 24A, 24B,
Supplied to 24C and 24D. Outputs of the equalizers 22A, 22B, 22C, and 22D are also supplied to clock regeneration PLL circuits 25A, 25B, 25C, and 25D, and clock pulses CKA, CKB, CKC, and CKD are reproduced. The clock pulses CKA, CKB, CKC, and CKD are supplied to D flip-flop circuits 24A, 24B, 24C, and 24D. And digital data DA, DB, DC, and DD synchronized with CKD.

The digital data DA, DB, DC, and DD are supplied to serial-parallel conversion circuits 26A, 26B, 26C, and 26D, respectively. Also, clock pulses CKA, 25 from the PLL circuits 25A, 25B, 25C, 25D
CKB, CKC, and CKD are supplied to the serial-parallel conversion circuits 26A, 26B, 26C, and 26D, respectively. From the serial-parallel conversion circuits 26A, 26B, 26C, and 26D, data in byte units and a clock signal with a byte cycle are obtained. The data in byte units are stored in FIFO memories 27A, 27B, 27C, and 27D, respectively.
Is supplied to the data input terminal of A clock signal having a byte cycle is supplied to the FIFO memories 27A, 27B, 27C, and 27D as a write clock.

In addition, the rotation phases of the rotating heads HA, HB, HC, and HD are shown.
A pulse PG (FIG. 6A) obtained for each degree rotation angle is supplied to the timing signal generation circuit 29. From the timing signal generation circuit 29, a signal RFSW (B in the drawing) synchronized with the scanning of the heads HA, HB, HC, and HD on the tape is obtained. Head HA, H
Data from B, HC, and HD are obtained during the high level period of the signal RFSW, as shown in FIG.

From the timing signal generation circuit 29, a write reset signal RTSW (FIG. 9C) is supplied to the FIFO memories 27A, 27B, 27C and 27D, respectively, and a write enable signal WE1 (E in FIG. 10) synchronized with the signal RFSW is supplied. Is done. Each of the FIFO memories 27A, 27B, 27C, 27D has a head HA, HB, HC,
Data A0, A1, A2 · obtained by one HD scan on the tape
.. (F in the same figure), B0, B1, B2 ... (G in the same figure), C0, C1, C2
(H in the figure), D0, D1, D2... (I in the figure) are written. The capacity of the FIFO memories 27A, 27B, 27C, 27D is
Any device that can store data obtained by one scan of A, HB, HC, and HD may be used.

Thus, the 1 stored in the FIFO memories 27A, 27B, 27C, 27D
As shown in FIG. 6, data obtained by the head scanning is read out during one rotation period of the head after the writing period.

Reference numeral 30 denotes a reference timing signal generation circuit 30 including a crystal oscillator, to which a signal RFSW is supplied. From the timing signal generation circuit 30, the read reset signals RSTRA, RSTRB, and RS are out of phase with each other (one rotation period / 4) during one rotation period of the head, which is the read period.
TRC, RSTRD (FIG. 6, J, L, N, P) and read enable signals REA, REB, REC, RED (K, M, O, Q in FIG. 6) are obtained. Then, the reset signal RSTRA and the enable signal REA are supplied to the FIFO memory 27A, and during the high level period of the enable signal REA, data A0, A1, A2 obtained by one scan of the head HA.
.. Are read from the FIFO memory 27A.

Also, the reset signal RSTRB and the enable signal REB
The data B0 and B, which are supplied to the FO memory 27B and obtained by one scan of the head HB during the high level period of the enable signal REB.
Are read from the FIFO memory 27B.

Also, the reset signal RSTRC and the enable signal REC are
The data C0 and C0 supplied to the FO memory 27C and obtained by one scan of the head HC during the high level period of the enable signal REC.
Are read from the FIFO memory 27C.

Also, the reset signal RSTRD and the enable signal RED are
The data D0 and D are supplied to the FO memory 27D and obtained by one scan of the head HD during the high level period of the enable signal RED.
Are read from the FIFO memory 27D.

Since writing of data to the FIFO memories 27A, 27B, 27C, and 27D is performed by the reproduction clock and reading is performed by the reference clock, the time axis error correction is performed in the FIFO memories 27A to 27D.

The data output terminals of the FIFO memories 27A, 27B, 27C, 27D are commonly connected to each other, and are connected to the input terminal of the buffer register 31. The buffer register 31 is supplied with a clock having a byte cycle from the timing signal generation circuit 30. As described above, the outputs of the FIFO memories 27A, 27B, 27C, and 27D are read at different timings from each other. Therefore, as shown in FIG. It is obtained in the state of.

In this case, since the data is ADRC and is compressed, there is ample room for reading from the FIFO memories 27A, 27B, 27C, and 27D.

The output of the buffer register 31 is output via the sync block ID extraction circuit 32 and via the buffer register 33.
Large-capacity memory 34 that can store more data than frames
Supplied to The extraction circuit 32 extracts a sync block ID for each sync block. Then, the data of each sync block is written to the memory 34 according to the sync block ID.

FIG. 7 is a view for explaining the contents stored in the memory area for two frames of the memory 34. In this example, 120 sync blocks are recorded per track. As described above, the data of two frames is 20
Recorded on the track of the book. As shown in FIG. 7, the memory area for two frames of the memory 34 is divided into 20 in the horizontal direction, and the data of one track is divided into the respective divided areas seg0.
Written to ~ seg19. Then, each divided area seg0 to seg
19 is further divided into 120 in the vertical direction, and data of one sync block is sequentially written in each of the subdivided areas SB0 to SB119 in the horizontal direction.

For example, 12-bit sync block address data SYAD is obtained from the extraction circuit 32. The upper 5 bits of the 12-bit address data SYAD indicate from which track out of the 20 tracks in which the data of 2 frames are recorded, and the division areas seg0 to seg19 are specified by this. You. The lower 7 bits indicate the sync block number, and the subdivision areas SB0 to SB119 are specified by this.

The sync block address data SYAD is supplied to the address conversion circuit 35. From the address conversion circuit 35,
The sub-regions SB0 to SB of the sub-region specified by the upper 5 bits of the address data SYAD in the sub-regions seg0 to seg19
In B119, address data AD representing the head address of the subdivision area specified by the lower 7 bits of address data SYAD is obtained. The head address data of the subdivision area is the head data address of the data of the sync block to be written (see FIG. 8A). The address data AD has 19 bits in this example.
The head address data AD is supplied to a preset terminal of the write address counter 36.

Further, a sync pulse SP (FIG. 8B) obtained from the extraction circuit 32 at the head of the sync block is supplied to the load terminal of the write address counter 36, and the head address is preset by the sync pulse SP. .
Further, a clock CKW (FIG. 9C) having a byte cycle is supplied as a clock of the write address counter 36. Therefore, from this write address counter 36,
Start address AD1, AD2, ... of the specified subdivision area
From this, the write address for each byte is obtained sequentially (D in the figure). This write address is supplied to the address terminal of the memory 34, and the data Si, T
i... (i = 0, 1, 2,..., 119) are written to the memory 34 (E in FIG. 8).

Reference numeral 37 denotes a read address counter which is cleared by a signal RS of a two-frame cycle and counts a clock CKR of a byte cycle. The read address from the read address counter 37 is also supplied to the address terminal of the memory 34. From the memory 34, data in byte units is sequentially read from the head address of the memory area of the data of two frames, that is, from the head data of the data of two frames.

With the above configuration, even during special playback such as high-speed playback, data from 20 tracks on which data for two frames are recorded is stored in the memory 34 for two frames shown in FIG. Written to the memory area, and
The data is sequentially read from the head data of the frame. In addition,
The write address and the read address are separated so that the write and the read do not become the same address. The memory 34 has a write enable signal
WE is supplied, and one data cycle of one byte is defined as one memory cycle, and this one memory cycle is time-divided into a write cycle and a read cycle. The write enable signal WE is supplied to the output enable terminal of the buffer register 33.
Data is output to the memory 34 when the memory 34 is in a write cycle.

The data read from the memory 34 is supplied to an error correction circuit 39 via a buffer register 38. In the error correction circuit 39, the error is corrected by the error correction code. The error correction circuit 39 generates corrected data 40 and an error flag 41 indicating the presence or absence of an error.

Output signals 40 and 41 of the error correction circuit 39 are supplied to a frame decomposition circuit 42. The frame decomposing circuit 42 separates the bit plane 43, the additional data 44, and the error flag 41. The output signals 41, 43, and 44 of the frame decomposing circuit 42
It is supplied to the RC decoder 45. In the ADRC decoder 45, the bit plane 43 is decoded by using the additional data 44, and 8-bit data corresponding to each pixel is obtained. Output signals 44 and 46 of the ADRC decoder 45 are supplied to a block decomposition circuit 47.

The block decomposition circuit 47 is constituted by a four-frame memory, and converts data of each pixel in the order of blocks into a signal in the scanning order of a television signal. Block decomposition circuit 47
Thereafter, pixel data 48 which is an 8-bit code signal corresponding to each pixel, an error flag 49 indicating whether or not each pixel has an error, and a motion determination code 50 are generated. The motion determination code 50 is a signal indicating whether the block is a still image block or a moving image block, and is separated from the additional data 44. In the case of a still image block, the ADRC encoder 10
Instead of the two areas A11 and A12 constituting the block, frame drop compression is performed in which the average value of both is encoded.

Output signals 48, 49, 50 of the block decomposition circuit 47 are supplied to a smoothing circuit 51. In the smoothing circuit 51, interpolation is performed on the still image block that has been dropped and compressed, and one area is used as data of two areas. At the same time, when the still image blocks continue, a smoothing process is performed to prevent the connection of the images between the blocks from becoming unnatural. At the output of the smoothing circuit 51, pixel data 52 and an error flag 49 are generated, and these output signals are supplied to an error correction circuit 53. In the error correction circuit 53, the error data is interpolated by other correct data having a temporal and spatial correlation.

The output signal 54 of the error correction circuit 53 is supplied to the rate conversion circuit 55. The relay conversion circuit 55 converts the (3: 1: 0) time-division multiplexed signal into a (4: 4: 4) component signal. Output signals (luminance signal Y, color difference signals U, V) of the rate conversion circuit 55 are supplied to a digital matrix circuit 56, where they are converted into three primary color signals (R, G, B). D / A conversion circuit 57
Thus, the three primary color signals are converted into analog three primary color signals, and are taken out to output terminals 58, 59, and 60.

As described above, the output data from the FIFO memories 27A, 27B, 27C, and 27D are superimposed in a time-division manner.
Since the data of four channels does not arrive at the ID extracting circuit 32 at the same time, an interchanger is not necessary as in the prior art. That is, the extraction circuit 32 can be constituted by an extraction circuit for the sync block ID for one channel, and does not require a memory or the like, so that the configuration is simplified. Since the data is ADRC and compressed data, the data rate is low and a sufficient signal processing time can be secured. Therefore, a high-speed processing circuit is not particularly required as a processing circuit.

In the above, four heads were arranged inline,
Although the present invention is applied to a rotary head, the present invention is applicable to various types of heads, head arrangements and rotary head devices. Further, the present invention can be applied to a digital VTR of a fixed head system.

Further, it is needless to say that the present invention is applicable not only to the digital VTR but also to various information signal reproducing devices.

〔The invention's effect〕

According to the present invention, when a plurality of channel head outputs are written to the first small-capacity memory and data is read from the first memory, the plurality of channel head outputs are converted to data of channels smaller than the original number of channels. Therefore, an address detection circuit may be provided for the multiplexed data at the time of writing to a memory provided at a subsequent stage and returning to the original data of one channel.
That is, unlike the related art, since data of a plurality of channels does not arrive at the same time, an interchanger having a memory as in the related art is not required, and the configuration of the reproducing apparatus can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a digital signal reproducing apparatus according to the present invention, FIG. 2 is a block diagram of an example of a digital signal recording apparatus, and FIGS. 3 to 5 are diagrams for explaining recording data. FIG. 6, FIG. 6 is a time chart for explaining the example of FIG. 1, FIG. 7 is a diagram for explaining the contents of the memory,
FIG. 8 is a time chart for explaining writing to the second memory. Description of main symbols in the drawings HA, HB, HC, HD: rotary head, 27A, 27B, 27C, 27D: FIFO memory, 32: sync block ID extraction circuit, 33: large capacity memory, 36: write address counter.

Claims (1)

(57) [Claims] 1. A reproduction digital signal of a plurality of channels reproduced simultaneously by a plurality of heads is synchronized with the reproduction digital signal in a plurality of first memories having a capacity capable of storing data reproduced by one scan. A clock signal is stored in correspondence with each of the plurality of heads, and data stored in the plurality of first memories is read out by a reference clock signal within one rotation cycle of the plurality of heads. Multiplexing the data with the number of channels smaller than the number of channels of the reproduced digital signal, supplying the multiplexed data to an address detection circuit, and according to the address detected by the address detection circuit,
A digital signal reproducing apparatus in which the multiplexed data is written to a second memory.