JP2712601B2 - Method of manufacturing circuit board with built-in resistor - Google Patents

Method of manufacturing circuit board with built-in resistor

Info

Publication number
JP2712601B2
JP2712601B2 JP1207260A JP20726089A JP2712601B2 JP 2712601 B2 JP2712601 B2 JP 2712601B2 JP 1207260 A JP1207260 A JP 1207260A JP 20726089 A JP20726089 A JP 20726089A JP 2712601 B2 JP2712601 B2 JP 2712601B2
Authority
JP
Japan
Prior art keywords
resistor
material layer
built
circuit board
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1207260A
Other languages
Japanese (ja)
Other versions
JPH0371696A (en
Inventor
修 花島
荘太郎 土岐
光彦 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP1207260A priority Critical patent/JP2712601B2/en
Publication of JPH0371696A publication Critical patent/JPH0371696A/en
Application granted granted Critical
Publication of JP2712601B2 publication Critical patent/JP2712601B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 <産業上の利用分野> 本発明は、抵抗体を内蔵した回路基板及びその製造方
法に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board having a built-in resistor and a method for manufacturing the same.

<従来の技術> 抵抗体内蔵基板は標準として厚さ70μm又は35μm、
18μmの電解銅箔を高導電材料層に用い、この片面にウ
エットめっき法でニッケル合金等の抵抗材料層及び絶縁
支持体を設けたものである。
<Conventional technology> A resistor built-in substrate has a standard thickness of 70 μm or 35 μm,
An electrolytic copper foil of 18 μm is used for a highly conductive material layer, and a resistance material layer such as a nickel alloy and an insulating support are provided on one side of the layer by wet plating.

この抵抗体内蔵基板から抵抗体内蔵の回路基板を形成
するには、フォトレジスト法が用いられるが、はじめに
抵抗パターン及び導体パターンの組合せパターンをフォ
トレジストで被覆した状態でそのパターン以外の部分の
高導電材料層とその直下の抵抗材料層を腐蝕除去し、次
に導体パターンのみを被覆した状態で電気抵抗パターン
の高導電材料層の部分を腐蝕除去して所望の抵抗回路が
形成される。
In order to form a circuit board with a built-in resistor from the substrate with a built-in resistor, a photoresist method is used. First, a combination pattern of a resistor pattern and a conductor pattern is covered with a photoresist, and the height of a portion other than the pattern is raised. The conductive material layer and the resistive material layer immediately thereunder are removed by corrosion, and then, while only the conductive pattern is covered, the portion of the high conductive material layer of the electrical resistance pattern is removed by corrosion to form a desired resistance circuit.

第1図(a)〜(h)は抵抗体内蔵の回路基板の製造
工程を示す。第1図(a)は、加工前の抵抗体内蔵基板
であるが、その構成は上の層から順番に、高導電材料層
1、抵抗材料層2、絶縁支持体3からなっている。第1
図(b)は、上記抵抗体内蔵基板表面に所定のフォトレ
ジスト膜4を設けた図であり、その後エッチングによ
り、高導電材料層1を選択除去したものが、第1図
(c)に示す状態である。その後、フォトレジスト膜4
を介したまま、抵抗材料層を選択除去し(第1図
(d))、フォトレジスト膜4を剥離した状態が第1図
(e)であり、この時に基本回路パターンが形成され
る。そして、再び高導電材料層1の上にフォトレジスト
膜5を設け(第1図(f))、第1図(g)のように高
導電材料層1を選択除去する。その後フォトレジスト膜
5を剥離して第1図(h)に示すような高導電部分6、
抵抗部分7、絶縁部分8の絶縁支持体3上への作成が終
了する。
1 (a) to 1 (h) show a process of manufacturing a circuit board having a built-in resistor. FIG. 1A shows a substrate with a built-in resistor before processing, which is composed of a high conductive material layer 1, a resistance material layer 2, and an insulating support 3 in this order from the upper layer. First
FIG. 1B is a diagram in which a predetermined photoresist film 4 is provided on the surface of the above-mentioned resistor-containing substrate, and FIG. 1C shows a structure in which the highly conductive material layer 1 is selectively removed by etching. State. After that, the photoresist film 4
FIG. 1 (e) shows a state in which the resistive material layer is selectively removed while passing through (FIG. 1 (d)) and the photoresist film 4 is peeled off. At this time, a basic circuit pattern is formed. Then, a photoresist film 5 is provided again on the high conductive material layer 1 (FIG. 1 (f)), and the high conductive material layer 1 is selectively removed as shown in FIG. 1 (g). Thereafter, the photoresist film 5 is peeled off, and the highly conductive portions 6 as shown in FIG.
The formation of the resistance portion 7 and the insulating portion 8 on the insulating support 3 is completed.

以上のように、この工程上において、高導電材料層
は、少なくとも2回のエッチング工程(第1図(b)〜
(c)、第1図(f)〜(g))を経なければならず、
特に2回目のエッチング工程(第1図(f)〜(g))
は高導電材料層直下の抵抗材料層を腐蝕させることなく
行わなければならない。換言すれば、この工程に使用さ
れるエッチング液は、高導電材料層と抵抗材料層に対し
て選択性を有するものでなくてはならない。ところが、
実際に利用できる高導電材料層用腐蝕性の選択性はそれ
ほど厳密でなく、そのため高導電材料層のエッチングの
際にその下から露出してくる抵抗材料層をも部分的に腐
蝕してその抵抗値を高めてしまい、所望の抵抗値から隔
たることになる。例えば、高導電材料として銅を用い、
抵抗材料としてニッケル合金を用いる場合、銅箔用のエ
ッチング液として最も普及している塩化第2鉄、塩化第
2銅等の水溶液は、第1図(b)〜(c)でのエッチン
グに用いる場合問題ないが、第1図(f)〜(g)での
エッチングでは上記の選択性の点でこの種の抵抗体内蔵
の回路基板には使用不可能であるため、特にクロム酸と
硫酸混合のエッチング液が使用されていた。それでもな
お、エッチングの選択性は満足すべきものではなく、そ
のため、銅箔のエッチング後は露出した抵抗材料層がで
きうる限りエッチング液に触れないよう注意が必要であ
った。また、設備や環境の面からも6価クロムは有害な
ので、特殊な設備が必要とされ、作業時の環境も安全性
を考えて従来以上の工夫が必要である。
As described above, in this step, the highly conductive material layer is subjected to at least two etching steps (FIG. 1B).
(C) and FIGS. 1 (f) to (g)).
In particular, the second etching step (FIGS. 1 (f) to (g))
Must be performed without corroding the resistive material layer immediately below the highly conductive material layer. In other words, the etchant used in this step must have selectivity for the highly conductive material layer and the resistive material layer. However,
The selectivity of the corrosiveness of the high conductive material layer which can be actually used is not so strict, and therefore, when the high conductive material layer is etched, the resistive material layer which is exposed from underneath is partially corroded and the resistance is lowered. The value will be increased, and will deviate from the desired resistance value. For example, using copper as a highly conductive material,
When a nickel alloy is used as the resistance material, an aqueous solution of ferric chloride, cupric chloride, or the like, which is most widely used as an etching solution for copper foil, is used for etching in FIGS. 1 (b) to 1 (c). Although there is no problem in the case of etching in FIGS. 1 (f) to 1 (g), it is impossible to use this kind of circuit board with a built-in resistor in view of the above selectivity. Was used. Nevertheless, the selectivity of the etching is not satisfactory, and therefore, care must be taken not to touch the etching solution as much as possible after the etching of the copper foil so that the exposed resistive material layer is formed. In addition, hexavalent chromium is harmful from the viewpoint of equipment and environment, so special equipment is required, and the work environment needs to be improved more than before in consideration of safety.

<発明が解決しようとする課題> 本発明は、従来問題になっていた高導電材料層と抵抗
材料層の専用のエッチング液によるエッチング選択性の
不充分さをエッチング液の変更から解決しようとするも
のである。
<Problems to be Solved by the Invention> The present invention is to solve the problem of insufficient selectivity of a high-conductivity material layer and a resistive material layer, which has been a problem in the past, by using a dedicated etchant by changing the etchant. Things.

<課題を解決するための手段> 即ち、本発明は、絶縁支持体の少なくとも片面にニッ
ケル合金からなる抵抗材料層と高導電体層が形成された
抵抗体内蔵基板から、抵抗体内蔵の回路基板を製造する
方法において、エッチングの際に硫酸アンモニウム・硫
酸銅(2価の銅イオン濃度が5〜200g/)及び水酸化
化合物からなるpH7.5〜9.5の範囲の液を使用することを
特徴とする抵抗体内蔵の回路基板の製造方法である。
<Means for Solving the Problems> That is, the present invention relates to a circuit board with a built-in resistor, from a substrate with a built-in resistor in which a resistance material layer made of a nickel alloy and a high conductor layer are formed on at least one surface of an insulating support. A method of using a solution of ammonium sulfate and copper sulfate (divalent copper ion concentration is 5 to 200 g /) and a hydroxide compound having a pH of 7.5 to 9.5 at the time of etching. This is a method for manufacturing a circuit board with a built-in resistor.

<作用> 本発明の抵抗体内蔵の回路基板の作製方法は実施例に
おいて述べるが、作製において第1図(f)〜(g)で
用いるエッチング液に関して説明する。
<Operation> A method for manufacturing a circuit board with a built-in resistor according to the present invention will be described in Examples, but an etching solution used in FIGS. 1 (f) to 1 (g) in manufacturing will be described.

本発明の中で触れる抵抗体内蔵の回路基板の材料構成
は、絶縁支持体の少なくとも片面にニッケル合金からな
る抵抗材料層と高導電体層が形成されたもので第1図
(a)に示してある。第1図(b)〜(c)及び第1図
(c)〜(d)で用いるエッチング液は従来使用してい
るエッチング液で変更はないが、第1図(f)〜(g)
におけるエッチング液は下記する本発明の液を使用し
た。第1図(f)〜(g)における従来のエッチング液
としてクロム酸と硫酸の混合液が用いられてきたが、前
述したように高導電材料層除去の際、下層の抵抗材料層
も若干エッチングしてしまう。また、クロム酸を使用す
るため、作業に関しては通常の設備・環境では行えず、
特殊設備も必要とされる。著者等は、上記した点を解決
すべく様々な試薬を検討した結果、硫酸アンモニウム、
硫酸銅(2価の銅イオン濃度が5〜200g/)及び水酸
化化合物から成る液がpH7.5〜9.5の範囲において、銅と
ニッケル合金の溶解速度比が1000:1以上になる事をみい
だしたのである。ここで用いる水酸化化合物とは、水酸
化ナトリウム、水酸化カリウム、水酸化アンモニウムを
いう。この時、銅の化学的溶解における反応式は次のよ
うに考えられる。
The material structure of the circuit board with a built-in resistor in the present invention is shown in FIG. 1 (a) in which a resistive material layer made of a nickel alloy and a high conductor layer are formed on at least one surface of an insulating support. It is. The etching solution used in FIGS. 1 (b) to 1 (c) and FIGS. 1 (c) to 1 (d) is the same as the etching solution conventionally used, but is not changed in FIGS. 1 (f) to 1 (g).
As the etching solution in the above, the following solution of the present invention was used. Although a mixed solution of chromic acid and sulfuric acid has been used as a conventional etching solution in FIGS. 1 (f) to 1 (g), the lower resistive material layer is slightly etched when the highly conductive material layer is removed as described above. Resulting in. Also, since chromic acid is used, work cannot be performed in ordinary facilities and environment,
Special equipment is also required. The authors studied various reagents to solve the above points, and found that ammonium sulfate,
It has been found that the dissolution rate ratio between copper and nickel alloy is more than 1000: 1 when the liquid composed of copper sulfate (divalent copper ion concentration is 5-200 g /) and hydroxide compound is in the pH range of 7.5-9.5. I was sorry. The hydroxyl compound used herein refers to sodium hydroxide, potassium hydroxide, and ammonium hydroxide. At this time, the reaction formula in the chemical dissolution of copper is considered as follows.

Cu+Cu(NH34 2+→2Cu(NH32 + ・・・・(1) Cu(NH3)2++1/402+2NH3+1/2H2O→Cu(NH3)4 2++OH- ・・・・(2) (1)式は銅の溶解を示すものであり、銅は一部アン
モニア錯体として存在している。
Cu + Cu (NH 3 ) 4 2+ → 2Cu (NH 3 ) 2 +・ ・ ・ ・ (1) Cu (NH 3 ) 2+ +1/40 2 + 2NH 3 + 1 / 2H 2 O → Cu (NH 3 ) 4 2+ + OH - ···· (2) ( 1) formula is intended to indicate a dissolution of the copper, the copper is present as part ammonia complex.

(2)式は1価の銅錯イオンを2価に酸化させ再び
(1)式の反応に用いるための液の回復機構を示すもの
である。
The formula (2) shows a liquid recovery mechanism for oxidizing a monovalent copper complex ion to divalent and using it again in the reaction of the formula (1).

以下実施例にて本発明の詳細を説明する。 Hereinafter, the present invention will be described in detail with reference to examples.

<実施例> 当該回路基板において絶縁支持体として厚さ1.6mmの
ガラスエポキシ材、高導電材料層に厚さ35μm電解銅箔
(日本鉱業社製)、中央に挟まれた抵抗材料層に厚さ0.
4μmのNi−P合金を用いた抵抗体内蔵基板を作製し
た。その後第1図(a)〜(h)に示すような工程に沿
って目的とする回路基板を作製していくわけだが、第1
図(b)〜(c)の工程でエッチング液は塩化第2鉄液
を用い、スプレー方式で行った。エッチング温度は40
℃、エッチング時間は約2分であった。この時使用した
フォトレジストはドライフィルム(デュポン社製)であ
る。第1図(c)〜(d)のエッチングは、第1図
(b)の所定のフォトレジスト膜をそのまま介して硫酸
銅と硫酸の混合液にて抵抗材料層たるNi−P合金をディ
ッピングにてエッチング除去した。エッチング温度は90
〜95℃、エッチング時間は約3分であった。その後、第
1図(b)で使用していたフォトレジスト膜を剥離し、
第1図(f)に示すような所定のフォトレジスト膜を設
け、本発明のポイントである硫酸アンモニウム・硫酸銅
(2価の銅イオン濃度が20〜40g/)及び水酸化化合物
からなるpH7.5〜9.5の範囲の液で抵抗材料層上の高導電
体層であるところの銅のみをスプレー方式でエッチング
を行った。表1の条件で銅のエッチングを行ったがエッ
チング後のNi−P合金の溶解状況は約0.01μm程度侵さ
れただけであった。
<Example> A glass epoxy material having a thickness of 1.6 mm as an insulating support on the circuit board, a 35 μm-thick electrolytic copper foil (manufactured by Nippon Mining Co., Ltd.) for a highly conductive material layer, and a thickness for a resistance material layer sandwiched in the center 0.
A resistor built-in substrate using a 4 μm Ni-P alloy was produced. Thereafter, the target circuit board is manufactured according to the steps shown in FIGS. 1 (a) to 1 (h).
In the steps of FIGS. (B) to (c), a ferric chloride solution was used as an etching solution and a spray method was used. Etching temperature is 40
C. and the etching time was about 2 minutes. The photoresist used at this time is a dry film (manufactured by DuPont). The etching of FIGS. 1 (c) to 1 (d) is performed by dipping the Ni-P alloy which is a resistive material layer with a mixed solution of copper sulfate and sulfuric acid through the predetermined photoresist film of FIG. 1 (b) as it is. And removed by etching. Etching temperature is 90
9595 ° C., the etching time was about 3 minutes. After that, the photoresist film used in FIG.
A predetermined photoresist film as shown in FIG. 1 (f) is provided, and pH 7.5 comprising ammonium sulfate / copper sulfate (divalent copper ion concentration is 20 to 40 g /) and a hydroxide compound, which is the point of the present invention, is used. Only copper, which is a high conductor layer on the resistance material layer, was etched by a spray method with a liquid in the range of 範 囲 9.5. Copper etching was performed under the conditions shown in Table 1, but the dissolution state of the Ni-P alloy after etching was only about 0.01 μm.

第1図(f)で使用したフォトレジストは一回目のパ
ターニングで用いたドライフィルムと同様である。
The photoresist used in FIG. 1 (f) is the same as the dry film used in the first patterning.

<発明の効果> 本発明の抵抗体内蔵の回路基板の製造工程において、
その工程の部分で使用していたクロム酸−硫酸の混合液
から本発明による液に変更することによって、抵抗材料
層の浸食もなく精度の良い抵抗体内蔵の回路基板を提供
する事が出来た。また従来問題になっていた作業環境の
問題がなくなり、設備面も簡潔になった。
<Effect of the Invention> In the manufacturing process of the circuit board with a built-in resistor of the present invention,
By changing the chromic acid-sulfuric acid mixture used in the process to the solution according to the present invention, it was possible to provide a circuit board with a built-in resistor with high accuracy without erosion of the resistance material layer. . In addition, the problem of the working environment, which has been a problem in the past, has been eliminated, and the equipment has been simplified.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(h)は、抵抗体内蔵の回路基板製造の
工程の概略を示す説明図である。 1……高導電材料層、2……抵抗材料層 3……絶縁支持体、4,5……フォトレジスト膜、 6……高導電部分、7……抵抗部分、 8……絶縁部分、
1 (a) to 1 (h) are explanatory views schematically showing steps of manufacturing a circuit board with a built-in resistor. DESCRIPTION OF SYMBOLS 1 ... High conductive material layer, 2 ... Resistive material layer 3 ... Insulating support, 4, 5 ... Photoresist film, 6 ... High conductive part, 7 ... Resistance part, 8 ... Insulating part,

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁支持体の少なくとも片面にニッケル合
金からなる抵抗材料層と高導電体層が形成された抵抗体
内蔵基板から、抵抗体内蔵の回路基板を製造する方法に
おいて、エッチングの際に硫酸アンモニウム・硫酸銅
(2価の銅イオン濃度が5〜200g/)及び水酸化化合
物からなるpH7.5〜9.5の範囲の液を使用することを特徴
とする抵抗体内蔵の回路基板の製造方法。
1. A method for manufacturing a circuit board with a built-in resistor from a substrate with a built-in resistor, in which a resistive material layer made of a nickel alloy and a high-conductivity layer are formed on at least one surface of an insulating support, A method for manufacturing a circuit board with a built-in resistor, characterized by using a solution of ammonium sulfate / copper sulfate (divalent copper ion concentration: 5 to 200 g /) and a hydroxide compound in a pH range of 7.5 to 9.5.
JP1207260A 1989-08-10 1989-08-10 Method of manufacturing circuit board with built-in resistor Expired - Fee Related JP2712601B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1207260A JP2712601B2 (en) 1989-08-10 1989-08-10 Method of manufacturing circuit board with built-in resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1207260A JP2712601B2 (en) 1989-08-10 1989-08-10 Method of manufacturing circuit board with built-in resistor

Publications (2)

Publication Number Publication Date
JPH0371696A JPH0371696A (en) 1991-03-27
JP2712601B2 true JP2712601B2 (en) 1998-02-16

Family

ID=16536848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1207260A Expired - Fee Related JP2712601B2 (en) 1989-08-10 1989-08-10 Method of manufacturing circuit board with built-in resistor

Country Status (1)

Country Link
JP (1) JP2712601B2 (en)

Also Published As

Publication number Publication date
JPH0371696A (en) 1991-03-27

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