JP2710378B2 - External memory unit copy protection system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a copy protection system for an external memory unit. More specifically, the present invention relates to a copy protection system for preventing unauthorized copying of an external memory unit detachable from an information processing apparatus.

(Prior art)

Showa 61- published on April 18, 1986
As disclosed in Japanese Patent No. 57989, a game in which a game program and an operation program of the operation means are incorporated in a main body including a dot matrix type liquid crystal display device (hereinafter, referred to as “LCD”) and operation means for driving the LCD 2. Description of the Related Art There is known a liquid crystal game board provided with a cassette which can be inserted and removed.

In a game device or the like using an external memory unit represented by a liquid crystal game board of this type, it is necessary to prevent illegal copying of a game cassette, that is, an external memory unit.

One such copy protection method is disclosed in Japanese Patent Publication No. 53-17849 published on Oct. 18, 1972 (1972). In the first method, first information (password) for assigning a specific information processing device to another information processing device is provided, and the first information and the software, that is, the first information provided to the floppy disk. The password is compared with the password information of No. 2 and the use of the floppy disk is permitted only when the two match.

A second method is disclosed in U.S. Pat. No. 4,462,076 issued Jul. 24, 1984. In this method, data indicating the copyright holder is stored in both the main unit side memory and the cartridge side memory,
The two are compared, and if they match, the copyright owner data is simply displayed, and then the game program is executed.

Furthermore, there is a third method disclosed in Japanese Patent Publication No. 59-18074 published on April 25, 1984.
According to this method, copy protection information such as a trademark is stored in each of a plurality of semiconductor memories, and when a board on which a program is copied is used, the copy protection information such as a trademark is displayed on a CRT, and thereby the trademark is displayed. It is possible to crack down on infringement.

Further, as a fourth method, there is a method disclosed in Japanese Patent Application Laid-Open No. 58-101349, which was published on June 16, 1983 (1983). In the fourth method, after information (registered trademark, owner name, etc.) in a data table stored in the game ROM 16 is displayed on the display 15, an identifier included in the information in the data table, When the microprocessor 10 compares the reference identifier stored in the executive ROM 12 with the reference identifier and determines that the two match (or matches), the microprocessor 10 executes an execution process of another program stored in the game ROM 16. When it is determined that they do not match, an error is displayed based on the data in the game ROM 16 and an endless loop is executed to prevent the game from being played depending on an incorrect game ROM. is there.

[Problems to be solved by the invention]

The third method is not effective for copy protection information, that is, for a copied product whose trademark has been modified so as to avoid trademark infringement. That is, since the infringement of the trademark right cannot be claimed by modifying the copy protection information, it is not an effective copy protection system.

The first and second methods are very similar, and both allow use of a floppy disk or cartridge on condition that the first and second data match. However, in the first method, since the password information is not displayed, the information of the copyright holder cannot be displayed as in the second method.

On the other hand, in the second method, when the copyright holder data in the main unit side memory does not match the copyright holder data in the cartridge side memory, the cartridge cannot be used, but the copyright holder data is not displayed. Therefore, the operator or user cannot know why the cartridge cannot be used. Therefore, the operator or the user cannot determine whether the game cannot be started due to the inconsistency of the copyright holder data, or whether the game is due to a defective cartridge or a defective main unit, and there is a possibility that the operator or the user may mistakenly determine that the main unit has failed. is there.

In the fourth method, an identifier stored in the game ROM 16, that is, a code corresponding to character data for display is compared with an identifier (code) stored in the executive ROM 12. If the character data corresponding to the code is falsified in the same manner, it is impossible to claim trademark infringement.

Furthermore, in the fourth method, the memory space accessible by the CPU is the same before and after the identifier comparison is determined to be valid, so that even if the program execution of the game ROM 16 is deactivated, the same Game ROM 16 in memory space
Is seriously disadvantageous in that the protection function is easily invalidated by altering the jump destination address programmatically.

SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a copy protection system for an external memory unit that can completely prevent copying.

[Means for solving the problem]

In brief, the present invention relates to an external memory unit having a built-in external memory and being detachably attached to an information processing apparatus, and a program stored in the external memory by display means when the external memory unit is mounted. An anti-copy system for an external memory unit in an information processing system including an information processing device capable of displaying a predetermined image in accordance with data, wherein the information processing device is capable of accessing a predetermined maximum address space. Means, and a first memory area corresponding to a first memory space relatively smaller than the maximum address space, based on the first character data and the first character data for copy prevention of the external memory unit. And the validity determination program data for determining the validity of the external memory unit. The external memory of the external memory unit includes a second memory area having a memory space corresponding to the first memory space and a third memory area having a relatively large second memory space. A second character data having a predetermined relationship with the first character data stored in the internal memory in a part of the third memory region of the external memory, including a memory region;
At least a remaining memory area of the third memory area of the external memory stores program data for displaying an image corresponding to a predetermined purpose of use, and the information processing apparatus further has a function of making the internal memory accessible. A first switching signal, a second switching signal for enabling access to a memory area corresponding to second character data stored in the external memory, and a second switching signal for enabling access only to the external memory. Memory switching means for selectively outputting the switching signal of the third character and the display control means for displaying the second character data stored in the external memory on the display means. When the memory unit is mounted, the second switching signal is output to the memory switching means, and the second character data is output by the display control means. After the display on the display means, the first switching signal is output to the memory switching means, and the first character data and the second character data are output based on the validity determination program data stored in the internal memory. Are determined to be in a predetermined relationship, and when it is determined that they are in the predetermined relationship, a third switching signal is output to the memory switching means to allow access to the external memory, and the relationship is not established. An access control of the external memory unit is characterized in that access to the external memory is prohibited when it is determined that the external memory unit is not copied.

[Action]

When the external memory unit is attached to the information processing device,
The memory switching means outputs a second switching signal. Therefore, the second character data in the external memory is read, and the display control means causes the display means to display the second character data.

Thereafter, the memory switching output outputs a first switching signal,
Therefore, the validity determination program stored in the internal memory is executed by the information processing means. At this time, the first and second character data are compared in accordance with the program, and when both have a predetermined relationship, the memory switching means outputs a third memory switching signal. Therefore, access to the external memory by the information processing means is permitted.

When the first and second character data do not have the predetermined relationship, the memory switching means does not output the third switching signal, and in this case, the information processing means is prohibited from accessing the external memory.

〔The invention's effect〕

According to the present invention, since the first and second character data are compared, it is possible to effectively eliminate copy products that could not be eliminated by the above-described third method.

In addition, since the second character data is displayed in the first method and the fourth method, it is possible to pursue trademark infringement or the like by the display.

In contrast to the second method, the second character data stored in the external memory is displayed prior to the comparison of the two character data, so that even if the first and second character data do not match, the operator or The user can easily know why the external memory cannot be used.

Further, according to the present invention, before the comparison of the character data is determined to be valid, the memory switching means can access the internal memory and can access the memory area corresponding to the second character data stored in the external memory. When it is determined that the character data is valid, the memory switching means makes only the external memory accessible, and when it is determined that the comparison of the character data is not valid, the memory switching means does not output the third switching signal. Since the access to the memory itself is prohibited, unlike the fourth method, the protection function is not invalidated.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

FIG. 2 is a perspective view showing an example of a portable liquid crystal game device to which the present invention can be applied. The portable liquid crystal game device (hereinafter, simply referred to as “game device”) 10 includes a case 12, and an upper surface of the case 12 has an LCD panel 1 on which display segments are arranged in dots according to a dot matrix system.
4 are provided.

An insertion port (not shown) is provided in the upper portion of the rear surface of the case 12, and an external ROM cassette 16 (third
Figure) is detachably mounted. An external ROM 16a (FIGS. 3 and 6) is built in the external ROM cassette 16, and game program data is stored in the external ROM 16a as described later in detail. Therefore, when the external ROM cassette 16 is mounted on the game apparatus 10, if the external ROM cassette 16 is legitimate or legally permitted, the game program is executed and the LCD panel 1
The image for the game is displayed on 4.

A cross key switch 18 for operating the game character displayed on the LCD panel 14 in this manner is provided on the upper surface of the case 12. The cross key has four directions, and any of them can be pressed to move the game character up or down or left or right.

Referring to FIG. 3, the external ROM cassette 16 described above
CPU 2 built in case 12 by pin connector 20
Connected to 2. The CPU 22 includes a CPU core 24, which is connected to the 32-pin connector 20 by respective buses 26a, 26b and 26c. Therefore, when the external ROM cassette 16 is mounted, the CPU core 24 and the external ROM cassette 16
Are connected.

As described in detail in FIG. 4, the CPU core 24 includes 8-bit registers A, F, B, C, D, E, H, and L in addition to the program counter PC and the stack pointer SP. Register A is an accumulator and register F is a flag register. Using 4 bits out of 8 bits, F1 (carry), F2 (half carry), F3 (negative) or
F4 (0 flag) can be represented. Register B and
C, D and E, and H and L, depending on their combination, can be used as 16-bit registers.

A key matrix such as the cross key switch 18 shown in FIG. An internal RAM 28 and an internal ROM 30 are provided in association with the CPU core 24. Internal ROM 30 is a memory switching circuit
Accessed by CPU core 24 only when selected by 32.

Here, the memory space and the storage data of the internal memory 30 and the external memory cassette 16 will be described in detail with reference to FIG. The internal memory 30 has an address “0000” corresponding to a relatively small memory space (first memory space).
H to 00FFH ". The lowermost" H "of the address indicates hexadecimal notation. The first memory area includes a trademark" Nintendo ". First character data to be displayed and validity determination program data for implementing the validity determination program shown in the flowchart of FIG. 1 are stored.

On the other hand, the external ROM cassette 16 is formed by housing an external ROM 16a in a case. A memory space of the external ROM 16a has a second memory area designated by an address “0000H to 00FFH” corresponding to the first memory space. It is divided into a third memory area (second memory space) specified by addresses “0100H to 7FFFH”. Then, the second character data identical to the first character data is stored in an area from the address “0100H” to several bytes in the third memory area,
Desired program data for the game is stored in the remaining area. Preferably, in a few bytes after the second character data storage area, auxiliary data such as a maker code and a game name are stored, and complement data of the auxiliary data is stored. This complement data is used in the processing shown in step S17 of FIG. If the capacity of the program data for the game is large, the second memory area (“0000H to 00FFH”) of the external ROM 16a may be used.

The CPU core 24 outputs display data to the LCD controller 38 via the line buffer 36 under the control of the DMA controller 34. Then, the LCD controller 38
It is connected to a display RAM via a RAM interface. Although not shown, the display RAM 42 includes a character RAM and
Including VRAM. Therefore, the LCD controller 38 converts the display data output from the CPU core 24 into an LCD drive signal from the display RAM 42. That is, the display data from the CPU core 24 designates the address of the character RAM and VRAM, and a character (or object) signal and a background (background) signal are output from the character RAM and VRAM. The signal is synthesized by 38 to become an LCD drive signal.

Then, the LCD drive signal is given to the LCD common driver 46 and the LCD segment driver 48 via the LCD drive signal buffer 44. Therefore, an image is displayed on the LCD panel 14 by the LCD common driver 46 and the LCD segment driver 48 in accordance with the display data from the CPU core 24.

A luminance volume 50 is provided, and the luminance volume 50 is connected to the LCD buffer amplifier 52.
4. The brightness on the top can be adjusted.

Further, as shown in FIG. 4, a chip select signal CS1 or CS2 is output from the memory switching circuit 32. The reset signal from the reset circuit 54 is supplied to the CPU core 24 and the memory switching circuit 32. This reset signal is output when a power switch (not shown) is turned on, so that the CPU core 24 and the memory switching circuit 32 are reset at that time. Then, a read signal RD and a write signal WR are output from the CPU core 24, and the signals are appropriately input to the external ROM cassette 16, the internal RAM 28, the internal ROM 30, and the memory switching circuit 32. Further, an address decode signal described later is supplied to the memory switching circuit 32 via the address decoder 33.

As shown in FIG. 5, the memory switching circuit 32 includes an RS flip-flop 56, and its set input S has a signal D0, a write signal WR and a detection signal of address data "FF00H", that is, an address decode signal (however, The lowest “H” is 16
AND gate that receives three signal inputs
Given 58 outputs. Signal D0 is the least significant bit of the data. The decoded signal of the address data "FF00H" is that all of the bits A0 to A7 of the address data are "0" (that is, the lower two digits are "00" in hexadecimal notation).
And that all of the bits A8 to A15 are "1" (that is, 16 bits).
When there is an output of an AND gate for detecting that the upper two digits are "FF" in hexadecimal notation, the address is given from the address decoder 33. A reset circuit 54 (fourth input) is connected to the reset input R.
Reset signal RES from FIG. Then, the non-inverted output Q is inverted by the inverter 60 and applied to one input of the AND gate 62, and
64 input to one input. The other input of the AND gate 62 is supplied with a decode signal of address data “0000H to 00FFH”. The other input of the OR gate 64 is supplied with a decode signal from the address data "0100H" to an address corresponding to the number of bytes storing the second character data. The decode signals of the address data "0000H to 00FFH" are the inverse of the OR of the bits A8 to A15 of the address data, and the decode signals from the address data "0100H" to the address corresponding to the storage byte number of the second character data are This is OR of address data A8 to A14. Then, the output of the OR gate 64 is provided as an input of the AND gate 66 together with a decode signal of the address “F7FFFH” which is the inversion of the address data A15. The outputs of the two AND gates 62 and 66 are the above-described chip select signals CS1 and CS2, respectively.

When a power switch (not shown) is turned on, a reset signal is output from the reset circuit 54, and thus the RS flip-flop 56 is reset. Therefore, the non-inverted output Q becomes “0”. Therefore, then, CPU core 2
If the address data from 4 is up to “00FFH”, the chip select signal CS1 is output from the AND gate 62.

The chip select signal CS2 from the AND gate 66 is output as “1” when the address data is “0100H” or later. Therefore, when the chip select signal CS1 is being output, the memory space indicated by the diagonally upward slanted line in FIG. 6 can be accessed by the CPU core 24, the first character data can be read from the internal ROM 30, and the chip select When the signal CS2 is output, the portion from the address “0100H” to the address corresponding to the number of bytes storing the second character data in the memory space indicated by the diagonally downward slanted lines in FIG. Access to external ROM cassette 16
The second character data stored after the address “0100H” can be read.

On the other hand, when memory switching is performed, a write signal WR is output from the CPU core 24 and the data bit D0 of the address “FF00H” is output.
Is stored, the output from the AND gate 58 becomes "1" at that timing, and the RS flip-flop 56 is set. Therefore, the non-inverted output Q is "1".
Since the AND gate 62 is deactivated, the chip select signal CS1 becomes "0" and the chip select signal CS2 from the AND gate 66 becomes "1". However, when the address data exceeds “8000H”, the chip select signal CS2 becomes “0”. Therefore, before and after the memory chip is switched by the memory switching circuit 32,
In FIG. 6, the memory configuration is as shown by hatching. That is, when the chip select signal CS2 is being output, the addresses “0100H” to “7FFFH” of the external ROM cassette 16
The program data stored until now can be executed.

Note that the character RAM, VRAM, various registers, and the internal RAM are always accessible by the CPU core 24 because the chip select CS1 and CS2 are not input.

Next, the operation of this embodiment will be described with reference to FIG. 1 and FIGS. 7 to 9.

Initial settings are made in steps S1, S3, S5 and S7 in FIG. That is, in step S1, the CPU core 24
The stack pointer register SP (FIG. 4) is set to a predetermined value, and the address "8000" is set in step S3.
H to 9FFFH ", that is, the display RAM 42
Clear Then, in step S5, various registers for a sound circuit (not shown) are initialized, and in step S7, a BG (Background) palette is set.

In the following step S9, the address data “0100H
. "In response to the application of" .about. "
32, the chip select signal CS2 is output and the external ROM
The second character data is read from the cassette 16 and the character data is stored in the character R included in the display RAM 42.
Transfer to AM. At this time, specifically, in order to realize an easy-to-see display with a small amount of character data by enlarging the display twice or more vertically and horizontally, the data is transferred while performing enlargement calculation processing. Then, in step S9, the character data transferred while being enlarged is transferred to the VRAM included in the same display RAM so that the display position becomes a predetermined position. In step S13, the BG palette initialized in step S7 is controlled to display the second character data read from the external ROM cassette 16 on the LCD panel 14 for a predetermined time while scrolling the background. I do. In this way, the character data shown in FIG. 7A is enlarged and displayed twice vertically and horizontally as shown in FIG. 7B.

Since such enlargement processing can be easily realized by controlling the character RAM, a detailed description thereof is omitted here. However, the character data shown in FIG. 7A may be displayed as it is without performing the enlargement processing.

Next, in step S15, the first character data “Nintendo” stored in a predetermined area of the internal ROM 30 is compared with the second character data “Nintendo”. Specifically, in step S151 in FIG.
The first address of the first character data of the internal ROM 30 is set in the register group HL of the core 24,
In step S152, the external ROM is stored in the register group DE.
The start address of the second character data of the cassette is set. Then, as in step S153, it is compared whether or not the character data specified by the address data loaded in the two registers completely match, and if they match, in steps S154 and S155, the respective register groups HL and DE are registered. Is incremented, the same comparison operation is repeated until the register group HL reaches the final address + 1 in step S156. If a mismatch occurs, the process enters the prohibition process of step S21.

When the comparison of the first and second character data in step S15 is completed, in step S17, the external R
A complement check is performed based on auxiliary data such as a maker code and a game name stored in the OM 16a in advance.
Then, if the complement check does not match, the process proceeds to the prohibition process in step S21, as in the previous step S15.

If the two comparison operations in steps S15 and S17 show that the first and second character data and their complements match, in step S19, the CPU core 24 outputs a write signal WR. Accordingly, as described above with reference to FIGS. 5 and 6, RS flip-flop 56 of memory switching circuit 32 is set, and thus chip select signal CS2 is output. Therefore, after this step S19, the game program data stored at the address “0100H to 8000H” of the external ROM cassette 16 is read out and can be executed.

Also preferably, the two comparison steps S15 and S17
If a mismatch is detected in any of the above, the CPU core 24 executes the prohibition process of step S21. Specifically, as shown in FIG. 9, in steps S211 and S212, BG
(Background) Write "white" and "black" on the pallet, and drive the LCD panel 14 for a certain period of time controlled by a timer. That is, in this embodiment, the first
And if the second character does not match, LC
The entire D panel 14 flashes or flashes, thereby informing the operator or user that the external ROM cassette currently mounted is incompatible.

At this time, in step S9, the second
Since the character data is already displayed, the operator or the user can easily know the reason why the external ROM cassette has become incompatible.

Further, as can be clearly understood from FIG. 9, this prohibition processing routine does not return to the main routine of FIG. 1, so that the bank switching as in step S19 is also prohibited thereafter, Use of the ROM cassette is completely denied.

In the above-described embodiment, since a registered trademark such as "Nintendo" is displayed as the first and second character data, in the case of an external ROM cassette which is copied so that both coincide with each other, Can be pursued as trademark infringement.

In the above-described embodiment, whether the first character and the second character are completely matched or not matched is determined. However, if the first and second characters are set in a predetermined non-identical relationship, the first
It may be determined whether the second character and the second character have such a predetermined relationship.

Further, in the prohibition processing routine shown in FIG. 9, the blinking is merely repeated, but the nonconforming display may be displayed more positively.

[Brief description of the drawings]

FIG. 1 is a flowchart showing the operation of one embodiment of the present invention. FIG. 2 is a perspective view showing an example of a game device to which the present invention can be applied. FIG. 3 is a block diagram showing the overall configuration of the embodiment shown in FIG. FIG. 4 is a block diagram showing a part of FIG. 3 in detail. FIG. 5 is a circuit diagram showing the memory switching circuit in detail. FIG. 6 is a memory map schematically showing an address space accessible by the CPU core. FIGS. 7A and 7B are illustrative views showing examples of character data to be displayed. FIG. 8 is a flowchart showing an operation for comparing the first and second character data. FIG. 9 is a flowchart showing the operation of the prohibition process when there is a mismatch. In the figure, 10 is a game device, 14 is an LCD panel, 16 is an external ROM cassette, 24 is a CPU core, 30 is an internal ROM, and 32 is a memory switching circuit.

Claims (1)

(57) [Claims] 1. An external memory unit having a built-in external memory and configured to be detachable from an information processing apparatus, and program data stored in the external memory by display means when the external memory unit is mounted. In an information processing system including an information processing device capable of displaying a predetermined image according to the above, a copy protection system of an external memory unit, wherein the information processing device is capable of accessing a predetermined maximum address space And a first memory area corresponding to a first memory space relatively smaller than the maximum address function, wherein first character data for preventing copy of the external memory unit and the first character are included. A validity determination program for determining the validity of the external memory unit based on data; An external memory of the external memory unit, the external memory having a memory space corresponding to the first memory space, and a relatively large second memory space. The third with
A second character data having a predetermined relationship with the first character data stored in the internal memory in a part of the third memory region of the external memory; The program take for displaying an image corresponding to a predetermined purpose of use is stored in at least a remaining memory area of the third memory area of the external memory, and the information processing apparatus further accesses the internal memory. A first switching signal for enabling, a second switching signal for enabling access to a memory area corresponding to the second character data stored in the external memory, and only the external memory. Memory switching means for selectively outputting a third switching signal for enabling access, and the second key stored in the external memory Display control means for displaying lacquer data by the display means, the information processing means, when the external memory unit is mounted, causes the memory switching means to output the second switching signal, After the second character data is displayed on the display means by the display control means, the first switching signal is output to the memory switching means, and the validity determination program data stored in the internal memory is output. And determining whether the first character data and the second character data are in the predetermined relationship, based on the first and second character data. 3 to output the switching signal to allow access to the external memory. When it is determined that the external memory is not in the predetermined relationship, the external memory A copy protection system for an external memory unit, wherein access to the external memory unit is prohibited.