FI105000B - Electronic hand-held game machine - Google Patents

Description

Handheld Electronic Gaming Machine 105000

Field of the Invention

The invention relates to a hand held electronic gaming machine.

5

Background and Summary of the Invention

As Japanese Utility Model 57989/1986, April 18, 1986, attests, liquid crystal display games are well known in the art. In this game, a game cassette that can be attached to a main body includes a game program and a user interface program to be executed by the central processing unit within the chassis. The main body also includes a liquid crystal display system ("LCD"). The present invention provides a unique method and device for preventing the use of illegal game cartridges in such a system. In this way, the use of illegal game cartridges containing copied or poor quality programs can be prevented in the system. In addition, poor quality game cartridges that can destroy the main body over time 15 (e.g., connectors) can be prevented from being used in the system. Methods known to prevent unauthorized or copied programs from being run on an information processing device are known. One such system is disclosed in Japanese Patent Publication No. 17849/1972, published May 18, 1972. This system discloses a first method of associating a first password with a particular information processing system to separate it from other information processing systems. The first password is compared with the second password associated with the diskette on which the program is stored. Floppy disk use is; only allowed when both passwords are identical. Another method is disclosed in U.S. Patent 4,462,076, issued July 24, 1984. In this method, the copyright holder information is stored in the main memory unit and cassette memory. Such information is compared, and if it is compatible, the copyright owner's data is simply displayed and then the program stored in the cassette memory can be executed. The third method is disclosed in Japanese Patent Publication No. 18074/1984, issued April 25, 1984. In this procedure, copy protection information such as a trademark is stored in a plurality of semiconductor memories, and when * the printed circuit board to which the program is copied is used, the copy protection information is sampled by a cathode ray tube, exposing the copier to any trademark infringement claim. The third method is clearly ineffective when the copier destroys or exchanges the anti-copying information in order to avoid the 2,105,000 trademark infringement issues. The first and second methods are similar in that they both permit the use of a diskette or cassette, provided that the first and second identifiers are identical. However, the first method does not clearly indicate that the password is displayed. Thus, the first method does not disclose the presentation of copyright-related information as in the second method. In the case where the holder data in the main unit memory and the holder data in the cassette memory are not compatible, another method cannot use the cassette. However, since no holder data is provided in this case, the operator or user is not informed as to why the cassette cannot be used. In addition, if the comparison results show that the holder's data is compatible, no further checks will be performed to verify that the cartridge is legal. Therefore, it is a primary object of the present invention to provide a validation system for an external storage unit, where it is possible to more effectively prevent the illegal use of external storage units in a predefined information processing system such as a handheld electronic video game system.

The present invention relates to an electronic gaming machine according to claim 1, comprising an external memory unit having an external memory fixedly / removably coupled to an information processing device capable of displaying a predetermined image on display media according to a program stored in the external memory. The information processing device comprises 20 information processing means capable of entering a predetermined maximum memory space; an internal memory having a first memory space which is relatively much smaller than the maximum memory space and storing the first character data to prevent unauthorized access to the external memory and to determine the authenticity of the external memory unit of the authentication program data based on the first character data and memory selection means 25 for changing any internal memory and external memory. The external memory of the external storage unit has a second memory area having a memory space corresponding to the first memory space and a third memory area having a relatively larger second memory space. A second character data is stored in a portion of the third memory area of the external memory in a predetermined proportion to the first character data stored in the internal memory. In addition, a program for displaying the image according to a predetermined purpose (e.g., an interactive game) is stored in at least the remaining memory area of the third memory area. When the external storage unit is loaded into the information processing device, the memory selection means sets the first memory space to an address space that can be accessed by the information processing means. The information processing means then determine whether the first character data and the second character data have a predetermined relationship by executing a stored authentication program stored in the internal memory. If the first and second character data 5 have a predetermined relationship, the memory selection means selects the second memory space as an address space that the information processing means can access allowing them to access the external memory. As indicated above, when an external memory unit is loaded into an information processing device, the memory selection means selects the first memory space as an address space that the information processing means can access. Then, before any comparison operation, the second character data stored in the external memory 10 is displayed on the display means. The authentication program stored in the internal memory is then executed. The first and second character data are then compared with each other according to an authentication program, and when determining that both character data have a predefined relationship, the memory selection means selects the external memory as memory that the information processing means may have access to.

15

The information processing device is constructed as a handheld electronic gaming machine intended for use while being held between the player's hands. Such a handheld electronic gaming machine includes a handheld case; a first operating switch disposed where it can be operated with a left-hand thumb 20 on the front surface of the housing; a second operating switch positioned where it can be operated with a right hand thumb on the front surface of the case and a third operating switch located in an area where the imaginary intersection of the left and right thumbs is on the front surface of the case.

The directional control switch (particularly the lattice switch) used to determine the movement direction of the chip is tracked as described above with the first operating switch and the action buttons (particularly the push button switch) to determine the different type of action or movement of a chip. For example, pressing such a pushbutton switch may cause the chip to jump; using a weapon, throwing a ball, or the like. These first and second operating switches are usually used during the game. The first and second operating switches 30 are positioned where they can be easily operated during game play. The third operating switch described above may be, for example, a start-up switch for determining the start of a game and / or a selector switch for selecting a mode of playing the game. Such a third operating switch is located in the area where the imaginary intersection of the thumbs of both hands is located. Therefore, the third operating switch is located where it is easy to operate with the thumb of either hand. Thus, the third switch can be used while playing the game without the user having to change hands during the game.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of embodiments of the present invention, taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

Figure 1 is a perspective view showing an exterior casing of a gaming machine according to an exemplary embodiment of the present invention; Fig. 2 is a cross-sectional view taken along the line Π-Π in Fig. 3; Figure 3 shows an illustration of the positioning of switches or keys such as the on / off switch, selector switch 15, etc., in the embodiment of Figure 1; Figure 4 is a block diagram showing the electronic components of the embodiment of Figure 1; Fig. 5 is a block diagram showing the main part of Fig. 4 in more detail; Fig. 6 is a circuit diagram showing an exemplary memory selection circuit as shown generally in Fig. 5; Figs. 7 (A) -7 (D) are a memory map illustrating memory states that may be accessed by a central processing unit; Figures 8 (A) and 8 (B) illustrate examples of character data to be displayed; FIG. 9 is a flowchart illustrating a sequence of authentication operations controlled by the processing system shown in FIG. 4; Fig. 10 is a flowchart showing a sequence of operations for comparing a first character data with a second character data; FIG. 11 is a flowchart illustrating the order of operations in the ban process when the first character data and the second character data are incompatible with each other; Fig. 12 shows a key matrix for detecting key or switch input; Figure 13 is an example of a memory map of character RAM; Figure 14 is an example of a VRAM memory map; Figures 15 (A) through 15 (L) of 105000 are embodiments of various addressable registers associated with a liquid crystal display driver.

DETAILED DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an exterior of an exemplary handheld liquid crystal display casing according to an exemplary embodiment of the present invention. This handheld liquid crystal display gaming machine (hereinafter referred to as a "gaming machine") includes a housing 12 provided with a liquid crystal display panel 14 including small display segments tracked according to a dot matrix array on the front or top surface of the housing.

An interface port 68 (which is more clearly shown in Figure 2) is formed on the back or bottom surface of the housing 12 in a portion opposite to the liquid crystal display panel 14. The external ROM cassette is plugged into the interface port 68. Specifically, the 32-pin connector 20 is inserted into the interface port 68. By inserting the external ROM cartridge 16 into the connector port 68, the connector (not shown) 15 formed on the edge of the external ROM cartridge 16 printed circuit board is inserted and connected to the connector 20. removable to the game machine 10. The external ROM 16a (Fig. 5) is included in the external ROM cassette 16. The game program is stored in the external ROM 16a. When the external ROM cassette 16 is loaded into the gaming machine 10, the game program is executed such that the image is displayed on the liquid crystal display panel 14 and the music of the game 20 is generated through the earphones connected to the speaker 11 or jack 69. Enclosure 12 also includes a six-pin connector 65 for connecting the gaming machine to other machines using a suitable cable so that multiplayer competition is possible when external cartridges contain multiplayer game software. The lattice key switch 18 used to move the chip displayed on the liquid crystal display panel 14 is disposed on the front or top surface 25 of the housing 12 below the liquid crystal display panel 14 as shown in Figures 1 and 3. The lattice key switch 18 has four directional control presses; It is possible to move one of the chips up or down or left or right. Further, as shown in Figures 1 and 3, the pushbutton switches 70a and 70b are disposed on the front or rear surface of the housing 12 on the right side below the liquid crystal display panel 14. These pushbutton switches 70a and 70b are used when it is necessary to control the chip shown on the liquid crystal display panel 14 to perform various predefined functions. For example, when the pushbutton switch 70a is pressed, the character shown may show 61050.00 jumping, or when the pushbutton switch 70b is pressed, the character may appear to be throwing a rock or ball or firing various other objects. Thus, the lattice key switch 18 is disposed for use with the left hand thumb, which locks the housing 12 in cooperation with the right hand, and the pushbutton switches 70a and 70b are disposed for use with the right 5 hand thumb. Further, a start switch 72 and a select switch 74 are disposed on the front or top surface of the casing 12 of the gaming machine 10. As shown in Figure 3, the on / off switch 72 and the selector switch 74 are provided in an area 78 below the lattice key switch 18 and the push key switches 70a and 70b. Within this range is the imaginary intersection of the thumbs 76L and 76R of both hands. Therefore, these switches 72 and 74 are centrally disposed so that they can be operated by the thumb of either the left or right hand (while the left and right hand hold the housing 12 of the gaming machine 10). In other words, the switches 72 and 74 can be operated without significantly changing the position of the hands. The selector switch 74 is used, for example, to use the game mode shown using the menu screen. In this regard, the selector switch 74 may be used to select one of a plurality of game levels. In addition, the selectable "weapon" selection function of the chip 15 may be associated with the select switch 74. The start switch 72 is used to start the selected game. Therefore, it is usually not necessary to use the start switch 72 and the select switch 74 during the game. However, since the stop function (pause) is also associated with the stop switch 72, the stop switch 72 may be depressed to temporarily suspend the game. In order to start the game after such a pause, the start-switch 20 must be pressed again. The housing 12 is further provided with a power switch 1, the battery power level '; with light 13, contrast control 50, and volume control 66.

Referring to Figure 4, the external ROM cassette 16 described above is coupled to a central processing unit 22 housed in a housing 12 via a 32-pin connector 20. The central processing unit 22 includes a microprocessor 24 which may be exemplified by a commercially available microprocessor such as Z80. The microprocessor 24 is connected to a 32-pin connector 20 for timing. ' circuit 25a and control bus 26a, address buffer 25b and address bus 26b and data buffer 25c and data bus 26c, as well as working memory RAM or working memory 23. Therefore, when the external ROM cassette 16 is loaded into the gaming machine, the CPU 24 is connected to the external ROM cassette 16. As shown in more detail in Figure 5, the microprocessor 24 described above includes registers A, F, B, C, D, E, H and L, each of which is an 8-bit register except the program counter PC and the stack pointer SP, which are 16-bit registers. Register A has 7,105,000 batteries and Register F has the flag register. By using the 4 bits of the 8 bits of the register F, it is possible to indicate F1 (memory number), F2 (half memory number), F3 (negative) or F4 (zero flag). Registers B and C, D and E, and H and L can be combined and used as 16-bit registers. The central unit 22 preferably has an associated set of instructions which allows for multiple 8 and 16 bit transmissions between registers or register pairs, multiple 8 and / or 16 bit arithmetic operations (e.g., ADD, SUB, AND / OR, INC. DEC, etc.), multiple wrap / transfer operations (e.g., left / right rotation of particular register content), multiple bit control operations (e.g., setting a specific bit in a particular register), conditional and absolute branch operations, subroutine call and return operations, and multiple program control operations, e.g. -10 tys, no operation, etc.). Returning to Figure 4, a key matrix for detecting key input by a grid key switch 18 is coupled to microprocessor 24 via port 27. Figure 12 shows an example of a key matrix. Lines P10-P13 in Figure 12 correspond to the four inputs to port 27 and lines P14 and P15 correspond to the two output lines from port 27. The four inputs P10-P13 are connected to a predetermined bias voltage Vdd. 15 The presence or absence of a signal on lines P10-P15 is recorded in the addressable port register of the central unit (not shown). As will be readily apparent to those skilled in the art, the state of the porttire register can be used to determine the control function desired by the player. In this way, pressing of the grid key switch 18 can be detected on the central unit, resulting in movement of the character to the right, left, up or down. Also, pressing of the control switches 70a, 70b, 72 20 or 74 can be detected and cause an input to the microprocessor 24 via port 27 to perform appropriate control functions. Further pressing of the control switches shown in Figure 12 can be used to cause data transfer between gaming machines via a 6-pin connector, cable and conventional serial register transfer port for controlling the microprocessor 24 serial transfer controller 21, the interrupt controller 31 and 25 external ROM cassette 16. The purpose of such data transfer is to provide simultaneous multiplayer competition according to specific game programs stored in the external cassette 16. The microprocessor 24 is also coupled to the internal RAM 28 and the internal ROM 30. The microprocessor 24 can access the internal ROM 30 only when the internal ROM 30 is selected by the memory selection circuit 32 as will be described in detail below. The oscillate 30 toroidal circuit 24b supplies clock pulses in response to the crystal generator 24a. The clock pulse divider 24c provides one or more pulse frequencies controlled by the timer 24b. Referring now to Figures 7A-7D, the address space of an exemplary microprocessor and data stored in internal memory 30 and external memory cassette 16 will now be described in detail. As shown in FIGS. 7A and 7B, internal ROM 30 has a first memory area designated as "OOOOH-OOFFH" corresponding to the first relatively small memory space. "H" indicates that these addresses are expressed in hexadecimal numbers. The first is stored in the first character data for the purpose of the present-5, e.g., the trademark "Nintendo" and in the external memory the authentication program shown in the flow chart of Figure 9. The external ROM cassette 16 includes an external ROM 16a. As shown in Figures 7C and 7D, the memory space of the external ROM 16a is divided into a second memory area designated "OOOOH-OOFFH" (which corresponds identically to the addresses defining the first memory space 10 described above) and a third memory area (second address space) designated "0100H- 7FFFH ". In the properly assigned external memory cassette, the second character data (which is the same as the first character data) is stored in the area beginning at "OIOOH" in the third memory area. The game program is stored in the remaining area of the third memory area. Preferably, auxiliary data such as the manufacturer's identification code, game name, cassette type, memory size, etc., stored in a few bytes after the second character data storage area, is also stored in the auxiliary data (e.g., the sum of such data). Complement data is used during step S17, which will be explained later in connection with FIG. 9. Further, in the case of a high capacity required by the game program, a second memory area ("OOOOH-OOFFH") of the external ROM 16a may be used to store such program data for the game.

Returning to Figure 4, where the output of the microprocessor 24 is provided, display data is fed to the liquid crystal display controller 38 via line buffer 36 under the control of the DMA controller 34. LCD monitor controller 38 is coupled to monitor RAM 42 via LCD monitor interface 40 and control, address, and data slots. Although not shown in the figure, display RAM 42 includes 25 character RAMs and VRAM as generally shown in Figure 7. Detailed examples of memory maps of character-RAM and VRAM memory areas can be found in Figures 13 · and 14, respectively. The VRAM memory map example, as shown in Figure 14, includes 1024 blocks (32 x 32) of character code representing background display data. Although only 360 (18 x 20) 1024 blocks are displayed on the LCD screen at any particular time, the displayed selected area can be changed by changing the data to the LCD controller 38 in the horizontal and vertical scrolling registers (SCY and SCX). The liquid crystal display controller 38 operates to control the central processing unit 22 through various addressable control / status registers which are located in the central processing unit address space as generally shown in FIG. These registers include a liquid crystal display register, a liquid crystal display controller status register, a horizontal and a vertical scrolling register, a liquid crystal display vertical line identification register, and moving object and background palette data (e.g., 2 bits 1 for 4 color tones). The LCD register controls the nature of the display and the status register indicates the current status of the LCD controller. Each point of the background display data is accessible by changing the horizontal and vertical scrolling index data. The LY and LYC registers detect and control the vertical line on the screen to which data has recently been transferred using the graphics cards. The X and Y window location registers control the part of the LCD screen area or window where the target and background character data appear. Details of these registers and their functions can be found in Figures 15 (A) to 15 (L). Liquid crystal display control 38 converts the display associated with the data output from microprocessor 24 to a liquid crystal display control signal from the output display RAM 42. More specifically, display data from microcomputer 24 determines the character RAM and VRAM (video RAM) addresses so that the character (or 15) signal and the background signal is output from the character RAM and VRAM. The liquid crystal display controller 38 generates the corresponding liquid crystal display control signals.

Liquid crystal display control signals are applied to a liquid crystal display common controller 46 and a liquid crystal display segment controller 48 via a liquid crystal display control signal pouch 44. Therefore, by means of a common LCD display controller 46 and a liquid crystal display segment controller 48 20, the image associated with the data associated with the data from the microprocessor 24 can be displayed on the liquid crystal display panel 14. Specifically, the liquid crystal display panel may e.g. bogie 144 x 160 pixel or dot matrix, each with a unique unique "cut" common electrode / segment electrode combination. The common controller 46 for the LCD monitor, which controls the lines connected to the common electrodes, may be, for example, 25 Sharp LH 5076 F. These graphics cards receive data from the LCD control signal buffer 44, which indirectly receives data from the CPU to the monitor RAM. and via a liquid crystal display controller 38.

In addition, there is intensity level control 50, which is coupled to a liquid crystal display buffer amplifier 52 such that the intensity of the liquid crystal display panel 14 can be adjusted by user level intensity control.

As shown in Fig. 5, the semiconductor chip selection signal CS1 or CS2 is output from the memory selection circuit 32. The setup signal is output when the power switch (not shown in FIG. 105000a) of the gaming machine 10 is turned on and therefore microprocessor 24 and memory selection circuit 32 are initially set. Then, the read signal RD and the positioning signal WR are output from the microprocessor pad 24, which is suitably an input to the external ROM cassette 16, the internal RAM 28, the internal ROM 30, and the memory selection circuit 32. Further, as will be described later, the address decoding signal is provided to the memory selection circuit 32 via the address encoder 33. As shown in Figure 6, a memory flip-flop 32 includes an RS flip-flop 57. The RS-flip-flop 57 setting input 5 receives an output of the JA-port 59 which receives three inputs including signal DO, positioning signal WR, and detecting signal, i.e., "FFOOH". signal. The signal DO is the least significant bit of the FFOOH or 10 flown data. The decoded signal of the address data "FFOOH" is the output from the address decoder 33, the output of the JAJA port (not shown) indicating that all bits A0-A7 of the address data are "0", i.e. the two least significant bits in the hexadecimal representation are "00" not shown) output, which indicates that all bits A8-A15 of the address data are "1", i.e. the two most significant bits in the hexadecimal representation are "FF", 15 are both output. The setting input R of the RS flip-flop 57 is connected to the setting signal RES from the setting circuit 55 (Fig. 4). The non-inverting output Q of the RS flip-flop is then applied to one of the inputs of the JA port 63. A decoded signal indicating address data "OOOOH-OOFFH" is applied to the second input of the JA port 63. A decoded signal corresponding to a few bytes (in which the second character data is stored) starting from the address data 20 "OIOOH" is applied to the second input of the OR port 65. The decoded signal of the address data "OOOOH-OOFFH" is an inversion of the bit data A8-A15 of the address data processed by the OR port. The signal decoded from the address data "OIOOH" up to the number of bytes storing the second character data is the address data bits A8-A14 which are processed by the OR port. The output of OR port 65 is then used as the input of the AND port 67 along with the decoded signals of the address "7FFFH". inversion of bit AI 5. The outputs of the two JA ports 63 and 67 output the aforementioned semiconductor chip selection signals CS1 and CS2, respectively. In use, when the power switch (not shown in the figure) is turned on, the setting signal is output from the setting circuit 55, and therefore the RS flip-flop 57 is set. Therefore, the non-inverting output Q receives the value "0". In this case, if the address data from microprocessor 24 is previously 30 "OOFFH", the semiconductor chip selection signal CS1 is output from the JA port 63. The semiconductor chip selection signal CS2 from the JA port 67 is output "1" when the address data is "OOOOH" or greater: " Therefore, in the state where the semiconductor chip selection signal CS1 is output Π 105000, the memory space represented by the oblique lines rising to the right in Fig. 7 (B) can be accessed by microprocessor 24 and thus it becomes possible to read first character data internally from ROM 30. The output CS2, the memory space represented by the oblique lines to the right in FIG. 7 (C), can be accessed by the microprocessor 24 and thus makes it possible to read the second character data stored after the address "1001H" in the external ROM cassette 16.

On the other hand, in the case of memory swapping or selection, if the positioning signal WR is output from microprocessor 24 and "l" is stored in data bit DO at "FFOOH", output JA port 59 becomes "l" and thus RS flip-flop 59 is set. Therefore, the non-inverting output 10 lo Q becomes "0", the operation of the JA port 63 is disabled if the address data exceeds "OOFFH" and so the semiconductor chip selection signal CS1 becomes "0" and the semiconductor chip selection signal CS2 becomes JA "l". However, if the address data exceeds "8000H", the semiconductor chip selection signal CS2 becomes "0". Therefore, before or after the memory selection circuit 32 replaces or selects the memory semiconductor chips, the memory microprocessor 24 is constructed 15 as shown by oblique lines in Figure 7. That is, when the semiconductor chip selection signal CS2 is output, it is possible to execute "0100H-7FFF" stored program data. Additionally, the character RAM, VRAM, various control or status registers and internal RAM microcomputer 24 have access, since the semiconductor chip selection signals CS1 and CS2 are not required to access these memory slots.

Referring to Figures 8-11, the operation of a gaming machine according to one embodiment of the present invention will be described below.

·. As shown in steps S1, S3, S5 and S7 of Figure 9, the system is initialized. Specifically, the predetermined value in step S1 is placed in the microprocessor 24 stack pointer register SP (Fig. 5), in step S3 the memory area denoted by "8000H-9FFFH", i.e., the RAM 42 of the display 25 is reset. The various registers used by 58, 60, 62, 64 are provisionally set. In addition, in step 57, the BG (background) palette data is loaded into a palette register (not shown in the figure) included in the liquid crystal display controller 38 by a microprocessor according to the program data stored in the internal ROM 30. The palette data defines two bits of shade data to be added to the character data so that four different shades of tinted color data can be output to the LCD. In the next step S9, when the address data "OIOOH" is output from microprocessor 24 according to program data stored in the internal ROM 30, the semiconductor chip selection signal CS2 is the output of the memory selection circuit 32 described above in response to the second token data being read from the external 42 included in the interleaved RAM range. Hereby, the second character data of the display, which can be easily seen with small character data, is preferably transmitted while being processed to magnify the character, e.g., by twice the length and width of the LCD 14 panel 14. Then, to display the desired character in a predefined coordinate position 42 VRAM regions so that its screen position matches the predefined position in VRAM. Then, in step S13, the second character read from the external ROM cassette 16 is displayed on the liquid crystal display panel 14 for a predetermined period of time while the background is scrolled. For example, the "Nintendo" mark representing the registered trademark shown in Figure 8 (A) may be doubled in length and width as shown in Figure 8 (B). Because such a magnification process is easily accomplished by adjusting the character RAM, its detailed description is omitted here. Although the magnification process is recommended, if desired, character data as shown in Figure 8 (A) may be displayed as such without the magnification process.

Next, in step SI 5, after the character data is displayed, the first character data "Nintendo" stored in the predetermined area of the internal ROM 30 is compared with the character data "Nintendo". More specifically, in step 10 of FIG. 10, the initial address of the first character data of the internal ROM 30 of the SI51 is set in the re-20 register group HL of the microprocessor 24. In step S512, the initial address of the second character data of the external ROM cassette 16 is set in the register group DE of the microprocessor 24. Then, as shown in step S513, i determines whether the character data defined by the address data loaded into the two register groups HL and DE are fully and fully compatible with each other. If both character data are compatible with each other, in steps S154 and S155, the address data in the register-25 groups HL and DE are incremented, and then the same comparison operation is repeated until the value of the register group HL becomes "end address +1" in step S156. If not compatible. then no, in step 321 we go into the blocking process.

After completing your first and second character data comparison step5, as described above, the check operation is performed in step SI7 based on complementary data stored in external ROM 16a, such as ROM size or equivalent, manufacturer code, game name, cassette memory type (ROM or ROM and RAM) etc. In this respect, for example, all auxiliary data can be summed and computed as the complement of such an amount and stored as 13,105,000 complement numbers. Then, if a comparison between the complement number and the stored complement number is calculated, results in a mismatch, the blocking step of step S21 is taken. In the case where the first and second character data are mutually compatible and the complement data are also compatible in the comparison processes in steps S15 and S17, the microprocessor 24 in step S19 outputs an alignment signal WR. 6 and 7, the RS flip-flop 57 of the memory selection circuit 32 is set and thus the semiconductor chip selection signal CS2 is output. Therefore, after step S19, game program data stored in the addresses "0100H-8000H" of the external ROM cassette 16 can be read and executed. Thereafter, the internal ROM 30 is not selected and therefore no access to the list is possible with the microprocessor 24.

In the next step 20, the game processing function is started according to the program data of the external ROM 16a. Specifically, the microprocessor 24, in accordance with the program data stored in the third memory area of the external ROM 16a, transfers the background character (dot data) to the character RAM area included in the display RAM 42. At the same time, the background palette data and the character-15 code that defines the background character to be displayed and its display location on the liquid crystal display panel 14 are transferred to the VRAM area. Additionally, the microprocessor 24 reads single-character target character display codes, display coordinate data, and characteristic data from a third memory area of the external ROM 16a and transmits them to the liquid crystal display controller 38 via the DMA controller 34 and the line buffer 36. In response, the LCD monitor controller 38 performs a pro-20 process to display an image where the background character and target characters are joined to each other on the LCD screen panel 14. Specifically, composite data combining single * Then, the LCD monitor controller 38 consecutively points the point data controllers to match the slot positions in the row direction, i.e., the row selection data to the LCD segment controller 48 and the data for sequentially selecting the columns of the corresponding row to the common LCD controller 46. Points that both row and column are selected. That is, the data representing whether or not the corresponding pixels of the target and background mark are controlled are provided to the LCD segment controller 48 and the common controller 46 by the liquid crystal display controller 30 38 for displaying the composite image on the liquid crystal display panel 14. By repeating such operations "other dots with a contrast • density or contrast. Further, according to the selected combination of controlled points, the arbitrary character may be displayed on a liquid crystal display panel 14.

In addition, microprocessor 24 preferably performs a difficult S21 inhibitory process if mismatch is detected in either of the two comparison steps S15 and S17. Specifically, 5 as shown in FIG. 11, in steps S211 and S212, the microprocessor 24 writes "white" and "black" to the background palette and the liquid crystal display panel 14 is operated for a predetermined time controlled by a timer such as S213 and S214. In other words, in this embodiment, if the first and second character data are not compatible, the LCD panel 14 is completely turned on, off or flashed, informing the operator or user 10 that the external ROM cartridge loaded at that time is not legal. the second character data in the external ROM cassette 16a is shown in the previous step S9, the operator or user knows the reason is that the external ROM cassette is an illegal cassette Also, as shown in FIG. 11, the blocking process subroutine cannot return to FIG. the replacement step performed in step-15 at step S19 is then prevented and thus the illegal external ROM cassette cannot be used.

In the embodiment described above, a trademark such as "Nintendo" is further presented as second character data. In the case of an external ROM cassette, which is copied so that both character data are compatible, the manufacturer's trademark has been unlawfully used.

Further, in the embodiment described above, it was determined whether the first and second characters 20 were completely compatible or not. Alternatively, however, all you need to do is check whether the first and second character data are predefined: relationship.

In addition, the blocking treatment routine shown in Figure 11, as explained, repeats the flash of the liquid crystal display. However, if desired, a warning phrase may also be displayed stating that the 25 ROM cartridges installed at that time cannot be used on this Gaming Machine.

While the invention has been described in the context of what was considered to be the most practical and preferred embodiment in the present case, it is to be understood that the invention is not limited to the disclosed embodiment but is intended to cover various modifications and similar arrangements within the spirit and scope of the appended claims.

Claims *

Claims (7)

An electronic handheld gaming machine (10), to which belongs: a housing (12) of a size suitable for pouring into the hand and having a substantially rectangular shape, determined by a front, a back, two side surfaces, an upper side and a bottom, each side surface being longer than the top and bottom, and the casing being poured between the bed hands during the course of the game, and the company side having a higher surface portion tili joining a higher portion of each side surface, and a lower surface portion joining a lower portion of each side surface; characterized in that the gaming machine further hears a first control key (70a, 70b) located in the right section of the lower surface portion of the front of the housing so that it can be used with the player's right thumb located on the housing; a second control key (18) located in the left section of the lower surface portion of the front of the housing so that it can be used with the player's left thumb lying on the housing; a dot matrix liquid crystal display (14), associated with a screen defining a matrix of dot rows and columns in the higher surface portion of the front of the housing such that the screen is in use above the first control key (70a, 70b) and the second control key (18); an insertion portion (68) formed in the upper side of the housing and extending in use behind the dot matrix liquid crystal display (14) in the housing; An outer memory (16) which can be fixedly and releasably inserted into the insertion portion (68) from the top of the housing to store game programs and background figure data and figure data: for moving objects with which the game figures are displayed on the screen; game processing means (24) for reading game programs and background figure data and figure data for moving objects from the external memory (16) and for controlling the display of moving objects on the screen (14) in response to the use of the first control key (70a, 70b) and the second control key (18); and to control the display of background figures on the screen; ice 105000 means a connector (20) for coupling the outer memory (16) inserted in the insertion portion (68) to the game's data processing means (24); an enclosed memory connected to the game's data processing means (24) for storing background figure data and figure data for movable objects Read out of the external memory (16) by means of the data processing means and transmitted via the switch (20); enclosed screen signal production means for producing a screen signal for displaying background figures and moving objects on the base of background image data and moving object figure data stored in memory; a control unit (38) for controlling the dot matrix liquid crystal display in accordance with the screen signals produced by the screen signal production means, for displaying background figures and moving objects on the screen, the control unit having a first unit for controlling columns on the dot matrix liquid crystal display for controlling rows on the dot matrix liquid crystal display. Handheld gaming machine according to claim 1, characterized in that further there are third control key means (72,74) adapted in the middle section of the lower surface portion on the front of the housing, so that the third control key means are in use where the locations for the bed are used. the thumbs intersect at the front of the housing. Handheld gaming machine according to claim 2, characterized in that the third control key means (72, 74) comprise two keys, one of which is located at the right thumb position with the first control key (70a, 70b), and the other is located at - place the thumb with the second control key (18). * Handheld gaming machine according to claim 1, characterized in that the display (14) is located above and below the first control key (70a, 70b) and the second control key (18). Handheld gaming machine according to claim 4, characterized in that further there is also a rotary contact located in the vicinity of the dot matrix liquid crystal display on one side surface of the housing, for adjusting the contrast on the screen. Handheld gaming machine according to claim 1, characterized in that the data processing means (24) of the game include means which are sensitive to an connected external memory (16) 30 to indicate whether the connected memory is legal or illegal. 19 105000 Handheld gaming machine according to claim 6, characterized in that the game data processing means (24) further include means which are sensitive to the detection means to prevent the use of an illegal memory for executing a game program.