JP2707465B2 - Inverter device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device that converts DC to AC and outputs the converted AC.

[Conventional technology]

FIG. 12 is a circuit diagram of a conventional inverter device of this kind. In the figure, Q ₁ and Q ₂ are switching elements such as transistors driven by input signals from the A terminal and B terminal, respectively, and Q ₃ and Q ₄ are MOSFETs and the like connected to the primary winding N of the output transformer T. In the switching element, a center tap is provided in the primary winding N of the output transformer T, and a DC power supply V _CC is connected to the center tap. C ₁ is a capacitor connected to the secondary winding S of the output transformer T, load 1 of CFL or the like through the capacitor C ₁ is connected. R ₁ and R ₂ are resistors.

The circuit having the above configuration is a separately-excited inverter circuit. Terminals A and B are for controlling rectangular waves having a frequency of, for example, several tens of KHz and being 180 ° out of phase with each other from an external circuit such as a CPU or a dimmer circuit. Each signal is continuously input. As a result, the switching elements Q ₃ and Q ₄ connected to the primary winding N of the output transformer T also repeat on (ON) and off (OFF), and an alternating current is generated in the secondary winding S of the output transformer T, This alternating current is supplied to the load 1. At that time, the output transformer T
And a capacitor C ₁ form a tank circuit,
The resonance frequency and the frequency of the control signal from the external circuit are matched so that the output is maximized, so that a stable power supply is supplied to the load 1. No.
FIG. 13 shows a voltage waveform at both ends of the load 1.

[Problems to be solved by the invention]

However, in the conventional inverter device as described above, the frequency of the control signal input from the outside and the resonance frequency of the tank circuit formed by the output transformer and the capacitor cannot be perfectly matched due to the variation in the inductance of the output transformer. If the input control signal from the outside is a rectangular wave, the voltage applied to the load becomes a differential waveform of the rectangular wave, and a high voltage is applied to the load temporarily, and the efficiency of the load is reduced. There was a problem that optimal control could not be performed.

The present invention has been made in view of such a problem, and an object of the present invention is to provide an inverter device that is efficient and capable of optimally controlling a load.

[Means for solving the problem]

The inverter device according to the present invention is configured as follows.

(1) In an inverter device for converting a direct current input to a primary side of an output transformer into an alternating current by driving a switching element and outputting the alternating current from a secondary side of the transformer, an oscillation signal for driving the switching element and an output transformer Comprising frequency control means for matching the resonance frequency of the resonance circuit formed by: a switch, a counter for counting up and counting down,
It has a PWM signal generator that generates a PWM signal, the counter up-counts or down-counts by the switch, and generates a pulse generated by the PWM signal generator in accordance with the output of the counter within a certain period, The dimming pulse was obtained by stopping the oscillation or oscillating the stopped pulse.

(2) In the inverter device according to (1), the frequency control means includes a plurality of counters and a PWM signal generator, and each of the PWM signal generators varies a pulse ON period and the fixed period. Was.

[Operation] In the inverter device of the present invention, since means for matching the frequency of the oscillation signal from the outside with the resonance frequency is provided, efficient control of the load can be performed efficiently.

〔Example〕

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, reference numeral 1 denotes a load, 2 denotes an output circuit (a booster circuit) having a built-in output transformer and a switching element, and converts a direct current input to the primary side of the output transformer into an alternating current by driving the switching element, and Output to load 1 from the secondary side. 3 is a CPU (Central Processing Unit) for outputting a drive pulse for driving the switching element, 4
Is a VCO (voltage c) that outputs a clock (CK) to this CPU3.
5 is a variable resistor that changes the output frequency of the VCO4. An oscillation signal (drive pulse) for driving the switching element of the output circuit 2 and a resonance frequency of an LC resonance circuit formed by an output transformer and a capacitor. Are provided as frequency control means for matching (matching)

The output circuit 2 has the same configuration as that of the circuit in FIG. 12, and a drive pulse of a continuous rectangular wave having a frequency of, for example, 10 KHz as shown in FIG. Is input in a shifted state. Then, the switching element is driven by the driving pulse, and the direct current input to the primary side of the output transformer is converted into an alternating current and output to the load 1 from the secondary side of the transformer.
At that time, the variable resistor 5 is manually adjusted while measuring the output voltage of the output circuit 2 so that the output voltage is maximized.

As described above, the frequency of the driving pulse output from the CPU 3 to the output circuit 2 is changed by the variable resistor 5 to match the frequency of the resonance circuit, so that even if the inductance of the output transformer varies, the load can be efficiently loaded. 1
Optimal control can be performed.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In the embodiment of FIG. 1, the matching is performed manually. However, the matching may be shifted due to a change in impedance due to the aging of the element or a change in the surrounding environment. Therefore, in this embodiment, the frequency is automatically adjusted. Like that. That is, the output voltage of the output transformer is constantly detected by the voltage detection circuit 6, and the frequency is automatically adjusted so that the output voltage becomes maximum.

The detection signal output from the voltage detection circuit 6 is A / D
The signal is input to a converter (analog / digital converter) 7, where it is converted into a _digitized signal V _INCPU.
Output to CPU3. The CPU 3 _stores the voltage level V ₁ of the signal V _{INCPU in} the internal memory, and then steps one step from the signal V _OUTCPU to the VCO 4 input through the D / A converter (digital / analog converter) 8 when the power is turned on ( One step is, for example, a frequency conversion to several hundred Hz. The increased signal is input to the VCO 4 and input to the CPU 3 as a clock. Then, the signal V _INCPU from the voltage detection circuit 6 is _changed to A /
Input via the D converter 7. At this time, comparing the voltage level of the current signal and the voltage level V ₁ of the previous signal, V ₁
<Data V ₁ is erased from the internal memory if V _2, newly storing the data of V _2. Repeat the above operation, compare the voltage level one step before and the current voltage level, and input the signal of the previous voltage level to VCO4 only when the current voltage level is lower or equal to the previous voltage level Then, the output signal _VOUTCPU from the CPU 3 is fixed.

Thus, the resonance frequency f ₀ between the drive pulse output from the CPU 3 and the resonance circuit (tank circuit) in the output circuit 2
Detecting a signal V from the CPU3 voltage level V ₀ which at that time
_By inputting _OUTCPU to VCO4, the above-mentioned matching can always be perfectly achieved. FIG. 4 shows the relationship between the level (V) of the detection voltage and the clock frequency (f) of the CPU 3.

A series of operations for detecting the frequency f _0, reset the CPU 3, that is, when the power rising is performed each time. When decreasing the current supplied to the load 1, for example, when the load 1
In the case of a discharge tube of L or the like, a drive pulse whose oscillation has stopped halfway during dimming is input from the CPU 3 to the output circuit 2. In this case, if the automatic adjustment of the matching is performed, the matching is largely shifted. To prevent this, the signal _VOUTCPU from the CPU 3 is always fixed during dimming.
However, at the time of maximum output, since the resonance frequency f ₀ gradually over time change of elements as described above varies, the signal V which is once output to a predetermined time, for example several tens of minutes to several hours
Compare _OUTCPU . If there is no change, the first routine operation is executed again after a predetermined time. But,
If there is a change, the memory is rewritten with the data of the new signal V _OUTCPU and fixed, and after the end of the second routine operation, the first routine operation is executed.

FIG. 5 is a block diagram showing a third embodiment of the present invention. In this embodiment, as in the embodiment shown in FIG. 3, the frequency adjustment is automated.
The frequency is automatically adjusted so that the input DC current flowing from the output circuit 2 to the output circuit 2 becomes maximum. In the figure, reference numeral 10 denotes a current detection circuit for detecting the input DC current, and a detection signal is input to a CPU (not shown) via an A / D converter 7. And
The same operation as that of the embodiment shown in FIG. 3 is executed by this CPU, so that the matching can always be completed completely.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention. This embodiment is configured as a lighting device for lighting a discharge lamp 11 such as a CFL as a load, and is basically the same as the circuit in FIG. 3 except that a center tap of a primary winding N of an output transformer T is provided. A coil L having an inductance sufficiently larger than the inductance of the primary winding of the transformer T is interposed between the coil L and the DC power supply (V _CC ). Further, the voltage detection circuit 6 is composed of a rectifier diode D ₁ and smoothing capacitor C _2.

Drive pulse initially set inside CPU3 (see Fig. 2)
Is input to the output circuit 2 from the X terminal and the Y terminal, and the power supply (V
_DD ) are input to the gates of FETs Q ₅ and Q ₆ , which are switching elements, via buffers 12 and 13 connected to the respective elements. As a result, a boosted AC is generated on the secondary side of the output transformer T, and is supplied to the discharge lamp 11, which is a load. FIG. 7 shows signal waveforms at various parts in FIG.

Here, when there is no coil L on the primary side of the output transformer T, the power is directly supplied to the center tap of the transformer T.
Since V _CC is supplied, the voltage waveform between the drain and ground (GND) of each of the FETs Q ₅ and Q ₆ becomes a rectangular waveform as shown in FIG. 7 (c). And B on the secondary side of the output transformer T
The waveform between the point and the ground also exceeds the predetermined value when the drive pulse rises and falls as shown in FIG. For this reason, a large voltage is temporarily applied to the discharge lamp 11, a rush current flows, and the life is shortened. However, in this embodiment, since the coil L is connected to the primary side of the output transformer T, the rectangular wave is shaped into a sine wave on the primary side of the transformer T. That is, when the coil L is present, the FETs Q _5, the drain of Q ₆ - voltage waveform between the ground, the center tap of the voltage waveform of the output transformer T, B point - Figure 7 respectively shows the voltage waveform between the ground (d) , (E) and (f).

Next, the circuit operation when the coil L is provided will be described in detail with reference to the circuit diagram of FIG. First, the output transformer T is assumed to primary and secondary sides are taken completely matched to the capacity of the transformer primary and C _P. The impedance of the discharge lamp load is Z, the inductance of the transformer primary side is L _P , the inductance of the secondary side is L _S, and the part of the inductance L _{P on} the FETQ ₅ side is L _P1 , FE
The minutes of the TQ ₆ side is referred to as L _P2. When the switch SW ₂ (FETs Q ₆ of FIG. 6) is first turned on, D point of Figure 8 becomes the ground level, the tank circuit with the inductance L _P and a capacitance C _P is formed. At this time, the inductance L _{L of the} coil L is a sufficiently large value (L _L ≫L _P1 , L _L ≫) compared to L _P1 and L _P2.
Since a L _P2), the potential at the point E gradually increases as the charge on C _P is charged as shown in FIG. 9, and reaches the voltage saturation point P, the potential at the point E is gradually Decrease. Then, the switch SW ₁ (first 6 Figure FETs Q ₅₎ and the switch SW ₂ is reversed at the time when the potential of the point E becomes zero, the switch SW ₂ is turned off switch SW ₁ is turned on. This switch SW ₁
SW ₂ is repeatedly turned on and off.
Since the coil L is interposed between the center tap and the power supply, the potential at the point E has a sine waveform as shown in FIG. Here, one cycle of oscillation and T _a, and the period of the drive pulse input to the output circuit 2 from the CPU 3, the period T _a would have matched.

FIG. 10 is a circuit diagram showing a fifth embodiment of the present invention, and shows a circuit configuration of a dimmer for controlling dimming of a load such as a discharge lamp. This shows a case where frequency control means is configured. In the figure, 14
Is a dimming switch composed of an up switch 14a and a down switch 14b, and 15 and 16 are first PWMs (pulse widths m) counted up and down by the switch 14.
odulation) up / down (U / D) counter and second PW
M up / down counters 17 and 18 are first PWs that generate PWM signals based on the outputs of the up / down counters 15 and 16.
M signal generator and second PWM signal generator, 19 to 24 are AND gates, 25 is an inverter (inverter), and 26 and 27 are OR gates. The other configuration is the same as that shown in FIG.

In the dimming circuit having the above configuration, at the time of normal power-on,
The basic pulse from the first PWM generator 17 shown in FIG. 11 (a) is output through the OR gates 26 and 27, and this basic pulse is used as a driving pulse of the switching element by the X of the output circuit.
Input from the terminal and the Y terminal (see FIG. 6). The basic pulse is a rectangular wave pulse of period T _k, the ON period (T _b)
And the off period are equal and 1: 1. At this time, the output is maximum.

Here, when the down switch 14b of the dimming switch 14 is turned on, the level of the down signal _SD1 is set to the H (high) level, and the first counter 15 sets the initial value (for example, in hexadecimal notation). When the the FFH) intended to make countdown by 1H, the countdown signal is input to the first PWM signal generator 17, as shown in FIG. 11, the oN period at a fixed period T _D in T _b is 1T _b amount corresponding light tone oscillation is stopped pulsed X _1, Y ₁ is output for one count. As a result, the load such as the discharge lamp is brought into a normal dimming lighting state. On the other hand, the down signal S _D1
Although input from one input terminal of for other input terminal L (low) level of the AND gate 20, that is, the output signal D ₀ of the first counter 15 is at the L level, the down signal S
_D1 is not input to the second counter 16 and the second PWM signal generator 18. Then, the down switch 14b is kept depressed, and the first counter 15 continues to count down, for example, when it reaches a set value 03H, the output signal D of the first counter 15
₀ changes from the L level to the H level, and this H level signal D ₀ is input to the other input terminals of the AND gates 19 and 20. Therefore, the H-level signal _SD2 output from the AND gate 20 is input to the second counter 16. At the same time, the output signal D ₀ of the first counter becomes the H level is input to the inverter 25, which is inverted by the inverter 25 L
The level signal is input to the AND gates 21 and 22. Therefore, the output of the dimming pulse is stopped. Further, the output signal D ₀ of the first counter 15 which has become H level is the AND gate 2.
3, 24, whereby the output pulse of the second PWM generation circuit 18 is supplied to the AND gates 23, 24 and the OR gate 26,
Output via 27.

Here, the initial value in the same manner as also the second counter 16 first counter 15 is assumed to be FFH, the ΔT _b (ΔT _b «T _b) an amount corresponding ON period T _b for one count (01H) Shorten the second
When the count value of the counter 16 becomes 03H, when harmonic light of Figure 11 short ON period T _c as shown in (Part 1) (T _c
<T _b ) Dimming pulses X ₂ and Y ₂ can be obtained. At this time,
Even if the down signal _SD2 is input to the second counter 16, the second counter 16 stops counting down, and
Hold 03H and do not count down any further. That is, the output becomes the lowest there.

The second counter 16 and the second PWM signal generator 18
By the action, the ON period of the basic pulse T _b or Δ
By increasing the T _f time by T _b (ΔT _b ≪T _b ) as shown in (d) of FIG.
The T _D can be increased up to T _e. In this case, time T _e -T _f is set in the same manner as when the above-mentioned harmonic light (1), the value is fixed.

Further, the above-mentioned operations (1) and (2) at the time of harmonic light can be performed simultaneously. That is, a pulse of the ON period T _b as short as [Delta] T _b min, then longer [Delta] T _b amount corresponding T _f time. This operation is alternately repeated to generate the lowest output waveform. According to the results of actual experiments, T _b = 16 μsec,
T _k = 32 μsec, T _c = 3 μsec, T _D = 8.2 msec, T _e = 12.5 msec, T
_g could be 96 μsec.

The case where the output is reduced from the maximum output has been described above, but the case where the output is increased from the minimum output can be similarly performed by operating the up switch 14a in FIG. At that time, by using a plurality of PWM up / down counters and PWM signal generators, the dimming ratio can be increased, and higher harmonics can be achieved.

Next, the advantage of the above-described double PWM method will be supplementarily described. For example, if the period T _k of the square wave is 256 in a constant period T _D, dimming ratio of normal dimming from the maximum output
256/256 → 255/256 → 254/256 …… and the rate of change is 1/256
However, if the dimming is further advanced, the dimming ratio will be 3/256 → 2/256
→ 1/256, the rate of change is 1/2. That is, while the change rate near the maximum output is small, the change rate near the minimum output is large. For this reason, the brightness of the discharge lamp, which is a load, decreases rapidly due to a large change rate, and the brightness does not seem to change linearly for an observer. Especially,
There is a limit in the normal mode when a linear luminance change is obtained with a harmonic ratio and the luminance is finely controlled near the minimum output. However, in this embodiment, since the second counter 16 and the second PWM signal generator 18 are provided, the above-described problem can be solved.

When dimming the discharge lamp, the time of T _g shown in FIG. 11 is used for the rise of the discharge lamp and the inverter circuit. _If the time of T _g is further shortened, the lamp does not light or flickers. Cause. However, according to this embodiment,
Since the amount of energy alone can be reduced without changing the time of T _g , the above problem can be solved.

The present invention can be widely used not only for lighting devices for light sources such as CFL, WFL, and EL, but also for other power supply circuits.

〔The invention's effect〕

As described above, according to the present invention, since the means for matching the frequency of the oscillation signal from the outside with the resonance frequency of the output transformer is provided, there is an effect that the efficiency can be efficiently controlled and the load can be optimally controlled. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram of a driving pulse input to the output circuit of FIG. 1, FIG. 3 is a block diagram showing a second embodiment of the present invention,
FIG. 4 is an explanatory diagram showing the operation of the circuit of FIG. 3, FIG. 5 is a block diagram showing a third embodiment of the present invention, FIG. 6 is a circuit configuration diagram showing a fourth embodiment of the present invention, 7 is a signal waveform diagram of each part of FIG. 6, FIG. 8 is a circuit diagram for explaining the operation of the circuit of FIG. 6, FIG. 9 is a waveform diagram showing the operation of the circuit of FIG. FIG. 11 is a circuit diagram showing a fifth embodiment of the present invention, FIG. 11 is an output waveform diagram of each part in FIG. 10, FIG. 12 is a circuit diagram of a conventional inverter device, and FIG. FIG. 3 is a diagram of voltage waveforms applied to the. DESCRIPTION OF SYMBOLS 1 ... Load 2 ... Output circuit 3 ... CPU 4 ... VCO 5 ... Variable resistance (frequency control means) 6 ... Voltage detection circuit 9 ... DC power supply 10 ... Current detection circuit 11 ... Discharge lamp 14 ... dimming switch 15 ... first PWM up / down counter 16 ... second PWM up / down counter 17 ... first PWM signal generator 18 ... second PWM signal generator C ₁ ... capacitor L ...... coil N ...... primary winding Q _5, Q ₆ ...... FET (switching element) S ...... secondary winding T ...... output transformer

Claims (2)

(57) [Claims] An inverter device for converting a direct current input to a primary side of an output transformer into an alternating current by driving a switching element and outputting the alternating current from a secondary side of the transformer, wherein an oscillation signal for driving the switching element is provided. Frequency control means for matching the resonance frequency of the resonance circuit formed by the output transformer, the frequency control means has a switch, a counter for counting up and down, a PWM signal generator for generating a PWM signal, The counter counts up or down by the switch, and the pulse generated by the PWM signal generator is stopped or oscillated in response to the output of the counter within a certain period, and the oscillation is stopped. An inverter device characterized in that a dimming pulse is obtained by the following. 2. The frequency control means comprises a plurality of counters and a PWM signal generator, wherein each of the PWM signal generators has a different pulse on period and the predetermined period. The inverter device according to claim 1.