JP2701805B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor, and more particularly to a method for manufacturing a wiring.

[0002]

2. Description of the Related Art With the rapid development and spread of mobile communication in recent years, there has been an increasing demand for low voltage, high density and high integration of communication MMICs (monolithic microwave integrated circuits). In particular, compound semiconductors such as GaAs (gallium arsenide) are often used in MMICs because they have higher power added efficiency, better low noise characteristics and higher frequency characteristics than Si (silicon). Further, in increasing the density of GaAs MMIC, MMIC
It is essential to reduce the size of the passive element that occupies most of the area of the above, and in particular, it is important to reduce the size of the inductor formed by the spiral spiral wiring.

[0003] By miniaturizing the wiring of the inductor, downsizing of the inductor can be realized, but at this time, a large problem is caused by current loss in the wiring portion due to high-frequency current. When an electromagnetic wave propagates through a wiring, a current flows intensively on a skin portion of the wiring in contact with the electromagnetic wave, that is, a so-called skin effect occurs. As the frequency increases, the skin thickness through which the current flows decreases. On the other hand, the resistance value per unit length of the wiring is inversely proportional to the cross-sectional area of the portion of the wiring through which the current flows. Therefore, the higher the frequency, the higher the resistance value, and as a result, the larger the current loss. This current loss also occurs in a frequency band of 1 to 6 GHz used in mobile phones and the like, and is a serious problem.

In order to solve this problem, it is effective to increase the surface area of the wiring. As one method, a wiring with an increased wiring height has been proposed in the Vol. 2, No. 2 of the 19th Congress of the Institute of Electronics, Information and Communication Engineers, Volume 575. To further increase the surface area, the cross-sectional shape of the wiring was made U-shaped Such wiring (hereinafter referred to as U-shaped wiring) is 1992
IEICE Autumn Conference Papers, Vol.

A method for manufacturing a U-shaped wiring disclosed in the above-mentioned document will be described with reference to FIG. 5A and 5B are schematic cross-sectional views showing a method of manufacturing a U-shaped wiring of a conventional semiconductor device, wherein FIG. 5A shows a state where a photoresist is patterned at a predetermined position of an interlayer insulating film on a semiconductor substrate, and FIG. A state in which a metal for an electrode is formed, (c) a state in which gold plating is performed thereon,
(D) shows the state where the second photoresist is patterned, and (e) shows the state where the U-shaped wiring is completed by removing the gold plating, the electrode metal and the photoresist other than the necessary parts. In the figure, reference numeral 51 denotes a semiconductor substrate, 52 denotes an interlayer insulating film, 54 denotes a first photoresist, 55 denotes an electrode metal, 56 denotes gold plating, and 58 denotes a second photoresist.

First, a first photoresist 54 having a thickness of about 8 μm is patterned on a desired portion of an interlayer insulating film 52 formed on a semiconductor substrate 51 by using a photolithography technique (FIG. 5A).

Next, an electrode metal 55 to be a current supply layer at the time of gold plating in the next step is formed on the entire surface of the interlayer insulating film 52 and the first photoresist 54 by a sputtering method (FIG. 5B). Thereafter, gold plating with a thickness of 1 μm is performed by a plating method (FIG. 5C).

A second photoresist 58 serving as a mask material at the time of forming the wiring is patterned on the wiring forming portion (FIG. 5D). After that, the gold plating 56 and the electrode metal 55 other than the wiring portion are removed by ion milling, and the first and second photoresists are peeled off to complete the U-shaped wiring (FIG. 5E).

[0009]

In the above-described method of manufacturing a semiconductor device, the photoresist is patterned twice to form a U-shaped wiring, so that the manufacturing cost is increased and the number of days is increased. there were.

Another problem is that misalignment occurs between the first and second photoresists so that the wiring shape may not be U-shaped.

It is an object of the present invention to provide a method of manufacturing a semiconductor device at a low cost and in which a U-shaped wiring can be formed stably.

[0012]

According to a method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device having a wiring having a U-shaped cross section, comprising the steps of: forming an insulating layer formed on a semiconductor substrate on which a semiconductor element is formed; Forming a first metal film on the film, patterning a photoresist at a predetermined position on the first metal film to form a cavity having a U-shaped cross section, A step of forming a second metal film on the metal film and the photoresist, and removing the surfaces of the first metal film and the second metal film parallel to the semiconductor substrate surface by ion milling or dry etching. Forming a second metal film formed on both side surfaces of the photoresist, and forming a wiring having a U-shaped cross section with the metal film and the first metal film on the lower surface of the photoresist.

In a method of manufacturing a semiconductor device having a wiring having a U-shaped cross section, a first metal film is formed on a first insulating film formed on a semiconductor substrate on which a semiconductor element is formed. And forming a second insulating film on the first metal film, patterning a photoresist at a predetermined position on the second insulating film, and etching the second insulating film into a U-shape. A step of forming a cavity having a shape cross section, a step of forming a second metal film on the first metal film and the second insulating film, and a semiconductor of the first metal film and the second metal film A surface parallel to the substrate surface is etched back by ion milling or dry etching and removed, and second metal films formed on both side surfaces of the second insulating film and lower surfaces of the metal film and the second insulating film Forming a wiring having a U-shaped cross section with the first metal film Degree and may have.

In a single photoresist patterning step as compared with the conventional manufacturing method, a U-shaped wiring having a small current loss even at a high frequency can be formed, and the photoresist formed in a U-shaped cross-section hollow portion is formed. Alternatively, the metal film formed on the side wall of the second insulating film becomes the wiring as it is, so that the shape of the wiring is stabilized.

By using the second insulating film formed by etching as a side wall, a U-shaped wiring having a wiring height higher than that of a photoresist thick film which is technically difficult to increase the film thickness is formed. it can.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a method of manufacturing a U-shaped wiring of a semiconductor device according to a first embodiment of the present invention. FIG. 1A shows a method of forming a low-resistance metal on an interlayer insulating film on a semiconductor substrate. (B) is a state where a photoresist is patterned at a predetermined position on a low resistance metal, (c) is a state where a metal for an electrode is formed and gold plating is performed thereon, and (d) is a wiring part Low resistance metal other than
(E) shows a state in which the metal for the electrode and the gold plating have been removed, and (e) shows a state in which the photoresist has been removed to complete the U-shaped wiring. In the figure, reference numeral 11 denotes a semiconductor substrate, 12 denotes an interlayer insulating film, 13 denotes a low-resistance metal, 14 denotes a photoresist,
Denotes metal for electrodes and 16 denotes gold plating.

In the first embodiment, an interlayer insulating film 12 is formed on a semiconductor substrate 11 on which semiconductor elements are formed, and after flattening, a film of a low-resistance metal 13 is formed thereon. (FIG. 1A), a photoresist 14 is patterned at a predetermined position of the low-resistance metal 13 by using a photolithography technique (FIG. 1B). Next, an electrode metal 15 serving as a current supply layer is formed on the entire surface on the low resistance metal 13 and the photoresist 14, and gold plating 16 is performed thereon (FIG. 1c). Thereafter, the entire surface is subjected to ion milling or reactive ion etching (hereinafter abbreviated as RIE) to form a low-resistance metal 1 on the outer surface parallel to the semiconductor substrate 11 except for the wiring portion.
3. If the etch back is performed until the metal 15 for the electrode and the gold plating 16 are removed, the metal 15 for the electrode and the gold plating 16 remain on the side wall of the photoresist 14 as a sidewall (FIG. 1D). Finally, when the photoresist 14 is removed, a U-shaped wiring based on the low-resistance metal 13 is completed. Compared with the conventional method of manufacturing a U-shaped wiring, only one patterning step of the photoresist is required, and the wiring is formed as a sidewall on the side surface of the photoresist. Absent.

Next, a second embodiment of the present invention will be described with reference to the drawings. 2A and 2B are schematic cross-sectional views illustrating a method for manufacturing a U-shaped wiring of a semiconductor device according to a second embodiment of the present invention. FIG. 2A shows a method of forming a low-resistance metal on an interlayer insulating film on a semiconductor substrate. (B) is a state in which the second insulating film formed on the low resistance metal is etched into a predetermined shape by using a patterned photoresist; (c)
Shows a state in which a metal for an electrode is formed and gold-plated thereon, (d) shows a state in which a low-resistance metal other than a wiring portion, metal for an electrode and gold plating are removed, and (e) shows a state in which a second insulating film is removed. This shows a state where the U-shaped wiring is completed. In the figure, reference numeral 21 denotes a semiconductor substrate, 22 denotes an interlayer insulating film, 23 denotes a low resistance metal, 24 denotes a photoresist, 25 denotes an electrode metal, 26 denotes gold plating, and 27 denotes a second insulating film.

In the second embodiment, an interlayer insulating film 22 is formed on a semiconductor substrate 21 on which semiconductor elements are formed, and a low-resistance metal 23 is formed thereon (FIG. 2A). A second insulating film 27 is formed, a photoresist 24 is patterned at a predetermined position of the second insulating film 27 by using a photolithography technique, and the second
Is formed in a predetermined shape (FIG. 2B). Next, an electrode metal 25 serving as a current supply layer is formed on the entire surface on the low resistance metal 23 and the second insulating film 27, and gold plating 26 is performed thereon (FIG. 2c). Thereafter, the entire surface is etched back by ion milling or reactive ion etching (hereinafter abbreviated as RIE) until the low-resistance metal 23, electrode metal 25, and gold plating 26 on the outer surface other than the wiring portion are parallel to the semiconductor substrate 21. Then, the electrode metal 25 and the gold plating 26 remain as side walls on the side walls of the second insulating film 27 (FIG. 2D). Finally, when the second insulating film 27 is removed, a U-shaped wiring based on the low-resistance metal 23 having the same shape as that of the first embodiment is completed.
Compared with the conventional method of manufacturing a U-shaped wiring, only one photoresist patterning process is required, and the wiring is formed as a sidewall on the side surface of the second insulating film. Will not occur.

In the first embodiment, the wiring is formed as a sidewall on the side surface of the photoresist formed in a predetermined shape. In the second embodiment, the wiring is formed in a predetermined shape by etching using a photoresist. A sidewall was formed on the side surface of the insulating film thus formed. Since the cavity of the U-shaped wiring is formed by using an insulating film formed by etching instead of the thick film photoresist which is difficult to manufacture, the width of the cavity can be reduced and the height can be increased. It is possible to form a U-shaped wiring having a narrower wiring width and a higher wiring height and a higher aspect ratio, and it is possible to obtain a wiring having a lower resistance than in the first embodiment.

Next, an example of specific manufacturing conditions of each embodiment will be described with reference to FIGS.

In the first embodiment, first, an interlayer insulating film 12 having a thickness of 2 μm is formed on a semiconductor substrate 11 on which a semiconductor element is formed, flattened, and then made of tungsten (W). A low-resistance metal 13 having a thickness of 500 nm is formed by a sputtering method (FIG. 1A). Note that a metal other than W may be used as the low-resistance metal material.

Next, using a photolithography technique, a photoresist 14 having a thickness of 8 μm is patterned at a desired location at a width of 2 μm and an interval of 6 μm (FIG. 1B).
Here, in order to form a thick-film photoresist, a photoresist made of a high-viscosity novolak-based resin is required. The kinematic viscosity of the photoresist for thick film is 200 or more and 100
It is preferably 0 cSt or less, and the kinematic viscosity of the photoresist used this time is 460 cSt. Usually used 1
Since the kinematic viscosity of a photoresist having a thickness of μm is 10 to 50 cSt, the photoresist for a thick film used this time is about 20 μm.
The viscosity is higher about twice. In the case of 200 cSt or less, it is difficult to apply a thick film of 5 μ or more, and 1000 cSt
In the above case, there is a problem of workability that the application port is clogged at the time of application and a problem that the film thickness becomes uneven in the wafer surface. Therefore, a photoresist having a kinematic viscosity of 200 to 1000 cSt is preferable.

After the photoresist is applied, a first baking process is performed to remove the residual solvent in the photoresist film.
90 sec. After the operation, at a temperature of 110 ° C. for 90 sec. carry out. There is a problem that the remaining solvent cannot be completely removed by the baking treatment at a low temperature of 95 ° C., and when the baking treatment is performed only once at a high temperature, the photoresist surface is hardened first and the photoresist film is hardened. Has a problem of foaming. Therefore, first, 100 ° C
It is desirable to perform a high-temperature bake of 100 ° C. or more and 130 ° C. or less after the following low-temperature bake. Other than the above method,
The baking process may be performed while gradually increasing the temperature.

Exposure and development need to be performed for a longer period of time than in the case of a 1 μm-thick photoresist commonly used. In the case of a 1 μm-thick photoresist commonly used, the UV light exposure energy is 10
0 mJ / cm ² , development time of alkaline developer is 60 seconds
c. In this case, the UV light exposure energy was 400 mJ / cm ² , and the development time of the solution was 180 sec.
Performed in Finally, a second bake treatment is performed at 110 ° C., 9
0 sec. And a thick photoresist is completed.

Then, an electrode metal 15 to be a current supply layer at the time of gold plating in the next step is formed on the entire surface of the interlayer insulating film 12 and the photoresist 14 by a sputtering method. (FIG. 1c). Here, the electrode metal is preferably W or titanium (Ti) having a thickness of 50 nm.

Thereafter, the whole surface is subjected to ion milling or reactive ion etching (hereinafter abbreviated as RIE) using a mixed gas of sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ) and argon (Ar). To remove the low-resistance metal 13, the electrode metal 15, and the gold plating 16 other than the wiring portion, and leave the electrode metal 15 and the gold plating 16 on the side surfaces of the photoresist 14 as sidewalls ( FIG. 1d).

In the above-described etchback, ion milling or RIE is used, but a method of combining both is desirable. Specifically, the gold plating 16 is removed by ion milling, and the electrode metal 15 and the low-resistance metal 13 are removed. R
The method of removing by the IE has a high throughput, and can reduce the problem of metal re-attachment and dust at the time of removal. In order to etch a groove having a high aspect ratio (groove width is 4 μm and height is 8 μm), it is necessary to perform ion milling and RIE at a low pressure. This time, in ion milling, the Ar gas flow rate was 5 sccm and the pressure was 0.5 mtorr.
r, the gold plating 16 is removed under the conditions of an ion beam energy of 700 V.
Gas flow rate SF ₆ 5sccm, CF ₄ 5scc by E device
The low-resistance metal 13 was removed under the conditions of m, Ar 10 sccm, pressure 1 mtorr, and RF power 350 W.

Further, an ashing method using a gas containing oxygen (O ₂ ) or a method of irrigating with a mixed solution of dichlorobenzene phenol and alkylbenzene sulfonic acid and then irrigating with methyl ethyl ketone and alcohol sequentially is used.
The photoresist 14 is removed, and the U-shaped wiring (the lower dimension of the wiring is 4 μm, the thickness of the wiring is 1 μm, and the pitch between the wirings is 4 μm)
m, wiring height 8 μm) is formed (FIG. 1e).

This U-shaped wiring has a shape in which the upper surface has a sharp corner. This is caused by the above-mentioned ion milling or etch back by RIE, and there is no problem in mechanical strength and electrical characteristics. Does not occur.

In the first embodiment, the wiring metal is formed by depositing the metal for the electrode in advance for gold plating and then performing the gold plating to form the wiring. However, the metal for the wiring is formed only by plating or sputtering. It may be formed.

In the second embodiment, first, silicon nitride (S) is formed on a semiconductor substrate 21 on which a semiconductor element is formed.
After forming an interlayer insulating film 22 made of iN), a low-resistance metal 23 is formed by a sputtering method (FIG. 2A).

Next, after a second insulating film 27 made of silicon oxide (SiO ₂ ) is formed, the photoresist 24 is patterned by photolithography.
The second insulating film 27 is selectively etched with respect to the low-resistance metal 23 by RIE using ethane hexafluoride (C ₂ F ₆ ) (FIG. 2B). At this time, a magnetron RIE apparatus was used under the conditions of a gas flow rate of C ₂ F _{6 of} 20 sccm, CO of 20 sccm, a pressure of 15 mtorr, and an RF power of 300 W.

After removing the photoresist 24, the electrode metal 2 serving as a current supply layer at the time of gold plating in the next step.
5 is formed on the entire surface of the interlayer insulating film 22 and the second insulating film 27 by a sputtering method, and thereafter, a 1 μm-thick gold plating 26 is performed by a plating method (FIG. 2C).

Further, as in the first embodiment, the entire surface is subjected to ion milling or RIE using a mixed gas of sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ) and argon (Ar). To remove the low-resistance metal 23, the electrode metal 25 and the gold plating 26 other than the wiring portion, and to form the electrode metal 2 on the side surface of the second insulating layer 27.
5 and the gold plating 26 are left as side walls. (FIG. 2d).

Second using hydrofluoric acid or buffered hydrofluoric acid
The insulating film 27 is removed to form a U-shaped wiring (FIG. 2E).

In the above example, S is used as the interlayer insulating film.
Although iN and SiO ₂ are used as the second insulating film, any film may be used as long as the second insulating film can be selectively removed from the interlayer insulating film.

Further, in the description of the present embodiment, the description has been made of the form in which the photoresist 24 obtained by etching the second insulating film 27 is removed and then the electrode metal 25 is formed.
A desired thickness is formed by combining the second insulating film 27 and the photoresist 24 patterned thereon, and the electrode metal 25 is formed thereon without removing the photoresist 24. The same effect can be obtained even if the same is performed.

[0039]

As described above, according to the present invention, after a low resistance metal is formed on an interlayer insulating film, a pattern for forming a cavity in a cross section of a U-shaped wiring is formed by a photoresist or a second insulating film. After forming metal and gold plating on the entire surface, the outer surface parallel to the semiconductor substrate is etched back by ion milling or RIE to form metal and gold plating on the side wall of the pattern forming the cavity. As a sidewall, and U
Since it is a manufacturing method for obtaining a character-shaped wiring, there is an advantage that the U-shaped wiring can be formed with one less number of times of photoresist patterning than the conventional method, and the manufacturing cost can be reduced.

Further, since the U-shaped wiring can be formed by self-alignment, there is an advantage that the problem of misalignment is eliminated and the U-shaped wiring can be always formed stably.

Further, when the pattern for forming the cavity in the cross section of the U-shaped wiring is formed by the second insulating film,
The width of the cavity can be narrowed and the height can be increased, whereby a wiring having a narrower U-shaped wiring and a higher aspect ratio having a higher wiring height can be formed, and a wiring having a lower resistance can be obtained. There is an effect that comes out.

The spiral inductor pattern shown in FIG. 3 (wiring length 3 mm, inductor occupation area 0.022
In the U-shaped wiring (lower dimension of wiring 4 μm, wiring thickness 1 μm, pitch between wirings 4 μm, wiring height 8 μm) formed according to the present invention forming 5 mm ² ), the U-shaped wiring formed by the conventional manufacturing method is used. Inductor characteristics equivalent to those of the mold wiring can be obtained.

More specifically, S-parameter analysis was performed at a frequency of 0.5 to 10 GHz, and fitting and fitting were performed using the equivalent circuit model shown in FIG. Then the inductor is 5n
H, the resistance value was 4Q, which was the same as the conventional method.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a U-shaped wiring of a semiconductor device according to a first embodiment of the present invention. (A) shows a state in which a low-resistance metal is formed on an interlayer insulating film on a semiconductor substrate. (B) shows a state where a photoresist is patterned at a predetermined position on the low resistance metal.
(C) shows a state in which a metal for an electrode is formed and gold plating is performed thereon. (D) shows a state in which the low resistance metal, the electrode metal, and the gold plating other than the wiring portion are removed. (E) shows a state in which the U-shaped wiring is completed by removing the photoresist.

FIG. 2 is a schematic cross-sectional view illustrating a method of manufacturing a U-shaped wiring of a semiconductor device according to a second embodiment of the present invention. (A) shows a state in which a low-resistance metal is formed on an interlayer insulating film on a semiconductor substrate. (B) shows a state where the second insulating film formed on the low resistance metal is etched into a predetermined shape by using a patterned photoresist. (C) shows a state in which a metal for an electrode is formed and gold plating is performed thereon. (D) shows a state in which the low resistance metal, the electrode metal, and the gold plating other than the wiring portion are removed. (E) is the second
2 shows a state in which the insulating film is removed to complete the U-shaped wiring.

FIG. 3 is a plan view of a spiral inductor.

FIG. 4 is an equivalent circuit model diagram used for S-parameter analysis.

FIG. 5 is a schematic cross-sectional view showing a method of manufacturing a U-shaped wiring of a conventional semiconductor device. (A) shows a state where a photoresist is patterned at a predetermined position of an interlayer insulating film on a semiconductor substrate. (B) shows a state where a metal for an electrode is formed.
(C) shows a state where gold plating is performed thereon. (D)
Shows a state where the second photoresist is patterned.
(E) shows a state where the U-shaped wiring is completed by removing the gold plating, the electrode metal and the photoresist other than the necessary portions.

[Explanation of symbols]

 11, 21, 51 Semiconductor substrate 12, 22, 52 Interlayer insulating film 13, 23 Low resistance metal 14, 24 Photoresist 15, 25, 55 Metal for electrode 16, 26, 56 Gold plating 27 Second insulating film 31 U-shaped Wiring 32 Through hole 33 Electrode 54 First photoresist 58 Second photoresist

Claims (2)

(57) [Claims] 1. A method for manufacturing a semiconductor device having a wiring having a U-shaped cross section, comprising: forming a first metal film on an insulating film formed on a semiconductor substrate on which a semiconductor element is formed; Patterning a photoresist for forming the cavity having the U-shaped cross section at a predetermined position on the first metal film; and forming a second photoresist on the first metal film and the photoresist. A step of forming a metal film; removing the surfaces of the first metal film and the second metal film parallel to the semiconductor substrate surface by etching back by ion milling or dry etching; The second metal film formed on the surface and the metal film and the first metal film on the lower surface of the photoresist form a U
Forming a wiring having a V-shaped cross section. 2. A method of manufacturing a semiconductor device having a wiring having a U-shaped cross section, wherein a first metal film is formed on a first insulating film formed on a semiconductor substrate on which a semiconductor element is formed. Forming a second insulating film on the first metal film; patterning a photoresist at a predetermined position on the second insulating film; and etching the second insulating film by etching. Forming a second metal film on the first metal film and the second insulating film; forming the second metal film on the first metal film and the second insulating film; A surface parallel to the semiconductor substrate surface of the second metal film is removed by etching back by ion milling or dry etching, and the second metal film formed on both side surfaces of the second insulating film and The lower surface of the metal film and the lower surface of the second insulating film Serial manufacturing method of a semiconductor device and having a first metal film and the step of forming a wiring of U-shaped cross-section.