JP2699859B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a read only memory (ROM). [0002] The present invention relates to a read only memory (ROM).
Switching and changing of the external input terminal, external output terminal and external control terminal of the integrated circuit are provided in advance in a circuit whose function can be changed, and in the same manufacturing process as the method of writing data in the memory cell of the integrated circuit. This is done efficiently. The representative of the read-only memory (hereinafter referred to as ROM), there is a mask programmable ROM (hereinafter referred to as mask ROM). The mask ROM uses a method in which the contents of the ROM are written by changing a part of a mask pattern used for manufacturing an LSI.
FIG. 1 shows a layout of a memory cell written by this method. The word lines and data lines in FIG. 1 are made of polysilicon and metal, respectively. Although a method of writing data into the memory cell are several, ROM bit pattern of FIG. 1A, the mask of the channel dough flops layer is immobilized (memory) the presence or absence of the channel dough up to the diffusion layer. The ROM bit pattern in FIG. 1B is fixed (memory) by the presence or absence of a contact hole using a mask of a contact layer. In this manner the mask ROM, the data to be memory, converts ROM manufacturer is the mask pattern, a method of writing to a memory cell has been taken. The mask required for manufacturing a mask ROM manufactured by the lithographic method is ROM
In addition to the mask for the bit pattern, more than ten masks used in another process are required, and the mask ROM is manufactured by using these in order. Therefore, when manufacturing mask ROMs having different data contents to be written into memory cells, the mask ROM manufacturer receives data from a user of the mask ROM, converts the data into a mask pattern, and writes the data. Only change the mask of the layer,
Other processes use the same mask as other mask ROMs,
A mask ROM is manufactured. FIG. 2 shows a block diagram of a typical mask ROM. Figure 2A is an address designation signal A _O to A ₁₁ of 15 and 16 as input signals, 17 of the chip select signal CS
And 43 output signals O _{1 to} O ₈ . FIG. 2B shows an input signal having 15, 16 addressing signals A _{O to} A ₁₁ , 18, ₁₉ , 21 chip select signals CS1, CS2, / CE (/ indicates an inverted signal), and 20 OE and 43 output signals O _{1 to} O ₈ . 2B has two chip select signals and one output control signal, and the functions are increased compared to FIG. 2A. FIG. 3 shows a part of a pin arrangement of the integrated circuit in a state where FIGS. 2A and 2B are packaged.
3A, A8 of 24, A9 of 25, C of 26
At the same pin in FIG. 3B, A11 of S and 27 is changed to a signal terminal of the / OE function of A9 and 31 of CS2 and CS23 of CS23 and CS30 of CS23. [0005] The function and arrangement of the terminals of such signal lines differ depending on the mask ROM user.
Conventionally, two types of functions A and B in FIG.
There are two types of pin arrangements, A and B in FIG. 3. Every time the pin function or pin arrangement is changed, it is necessary to change the entire process mask or at least the metal mask. There is a drawback that the number of masks is large, and the time and cost for preparing the mask are high. According to the present invention, in order to eliminate such a drawback, a circuit having another function or a circuit which can be shared with another function is provided in advance, and this circuit is provided with a mask 1 having the same layer as the ROM bit pattern for writing the memory. The circuit is intermittently interposed between sheets, and the pin functions and the arrangement of signal terminals are changed. [0007] That is, the present invention provides a mass spectrometer.
Memory cells to which data is written using
An external terminal to which one of the functions is set
In a method of manufacturing a semiconductor device having a plurality of logic circuits,
A first step of manufacturing a transistor group that can be configured as:
Writing data to the memory cells using the mask
And selective connection wiring within the transistor group
Signal according to the function set to the external terminal.
A logic circuit for performing signal processing selectively, and the external terminal
A first function set to one of the plurality of functions.
It has two steps . FIG. 4 shows an embodiment of the present invention. FIG.
Represents a circuit that can be commonly used by sharing the block diagrams of A and B in FIG. The connection by the solid line in FIG. 4 corresponds to the function of A in FIG. When a portion indicated by a broken line is connected to a solid line in FIG. 4, a circuit having the function of B in FIG. 2 is obtained.
Parts a and b in FIG. 4 correspond to the chip selection signal circuits 18 and 19 in FIG. 2B, and are circuits that wait for another function in advance. C portion of FIG. 4, in the case if the Figure 2A, becomes Ji <br/> class tap select signal CS circuit 17, in the case of FIG. 2B, 2
It becomes an output control signal / OE circuit of 0, and has a group of transistors that can be used in common to have another function. That is, in FIG. 4C, a transistor group connected by a solid line is used in common for the two functions of CS and / OE, and a transistor group connected by a broken line is used for the function of / OE. The part e of FIG. 4 is the case of FIG.
It becomes 21 of the address signal A ₁₁ circuit, in the case of Figure 2B, as the input control signal / CE circuit, has a circuit with a common transistor group. FIG. 5 shows an example in which such switching of the pin function and change of the pin arrangement are performed by using the same layer mask as the ROM bit pattern to be written into the memory.
In FIG. 5, the switching and connection of the circuit is based on the same contact layer as the writing to the memory cell shown in FIG. 1B. Reference numerals 33, 34, and 35 in FIG. 5 denote polysilicon forming transistors. 36 and 42 in FIG.
It is a metal wiring part. Reference numeral 37 in FIG. 5 denotes a diffusion layer. Reference numerals 33, 39, 40, and 41 in FIG. 5 represent contact layers. When 38 contact layers are formed, 33
And the metal of 36 are conducted to connect the wiring. Further, when the contact layers of 39 and 40 enter,
The diffusion of 37 and the metal of 36 are conducted and the wiring is connected to form a circuit. Conversely, if the contact layer 41 is not metal port Rishirikon and 42 of 34 and 35 becomes non-conductive, interconnection is cut. Intermittent of such wiring is not only a contact layer, <br/> channel dough flop 5 of Figure 1A are possible. As described above, according to the present invention, the switching of the wiring is performed using the same mask as that for writing to the memory .
In comparison with conventional switching and changing of wiring such as metal mask
In all, reducing the time and cost of creating masks
it can. [0011] Such a method is not limited to a mask ROM, but may be an integrated circuit having a built-in ROM function or a PLA.
It is also applied to circuits.

[Brief description of the drawings] FIG. 1A shows a method for writing data using a diffusion layer.
Of Mori CellLesIout diagram. (B) Memo when writing data by contact layer
Of re cellLesIout diagram. FIG. 2A is an external control signal chip.StepSelect signal
Typical mask ROM block with one CS
FIG. (B) Chip select signals CS1, which are external control signals
CS2, / CE 3 and output control 1 signal / OE 1
The block diagram of the typical mask ROM in the case. FIG. 3A shows a packaged package having the function of FIG. 2A.
FIG. 3 is a partial view of a pin arrangement of the integrated circuit. (B) Package having the function of FIG. 2BSaIntegrated circuit
FIG. FIG. 4 is a SEP select circuit diagram. FIG. 5 shows polysilicon and metal by contact layer,
Connection diagram of diffused layer and metal. [Explanation of symbols]In FIG. 1 ‥‥‥ polysilicon word line 2 metal data lines 3) Contact part 4 ‥‥‥ Diffusion unit 5 ‥‥‥ channel dopeIn FIG. 5 ‥‥‥ Memory Matrix 6 ‥‥‥ Y selector 7 @ X decoder 8 @ Y decoder 9 ‥‥‥ A₀~ A₇Address input buffer 10 ‥‥‥ A₈~ A₁₂Address input buffer 11 output buffer 12 ‥‥‥ chip select input buffer 13 ‥‥‥ chip enable input buffer 14 ‥‥‥ outStepReset enable input buffer 15 ‥‥‥ A₀~ A₇JJ with address 16 ‥‥‥ A₈~ A₁₂Address input 17 ‥‥‥ CS chip select input 18 ‥‥‥ CS1 chip select input 19 ‥‥‥ CS2 chip select input 20 ‥‥‥ OE output circuit control input 21 @ CE address buffer circuit control input 22 ‥‥‥ A₁₁Address input 43 ‥‥‥ O₀~ O₇Data outputIn FIG. 23 ‥‥‥ plus power supply V_DD 24 ‥‥‥ A₈Address input 25 ‥‥‥ A₉Address input 26 ‥‥‥ CS chip select input 27 ‥‥‥ A₁₁Address input 28 @ CS1 chip select input 29 ‥‥‥ CS2 chip select input 30 ‥‥‥ A₉Address input 31 ‥‥‥ / OE output circuit control input 32 $ / CE address buffer circuit control input In FIG. a @ CS1 chip select input circuit b @ CS2 chip select input circuit C @ CS and / OE common circuit d ‥‥‥ Common circuit of CS and / CE e @ A₁₁Common circuit for address input and / CEIn FIG. 33, 34, 35, polysilicon 36,42 ‥‥‥ metal 37 ‥‥‥ diffusion layer 38, 39, 40, 41 contact layer

Claims (1)

(57) [Claims] Memory cells to which data is written using a mask
And one of a plurality of functions is set.
In a method of manufacturing a semiconductor device having external terminals, a transistor group capable of forming a plurality of logic circuits is manufactured.
A first step, and writing data to the memory cells using the mask
And selective connection wiring within the transistor group
Signal according to the function set to the external terminal.
A logic circuit for performing signal processing selectively, and the external terminal
A first function set to one of the plurality of functions.
A method for manufacturing a semiconductor device, comprising: 2. 2. The method according to claim 1 , wherein the mask is a mask for forming a contact layer. 3. 2. The method according to claim 1 , wherein the mask is a mask for channel doping.