JPH07211805A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To cut a circuit with a mask of the same layer as the ROM bit pattern of writing on a storage device, and change pin function and the arrangement of signal terminals, by forming a selective connection wiring, selectively forming logic circuits for signal processing in response to the functions, on external terminals, and setting a function on the external terminals. CONSTITUTION:In the case that pin function and pin arrangement are changed with a mask of the same layer as the ROM bit pattern of writing on a storage device, when a contact layer 38 is formed, metal 36 is electrically connected and a wiring is electrically connected. Further when contact layers 39, 40 are formed, diffusion 37 and the metal 36 are electrically connected, the wiring is connected, and a circuit is constituted. On the contrary, when a contact layer 41 is not present, polysilicon 34, 35 and metal 42 become electrically discontinuous, and the wiring is cut. Hence the switching and the change of signal lines are made possible with a mask which is the same mask as the mask for writing on a storage device, and efficiency and convenience are increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a read only memory (ROM).

[0002]

2. Description of the Related Art The present invention is a read only memory (ROM).
Within the same manufacturing process as the method for writing data in the memory cells of the integrated circuit by previously providing a circuit whose function can be switched and changed for the external input terminal, external output terminal and external control terminal of the integrated circuit. It is an efficient way to do it. A typical example of the read-only memory (hereinafter referred to as ROM) is a maskable programmable ROM (hereinafter referred to as mask ROM). The mask ROM uses a method of writing the contents of the ROM by changing a part of the mask pattern used in LSI manufacturing.
The layout of the memory cell written by this method is shown in FIG. The word lines and data lines in FIG. 1 are composed of polysilicon and metal, respectively. Although there are several methods of writing data to the memory cell, the ROM bit pattern of FIG. 1A is fixed (memory) by the mask of the channel dove layer and the presence or absence of the channel dove in the diffusion layer. The ROM bit pattern of FIG. 1B is fixed (memory) by the presence or absence of a contact hole by the mask of the contact layer. As described above, in the mask ROM, the method of converting the data to be stored into the memory into the mask pattern by the manufacturer of the ROM and writing it into the memory cell is adopted. A mask required for manufacturing a mask ROM manufactured by the lithographic method is a ROM
In addition to the bit pattern mask, ten or more masks used in another process are required, and the mask ROM is manufactured by using them in order. Therefore, the mask ROM manufacturer receives data from the user of the mask ROM, converts it into a mask pattern, and writes the data when manufacturing several kinds of mask ROMs having different data contents to be written in the memory cell. Replace only the layer mask,
Other processes use the same mask as other mask ROM,
A mask ROM is manufactured.

FIG. 2 shows a block diagram of a typical mask ROM. FIG. 2A shows 15 and 16 addressing signals A _{O to} A ₁₁ as input signals and 17 chip select signals CS.
And have 43 output signals O ₁ -O ₈ .

[0004] Figure 2B, the address designation signal A _O to A ₁₁ of 15 and 16 as the input signal has a chip select signal CS1 of 18,19,21, CS2, / CE (/ indicates an inverted signal), 20 Output control signal OE and output signals O _{1 to} O ₈ of 43. 2B has two chip select signals and one output control signal, and has more functions than A of FIG. FIG. 3 represents a portion of the pinout of the integrated circuit of FIGS. 2A and B as packaged.
3A signal terminal, 24 A8, 25 A9, 26 C
In the same pin of FIG. 3B, A11 of S and 27 is changed to a signal terminal of the function of / OE of A9 and 31 of CS2 and CS2 of 30 and CS2 of 30.

[0005]

The function and arrangement of the terminals of such signal lines differ depending on the mask ROM user.
Conventionally, it has two kinds of functions of A and B of FIG.
There are two types of pin arrangements, A and B in Fig. 3, and it is necessary to change the mask of the whole process or the metal mask at least at every change of the pin function or the pin arrangement. However, there is a drawback that it takes a lot of time and cost to make a mask.

According to the present invention, in order to eliminate such a drawback, a circuit having another function or a circuit which can be shared with another function is provided in advance, and this is provided in the mask 1 in the same layer as the ROM bit pattern for memory writing. The circuit is interrupted by a single sheet, and the pin function and the arrangement of signal terminals are changed.

[0007]

That is, according to the present invention, a memory cell in which data is written using a mask at the time of manufacturing, an external terminal whose function can be selectively set from a plurality of functions, and an external terminal A group of transistors used in a logic circuit configured to perform signal processing according to a set function, the transistor group performing signal processing according to a first function of the plurality of functions. A first transistor group used when configuring one logic circuit, and a second transistor group that performs signal processing according to the second function of the plurality of functions when configuring the first logic circuit. A second transistor group commonly used when forming a logic circuit, and forming a selective connection wiring in the transistor group by using the mask for writing data to the memory cell. Wherein selectively the logic circuit for signal processing in accordance with the function of setting the external terminal, characterized by comprising setting the one function of the plurality of functions to the external terminal Ri. Particularly in the manufacture of a mask ROM, since the data to be written in the memory is received from the user and converted into a mask pattern, if the function and arrangement of the pins are switched or changed with the mask of the same layer as this,
With one mask, the writing of the memory contents and the use required by the user are satisfied, and the efficiency is good.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 4 shows one embodiment of the present invention. Figure 4
Shows a circuit that can be commonly used by sharing the block diagrams of A and B in FIG. The connection by the solid line in FIG. 4 corresponds to the function of A in FIG. When the broken line portion is connected to the solid line in FIG. 4, a circuit having the function of B in FIG. 2 is obtained.
Parts a and b in FIG. 4 correspond to the chip selection signal circuits 18 and 19 in FIG. 2B and are circuits that wait for another function in advance. The portion C in FIG. 4 is the chip select signal CS circuit 17 in the case of FIG. 2A, and is 2 in the case of FIG. 2B.
It becomes an output control signal / OE circuit of 0, and has a transistor group that can be commonly used to have another function. That is, the transistor group tangent to the solid line in FIG. 4C is commonly used for the two functions CS and / OE, and the transistor group connected to the broken line is used for the / OE function. In the case of A of FIG. 2, the part e of FIG.
21 address signal A ₁₁ circuit, and in the case of FIG. 2B,
It is an input control signal / CE circuit, and has a common transistor group.

FIG. 5 shows an example of the case where the switching of the pin functions and the change of the pin arrangement are performed by using the mask on the same layer as the ROM bit pattern to be written in the memory.
FIG. 5 shows that switching and connection of the circuit are performed by the contact layer which is the same layer as the writing to the memory cell shown in FIG. 1B. Reference numerals 33, 34 and 35 in FIG. 5 are polysilicon forming a transistor. 36 and 42 in FIG.
This is a metal wiring part. Reference numeral 37 in FIG. 5 is a diffusion layer. Reference numerals 33, 39, 40 and 41 in FIG. 5 denote contact layers. When the contact layer of 38 is formed, 33
And the metal of 36 is electrically connected to connect the wiring. Furthermore, when 39 and 40 contact layers are included,
A circuit is formed by connecting the diffusion of 37 and the metal of 36 to connect the wiring. On the contrary, when the contact layer of 41 is not provided, the polysilicon of 34 and 35 and the metal of 42 are non-conductive, and the wiring is disconnected. Such disconnection of the wiring is possible not only in the contact layer but also in the channel dove of FIG. 1A.

[0010]

As described above, according to the present invention, the wiring can be switched with the same mask as that for writing in the memory,
Compared to the conventional switching and changing of wiring such as metal masks, data writing and switching and changing of signal lines can be done efficiently with one mask.

Note that such a method is not limited to the mask ROM, but is applicable to an integrated circuit having a ROM function or a PLA.
It is also applied to circuits.

[Brief description of drawings]

FIG. 1A is a layout diagram of a memory cell when data is written by a diffusion layer. (B) Layout diagram of the memory cell when data is written by the contact layer.

FIG. 2A is a block diagram of a typical mask ROM when there is one chip select signal CS which is an external control signal. (B) Chip select signal CS1, which is an external control signal
FIG. 3 is a block diagram of a typical mask ROM when there are three CS2, / CE and one output control 1 signal / OE.

FIG. 3A is a partial view of the pinout of a packaged integrated circuit having the functionality of FIG. 2A. (B) A partial view of the pin arrangement of a packaged integrated circuit having the function of FIG. 2B.

FIG. 4 is a sep select circuit diagram.

FIG. 5 is a connection diagram of polysilicon and metal by a contact layer and a diffusion layer and a metal.

[Explanation of symbols]

1 ··· Polysilicon word line 2 ·· Metal data line 3 ··· Contact part 4 ··· Diffusion part 5 ··· Channeled -Pop section 5 ... Memory matrix 6 ... Y selector 7 ... X decoder 8 ... Y decoder 9 ... A _O to A ₇ address input Baffua 10 ...... A ₈ to A ₁₂ an address input buffer 11 ...... output buffer 12 ...... chip select input Baffua 13 ...... chips Enable input buffer 14 ... Outbut enable input buffer 15 ... A _{O to} A ₇ address input JJ 16 ... A _{8 to} A ₁₂ address input 17 ...・ CS chip select input 18 ・ ・ ・ ・ ・ CS1 chip select Input 19 ... CS2 chip select input 20 ... OE output circuit control input 21 ... CE address buffer circuit control input 22 ... A ₁₁ address input 43 ...... _O O ~ O ₇ data output 23 ...... positive supply V _DD 24 ...... A ₈ address inputs 25 ...... A ₉ address input 26 ... ··· CS chip select input 27 ······ A ₁₁ address input 28 ······ CS1 chip select input 29 ······ CS2 chip select input 30 ······ A ₉ address Input 31 ... // OE output circuit control input 32 ../ CE address buffer circuit control input a ... CS1 chip select input circuit b ... CS2 chip Select input circuit C Common circuit e · · · · · · A ₁₁ address input and / CE of the common circuitry 33, 34 and 35 of the common circuit d · · · · · · CS and / CE CS and / OE, · · · · · · Polysilicon 36, 42 ... Metal 37 ... Diffusion layer 38, 39, 40, 41 ... Contact layer

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[Procedure amendment]

[Submission date] April 21, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art The present invention is a read only memory (ROM).
Within the same manufacturing process as the method for writing data in the memory cells of the integrated circuit by previously providing a circuit whose function can be switched and changed for the external input terminal, external output terminal and external control terminal of the integrated circuit. It is an efficient way to do it. The representative of the read-only memory (hereinafter referred to as ROM), there is a mask programmable ROM (hereinafter referred to as mask ROM). The mask ROM uses a method in which the contents of the ROM are written by changing a part of a mask pattern used in LSI manufacturing.
The layout of the memory cell written by this method is shown in FIG. The word lines and data lines in FIG. 1 are composed of polysilicon and metal, respectively. Although a method of writing data into the memory cell are several, ROM bit pattern of FIG. 1A, the mask of the channel dough flops layer is immobilized (memory) the presence or absence of the channel dough up to the diffusion layer. The ROM bit pattern of FIG. 1B is fixed (memory) by the presence or absence of a contact hole by the mask of the contact layer. In this manner the mask ROM, the data to be memory, converts ROM manufacturer is the mask pattern, a method of writing to a memory cell has been taken. A mask required for manufacturing a mask ROM manufactured by the lithographic method is a ROM
In addition to the bit pattern mask, ten or more masks used in another process are required, and the mask ROM is manufactured by using them in order. Therefore, the mask ROM manufacturer receives data from the user of the mask ROM, converts it into a mask pattern, and writes the data when manufacturing several kinds of mask ROMs having different data contents to be written in the memory cell. Replace only the layer mask,
Other processes use the same mask as other mask ROM,
A mask ROM is manufactured.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

[0005]

The function and arrangement of the terminals of such signal lines differ depending on the mask ROM user.
Conventionally, it has two kinds of functions of A and B of FIG.
There are two types of pin arrangements, A and B in FIG. 3, and it is necessary to change the mask of the entire process or at least to correct the metal mask every time the pin function or the pin arrangement is changed. There are many disadvantages that it takes time and costs to make masks.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007]

That is, according to the present invention, a memory cell in which data is written using a mask at the time of manufacturing, an external terminal whose function can be selectively set from a plurality of functions, and an external terminal A group of transistors used in a logic circuit configured to perform signal processing according to a set function, the transistor group performing signal processing according to a first function of the plurality of functions. A first transistor group used when configuring one logic circuit, and a second transistor group that performs signal processing according to the second function of the plurality of functions when configuring the first logic circuit. A second transistor group commonly used when forming a logic circuit, and forming a selective connection wiring in the transistor group by using the mask for writing data to the memory cell. Wherein selectively the logic circuit for signal processing in accordance with the function of setting the external terminal, characterized by comprising setting the one function of the plurality of functions to the external terminal Ri. Particularly in the manufacture of a mask ROM, since the data to be written in the memory is received from the user and converted into a mask pattern, if the function and arrangement of the pins are switched or changed with the mask of the same layer as this,
With one mask, writing of the memory contents and the specifications required by the user are satisfied, which is efficient.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 4 shows one embodiment of the present invention. Figure 4
Shows a circuit that can be commonly used by sharing the block diagrams of A and B in FIG. The connection by the solid line in FIG. 4 corresponds to the function of A in FIG. When the broken line portion is connected to the solid line in FIG. 4, a circuit having the function of B in FIG. 2 is obtained.
Parts a and b in FIG. 4 correspond to the chip selection signal circuits 18 and 19 in FIG. 2B and are circuits that wait for another function in advance. C portion of FIG. 4, in the case if the Figure 2A, becomes Ji <br/> class tap select signal CS circuit 17, in the case of FIG. 2B, 2
It becomes an output control signal / OE circuit of 0, and has a transistor group that can be commonly used to have another function. That is, the transistor group tangent to the solid line in FIG. 4C is commonly used for the two functions CS and / OE, and the transistor group connected to the broken line is used for the / OE function. In the case of A of FIG. 2, the part e of FIG.
21 is the address signal A ₁₁ circuit, and in the case of FIG. 2B, it is the input control signal / CE circuit, which is a circuit having a common transistor group.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

FIG. 5 shows an example of the case where the switching of the pin functions and the change of the pin arrangement are performed by using the mask on the same layer as the ROM bit pattern to be written in the memory.
FIG. 5 shows that switching and connection of the circuit are performed by the contact layer which is the same layer as the writing to the memory cell shown in FIG. 1B. Reference numerals 33, 34 and 35 in FIG. 5 are polysilicon forming a transistor. 36 and 42 in FIG.
This is a metal wiring part. Reference numeral 37 in FIG. 5 is a diffusion layer. Reference numerals 33, 39, 40 and 41 in FIG. 5 denote contact layers. When the contact layer of 38 is formed, 33
And the metal of 36 is electrically connected to connect the wiring. Furthermore, when 39 and 40 contact layers are included,
A circuit is formed by connecting the diffusion of 37 and the metal of 36 to connect the wiring. Conversely, if the contact layer 41 is not metal port Rishirikon and 42 of 34 and 35 becomes non-conductive, interconnection is cut. Intermittent of such wiring is not only a contact layer, <br/> channel dough flop 5 of Figure 1A are possible.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Note that such a method is not limited to the mask ROM, but is applicable to an integrated circuit having a ROM function or a PLA.
It is also applied to circuits.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

1 (A) layout view of a memory cell when writing data by the diffusion layer. (B) layout view of a memory cell when writing data by the contact layer.

[2] (A) a block diagram of a typical mask ROM when multichip select signal CS is one which is an external control signal. (B) Chip select signal CS1, which is an external control signal
FIG. 3 is a block diagram of a typical mask ROM when there are three CS2, / CE and one output control 1 signal / OE.

FIG. 3A is a partial view of the pinout of a packaged integrated circuit having the functionality of FIG. 2A. (B) partial view of a pin arrangement of the packaged integrated circuit having a function of Figure 2B.

FIG. 4 is a sep select circuit diagram.

FIG. 5 is a connection diagram of polysilicon and metal by a contact layer and a diffusion layer and a metal.

[Explanation of Codes] In FIG. 1, 1 ... Polysilicon word line 2 ... Metal data line 3 ... Contact part 4 ... Diffusion part 5 ... Channel dope part 5 in FIG. Memory matrix 6 ... Y selector 7 ... X decoder 8 ... Y decoder 9 ... A _{0 to} A ₇ address input buffer 10 ... A _{8 to} A ₁₂ address input buffer 11 ... output buffer 12 ‥‥‥ chip select input Baffua 13 ‥‥‥ chip enable input Baffua 14 ‥‥‥ out flop Tsu preparative enable input Baffua 15 ‥‥‥ _A 0 ~A ₇ address input JJ 16 ‥‥‥ _A 8 _{~A 12} address input 17 ... CS chip select input 18 ... CS1 chip select input 19 ... CS2 chip select input 20 ... OE output circuit system Input 21 ... CE address buffer circuit control input 22 ... A ₁₁ address input 43 ... O _{0 to} O ₇ data output 23 in Fig. 3 Positive power supply V _DD 24 ... A ₈ address Input 25 ... A ₉ address input 26 ... CS chip select input 27 ... A ₁₁ address input 28 ... CS1 chip select input 29 ... CS2 chip select input 30 ... A ₉ address input 31 ... / OE output circuit control input 32 ... / CE address buffer circuit control input In Fig. 4, a ... CS1 chip select input circuit b ... CS2 chip select input circuit C ... CS and / OE Common circuit d ... CS and / CE common circuit e ... A ₁₁ common circuit for address input and / CE 33, 34, 35, ... in FIG.・ ・ ・ Polysilicon 36, 42 ・ ・ ・ Metal 37 ・ ・ ・ Diffusion layer 38, 39, 40, 41 ・ ・ ・ Contact layer

Claims (3)

[Claims] 1. A memory cell in which data is written by using a mask, an external Satoshi whose function can be selectively set from a plurality of sockets, and a signal processing corresponding to the socket set to the external terminal. And a transistor group used in a logic circuit configured to perform the above-mentioned transistor group, the transistor group including a transistor group for performing signal processing in accordance with a first function of the plurality of functions. A first transistor group used for
The second commonly used in the case of constructing the false mitigation of the first or in the case of constructing the second logic circuit for performing the signal processing according to the second function of the plurality of functions. Signal processing according to a function set in the external terminal by forming a selective connection bus bar in the transistor group using the mask for writing data to the memory cell, including a transistor group. A method of manufacturing a semiconductor device, wherein a logic circuit is selectively configured and one of the functions of the compound is set to the external terminal. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the mask is a mask for forming a contact layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the mask is a mask for a channel dove.