JPH0320903B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to read only memory (ROM) integrated circuits. The present invention enables switching and changing of external input terminals, external output terminals, and external control terminals of a read-only memory (ROM) integrated circuit by providing a circuit that can change functions in advance and storing data in memory cells of the integrated circuit. This method can be efficiently performed within the same manufacturing process as the writing method. Read-only memory (hereinafter referred to as ROM)
A typical example is mask programmable ROM.
(hereinafter referred to as mask ROM). mask rom
This method uses a method in which the contents of the ROM are written by changing some of the mask patterns used in LSI manufacturing. The layout of a memory cell written by this method is shown in FIG. The word line and data line in FIG. 1 are made of polysilicon and metal, respectively. There are several ways to write data to memory cells.
The ROM bit pattern in FIG. 1A is fixed (memory) by the mask of the channel dope layer depending on whether or not the diffusion layer is channel doped. The ROM bit pattern in FIG. 1B is fixed (memory) by the presence or absence of contact holes using a mask in the contact layer. In this way, in mask ROM, the data to be memorized is
A method is used in which the ROM manufacturer converts the mask pattern into a mask pattern and writes it into the memory cell. In addition to the ROM bit pattern mask, there are about 11 to 15 masks required for manufacturing mask ROM produced by the lithography method, which are used in other processes. A mask ROM is manufactured using sequentially. Therefore, when a mask ROM manufacturer manufactures several types of mask ROMs with different data contents to be written to memory cells, it is necessary to receive data from the mask ROM user, convert it into a mask pattern, and then write that data. A mask ROM is manufactured by exchanging only the layer mask and using the same mask as the previous step for other steps.

FIG. 2 shows a block diagram of a typical mask ROM. Figure 2 A shows 15, 16 as input signals.
It has addressing signals A ₀ -A ₁₁ , 17 chip selection signals CS, and 43 output signals O ₁ -O ₈ .

FIG. 2B has as input signals 15, 16 addressing signals A ₀ -A ₁₁ and 18, 19, 21 chip selection signals CS1, CS2, 20 output control signals, 43 output signals O ₁ to have ₈ . B in Fig. 2 has two chip selection signals,
The function is increased by one output control signal compared to A in FIG. FIG. 3 depicts a portion of the pinout of the packaged integrated circuit of FIGS. 2A and 2B. Signal terminal of Fig. 3A, 24
A ₈ , A ₉ of 25, CS of 26, A ₁₁ of 27 are the third
For the same pin in Figure B, 28 CS1, 29 CS1
CS2, 30 A ₉ and 31 have been changed to function signal terminals.

The function and arrangement of such signal line terminals are masked.
It varies depending on the ROM user, but conventionally, A in Figure 2
A in Figure 3 has two types of functions: and B.
There are two types of pin layouts: and The drawback was that it was time consuming and expensive to create.

In order to eliminate such drawbacks, the present invention provides a circuit that has a different function or a circuit that can be shared with another function, and uses this circuit for memory writing.
Using a single mask on the same layer as the ROM bit pattern, circuits can be interrupted to change functions and signal terminal locations. In other words, the integrated circuit of the present invention includes a memory cell into which data is written using a mask during manufacturing, an external terminal whose function can be set selectively from a plurality of functions, and a memory cell into which data is written using a mask during manufacturing. a group of transistors used in a logic circuit configured to perform signal processing according to a first function of the plurality of functions; A first transistor group used when configuring the first logic circuit, or a second logic circuit that performs signal processing according to a second function of the plurality of functions. and a second group of transistors that are commonly used in the case, and are set to the external terminals by forming selective connection wiring within the transistor group using the mask for writing data to the memory cell. The device is characterized in that a logic circuit that performs signal processing according to the function to be used is selectively configured, and one of the plurality of functions is set to the external terminal. especially the mask
When manufacturing ROM, the data to be written into the memory is received from the user and converted into a mask pattern, so if you switch or change the signal function or arrangement using a mask on the same layer as this, you can use one mask. , it is efficient to write memory contents and provide the functions requested by the user.

FIG. 4 is an example of the use of the present invention. Fourth
The figure shares the block diagrams of A and B in Figure 2,
It represents a circuit that can be used in common. The connection indicated by the solid line in FIG. 4 corresponds to the function of A in FIG. If we connect the broken line to the solid line in Figure 4, we get
The circuit has the function B in FIG. 2. Portions a and b in FIG. 4 correspond to the chip selection signal circuits 18 and 19 in FIG. 2B, and are circuits that have different functions in advance. In the case of Fig. 2A, the part C in Fig. 4 becomes 17 chip select signal CS circuits, and in the case of Fig. 2B, it becomes 20 output control signal circuits. , the circuit has a group of transistors that can be used in common.
That is, in FIG. 4C, the transistor groups connected by solid lines are commonly used for the two functions of CS, and the transistor groups connected by broken lines are used for the functions of CS. In the case of A in Fig. 2, the part e in Fig. 4 becomes the 21 address signal A ₁₁ circuits, and in the case of Fig. 2 B, it becomes the input control signal circuit, which is a circuit with a common transistor group. There is.

FIG. 5 shows an example of switching and changing such functions using a mask in the same layer as the ROM bit pattern written into the memory.

In FIG. 5, the circuit switching and connections are by means of a contact layer in the same layer as the writing to the memory cell indicated by B in FIG. Figure 5, 3
3, 34, and 35 are polysilicon layers forming transistors. Reference numerals 36 and 42 in FIG. 5 are metal wiring portions. 37 in FIG. 5 is a diffusion layer. 38, 39, 40, and 41 in FIG. 5 represent contact layers. When the contact layer 38 is formed, the polysilicon layer 33 and the metal layer 36 are electrically connected, and the wiring is connected. Furthermore, 39,
With 40 contact layers, 37 diffusions and 3
The metal 6 becomes conductive and the wiring becomes connected, forming a circuit. Conversely, if there is no contact layer 41, the polysilicon 34 and 35 and the metal 42 are non-conductive and the wiring is cut. This kind of wiring discontinuity occurs not only in the contact layer but also in the
5 channel doping is also possible.

As described above, according to the present invention, wiring can be switched using the same mask as for memory writing.
Compared to switching and changing wiring using conventional metal masks, writing data and switching and changing signal lines can be done with just one mask, making it more efficient and convenient.

Note that this method is applicable not only to mask ROM but also to integrated circuits with built-in ROM functions and PLA.
It also applies to circuits.

[Brief explanation of the drawing]

FIG. 1A is a layout diagram of a memory cell when data is written using a diffusion layer. Figure 1B shows the memory structure when writing data using the contact layer.
Cell layout diagram. In FIGS. 1A and 1B, 1...polysilicon word line, 2...metal data line, 3...contact part, 4...diffusion part, 5...channel doped part. Figure 2 A is the chip select signal of the external control signal.
Block diagram of a typical mask ROM with one CS. FIG. 2B is a block diagram of a typical mask ROM when external control signals include three chip select signals CS1 and CS2 and one output control signal. In FIGS. 2A and B, 5...memory matrix, 6...Y selector, 7...X decoder, 8...Y decoder, 9... _A0 to _A7 address input buffer, 10... _A8 ~A ₁₂ address input buffer, 11...output buffer, 12...chip select input buffer, 13...chip enable input buffer, 14...output enable input buffer, 15...A ₀ ~A ₇ address input,
16... _A8 to _A12 address input, 17...CS chip select input, 18...CS1 chip select input, 19...CS2 chip select input, 20...
...Output circuit control input, 21...CE address buffer circuit control input, 22... _A11 address input, 43... _O0 to _O7 data output. FIG. 3A is a partial diagram of the pinout of a packaged integrated circuit having the functionality of FIG. 2A. FIG. 3B is a partial diagram of the pinout of a packaged integrated circuit having the functionality of FIG. 2B. In Figure 3 A and B, 23...positive power supply
V _DD , 24...A ₈ address input, 25...A ₉ address input, 26...CS chip select input, 2
7...A ₁₁ address input, 28...CS1 chip select input, 29...CS2 chip select input,
30...A ₉ address input, 31...Output circuit control input, 32...Address puffer circuit control input. Figure 4 is a sep select circuit diagram. In Fig. 4, a...CS1 chip select input circuit, b...CS2 chip select input circuit, c
...Common circuit with CS, d...Common circuit with CS, e...Common circuit with A ₁₁ address input. FIG. 5 is a diagram showing the connection between polysilicon and metal, and between the diffusion layer and metal using a contact layer. In FIG. 5, 33, 34, 35... polysilicon, 36, 42... metal, 37... diffusion layer, 38, 39, 40, 41... contact layer.

Claims (1)

[Scope of Claims] 1. A memory cell into which data is written using a mask during manufacturing, an external terminal whose function can be selectively set from a plurality of functions, and a memory cell whose function can be selectively set from a plurality of functions, and a memory cell whose function is set selectively from a plurality of functions, and a memory cell whose function is set selectively from a plurality of functions. and a transistor group used in a logic circuit configured to perform signal processing, the transistor group forming a first logic circuit that performs signal processing according to a first function among the plurality of functions. When configuring the first logic circuit with the first transistor group used in the case, or when configuring the second logic circuit that performs signal processing according to the second function of the plurality of functions, a second group of commonly used transistors, and a function of setting the external terminal by forming selective connection wiring within the transistor group using the mask for writing data to the memory cell; What is claimed is: 1. An integrated circuit comprising: selectively configuring a logic circuit that performs signal processing in accordance with the above; and setting one of the plurality of functions to the external terminal. 2. The integrated circuit according to claim 1, wherein the mask is a mask for forming a contact layer. 3. The integrated circuit according to claim 1, wherein the mask is a mask for channel doping.