JP2695734B2 - Storage control device and access request selection method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system control technique, and more particularly, to a process for preventing contention of access destinations between a plurality of access requests to a storage device and improving the transmission efficiency of access requests and accessing the storage device. The present invention relates to a technique which is effective when applied to a storage controller capable of increasing the processing speed at the time of access and an access request selection method therefor.

[0002]

2. Description of the Related Art Conventionally, in a case where access destinations among a plurality of access requests to a storage device conflict with each other, a technique for preventing the conflict between the access destinations is disclosed in Japanese Patent Laid-Open No. 1-2617.
No. 80, a technique based on a priority order determination method, and the like.

For example, as components of a system according to this method, there are a storage device having a plurality of independently accessible storage units and a plurality of access request control devices for issuing access requests to the storage device independently. It comprises an instruction processor and a storage controller between the storage device and the instruction processor.

Further, the access request control device is divided into two access request control groups, storage units are divided into several storage groups by several units, and ports and ports are assigned to the access request control groups and the storage groups. The access paths S0 and S1 to the storage device called are provided.

[0005] In this case, the instruction processor assigns a series of access instructions of vector data composed of a plurality of element data used in the vector instruction to each access request control group, and issues a command to the plurality of access request control devices. Issuance of access requests is assigned to each vector element.

As a method for resolving access contention of access requests issued in parallel by a plurality of access request control devices in units of storage groups, the storage control device first performs contention resolution in each port. One access request is selected, and then the conflict between ports is checked by comparing the access destination storage units of the access requests selected at the S0 and S1 ports.

As a result, when there is no contention between the ports, an access request is sent to the storage device via an access path provided for the storage group and for the port, and when there is contention between the ports, In accordance with the set priority, one access request is sent to the storage device, and the other access request is suppressed.

[0008] The above is a basic conflict resolution method.
In addition, the following special processing is performed. That is, when assigning a vector access instruction to the access request control group, the instruction processor checks the type of the vector access instruction and the access destination.

As a result, this vector access instruction
If the address of the storage device is accessed regularly, the information is added to the access request and sent to the storage control device. Further, when the vector access instruction of both ports is this continuous access, the storage controller predicts the access destination of the access request group included in the preceding vector access instruction.

[0010] Then, a subsequent vector access instruction accesses the predicted storage unit first, so that an access request included in the preceding access instruction waits for a bank busy (a state in which the storage unit is operating). Is predicted, the transmission of the subsequent vector access instruction is suppressed in advance. With this method, it is possible to prevent the processing of the preceding vector access instruction from being disturbed by the subsequent instruction.

[0011]

However, in the prior art as described above, only when the two vector access instructions are continuous accesses, the subsequent instruction is first stored in the storage unit of the access destination of the previous instruction. Access to the previous instruction and prevent the processing of the previous instruction from being interrupted, but in the case of a vector access instruction that is not a continuous access, a similar subsequent instruction is first stored in the storage unit to which the preceding instruction is accessed. Since the process of suppressing access to the URL is not performed, the following problem occurs.

(1) Excessive suppression of access requests In the conventional method, conflicts are resolved in two stages: intraport conflict resolution and interport conflict resolution. In this case, when the two access requests selected in the first stage compete in the second stage, one of them is selected according to the priority order, for example, the S0 side is selected and the S1 side is suppressed.

Here, if the access request not selected in the first stage on the S1 side does not conflict with the access request selected on the S0 side between the ports, if the access request is not suppressed in the first stage, two An access request can be sent. As described above, although two access requests can be transmitted, only one is transmitted, and the access request is excessively suppressed.

(2). Inversion of Priority The processing will be described with reference to the timing chart of FIG. 11, for example. In this case, the access request 5 is sent to the S0 side.
0A, 50B, and an access request 50C on the S1 side.
50A, 50B, 5 in descending order of priority.
0C. The access destinations of 50A to 50C are 50B as storage units 51A, 51B, and 51B, respectively.
And 50C are competing.

Then, according to the priority order, 50 A is set on the S0 side.
(500A), and S1 sends 50C (500A).
C), the storage units 51A and 51B become bank busy (510A and 510B). Here, the access request 50B that has not been transmitted cannot transmit the access request for the bank busy time (time until the processing is completed) because the access destination storage unit 51B is busy.
B). Thus, there is a problem that the 50B is delayed by the bank busy time even though the priority is higher than the 50C (500B, 500C).

Due to this problem, particularly in a vector computer system that performs pipeline processing, a delay in processing of an access request for some vector elements leads to a delay in the end time of the entire instruction sequence. In general, the operation speed of a storage unit is lower than the operation speed of an instruction processor or a storage control device. Therefore, the greater the difference between the operation speeds, the greater the effect on the entire instruction sequence.

Accordingly, an object of the present invention is to solve the above two problems and to provide a plurality of access requests to a storage device in a conflict resolution system in which leakage does not occur depending on the type of vector access instruction. In this case, by checking all combinations of conflicts in advance, an access request that can transmit all access requests to the storage device as fast as possible within a range where the storage units of the access destination do not conflict and the priority does not reverse for one cycle or more is checked. An object of the present invention is to provide a selectable storage control device and an access request selection method therefor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the storage control device of the present invention comprises: n × t access request control devices for independently generating access requests; and a storage device comprising m × s storage units that can be independently accessed. , An access request control device and a storage control device between the storage devices, and t access request control groups in which the access request control devices are grouped every n units and s in which the storage units are grouped every m units. Storage groups and s × t access request selection circuits corresponding to the storage groups and the access request control groups in the storage control device. Are issued to storage units in the storage group corresponding to the access request selection circuit by n access request control devices in the access request control group corresponding to A maximum of one access request is selected from the access requests, and the selected access request is sent to a corresponding storage unit in a corresponding storage group via an access path provided corresponding to the access request selection circuit. A conflict check circuit is provided for each storage group.

In this case, in the conflict check circuit,
A plurality of access destination storage unit comparison circuits and an access conflict type determination circuit are provided.

Further, the storage control device is provided with a priority storage means for retaining a priority set between the access request control devices.

Further, an access request selection signal generation circuit for deciding an access request to be selected in accordance with the form of competition between access request control groups and the priority order is provided in the storage control device.

Further, in the method for selecting an access request of a storage controller according to the present invention, when an access request is selected in the storage controller, when a conflict occurs between different access request control groups, a plurality of conflicting access control groups may be selected. The access request having the highest priority among the access requests is selected first.

[0025]

According to the above-described storage control device and the access request selection method therefor, the contention check circuit is provided in the storage control device in correspondence with the storage group, so that the t access request selection circuits corresponding to the storage group can access. Before selecting a request, the contention check circuit compares the access destination storage units for all combinations of different access request control groups among all the access requests issued to this storage group and performs the contention mode. Is determined, and an access request can be selected by t access request selection circuits in accordance with the contention form.

In this case, a plurality of access destination storage unit comparison circuits and an access conflict type discrimination circuit are provided in the contention check circuit. Compares the access destination storage units of the two access requests in charge of each other and outputs match / mismatch information, and the access conflict type determination circuit outputs a match output from all access destination storage unit comparison circuits in the conflict check circuit. It is possible to determine the type of contention between the access destination storage units of a plurality of access requests handled by the contention check circuit from the information on the / mismatch.

Further, by providing the priority storage means in the storage control device, when selecting an access request in the access request selection circuit, the access request is selected using the priority of the priority storage means. Can be.

Further, by providing an access request selection signal generating circuit in the storage control device, the access request having the highest priority among the conflicting access requests is determined, and the access request among the other access requests is determined. An access request that does not conflict with the access request selected in (1) can be determined according to the priority order.

That is, (1) an access-destination storage unit comparison circuit that checks all access-destination conflicts between access requests having different access request control groups, and (2). (3) priority storage means for holding the priority set between the access request control devices, and (4) both accesses according to the type and priority of the conflict between the access request control groups. By providing an access request selection signal generation circuit that determines an access request to be selected in synchronization with the request control group, it is possible to select an access request for each access request selection circuit.

Thus, when selecting one access request corresponding to each access request control group from a plurality of access requests, the access destination storage unit comparison circuit preliminarily sets different access request control groups connected to the same storage group. The storage units at the access destination are compared between the access requests of all combinations of the above.

Then, the access contention type determination circuit determines the contention type between the access request control groups, and the access request selection signal generation circuit first determines the contention of the access request that has caused the contention according to the contention type between the access request control groups. Select the highest priority access request among them,
An access request that does not conflict with the access request selected from the other access requests is selected and transmitted according to the priority order.

By the above method, the contention is resolved for each access request without considering the vector access instruction, and when selecting an access request, all access requests that can be transmitted within a range in which the priority is not reversed for one cycle or more are selected. Can be sent.

[0033]

FIG. 1 is a schematic diagram showing a computer system using a storage controller according to an embodiment of the present invention, FIG. 2 is a block diagram of the storage controller of the present embodiment, and FIG. 4 is an explanatory diagram showing the assignment of addresses accompanying the access request, FIGS. 5 to 9 are explanatory diagrams showing an outline of the conflict resolution processing in the present embodiment, and FIG. It is a timing chart which shows a delay in case of reverse rotation.

First, the configuration of a computer system using the storage controller of this embodiment will be described with reference to FIG.

The computer system according to the present embodiment comprises, for example, a plurality (2 × 2) of access request control devices that independently generate access requests and a plurality (3 or more × 4) of storage units that can be accessed independently. And a storage control device between the access request control device and the storage device. The two instruction processors 10A, 10A,
10B, four storage control devices 11A to 11D, and a storage device 12.

In the instruction processors 10A and 10B, two access request control units 100A and 10
0B, 100C and 100D, the access request control devices 100A and 100C belong to a first access request control group, and the access request control devices 100B and 100D
D belongs to the second access request control group.

The storage device 12 has four storage groups 120A to 120D.
Instruction processors 10A and 10B corresponding to
The storage control devices 11A to 11D are provided between the storage device 12 and the storage device 12. Then, the storage groups 120A to 120A
D includes a plurality of storage units 1200A to 120A, respectively.
0C, 1200D to 1200F, 1200G to 1200
J, 1200K to 1200M, and the storage unit 12
00A to 1200M is the minimum unit that can be accessed independently.

Each of the instruction processors 10A and 10B has two types of access paths called ports corresponding to the access request control groups, and the one corresponding to the first access request control group. A port corresponding to the S0 port and the second access request control group is called an S1 port.

The computer system of this embodiment uses the storage device 12 using two types of access paths according to the access requests generated by the access request control devices 100A to 100D.
Can be read / written from / to the storage units 1200A to 1200M.

In this case, an address format indicating the access destination of the access request as shown in FIG. 4 is used, and the access request includes the storage units 1200A to 1200A of the access destination.
Lower address 41 for specifying 200M, storage unit 120
An upper address 40 indicating an access destination inside 0A to 1200M accompanies, and although not shown in the figure, an access request is accompanied by a code indicating an instruction type, write data, and the like.

The storage control device 11A has access request holding means 110A, 110C and 110B, 110D corresponding to the access request control devices 100A to 100D, and those corresponding to each other are connected. Here, the access request holding units 110A and 110B are connected to the S0 port, and the access request holding units 110C and 110D are connected to the S0 port.
It belongs to one port and is connected to conflict resolution circuits 113A and 113B provided corresponding to each port.

Access request holding means 110A to 110D
Are connected to a conflict checking circuit 112A in addition to the conflict solving circuits 113A and 113B. The conflict check circuit 112A is connected to the conflict resolution circuits 113A and 113B together with the priority order storage means 111A, and sends out information necessary for conflict resolution. Further, the conflict resolution circuit 113A,
113B is connected to the corresponding storage group 120A via access paths 130A and 130B. The connections in the storage control devices 11B to 11D are the same as in the storage control device 11A.

The access request control device 100A receives a read / write instruction to the storage device 12 in the instruction processor 10A, determines an address of an access destination storage unit, prepares a necessary instruction code, and generates an access request. Let it. Then, the access request holding unit 11 looks at the bit 411 (FIG. 4) for specifying the access destination storage group of the lower address 41 attached to the generated access request.
0A, 110E, 110I, and 110M are sent to the corresponding ones. The access request control devices 100B to 100B
The same applies to 100D.

The storage control device 11A receives an access request to the storage group 120A among the access requests generated by the access request control devices 100A and 100C and the access requests generated by the access request devices 100B and 100D, and sends the request to the access request control devices 100A to 100D of the generation sources. Corresponding access request holding means 1
Hold at 10A to 110D. Of the maximum four access requests, a maximum of two access requests, one for each port, are selected in the storage controller 11A, and the storage groups are selected via the access paths 130A and 130B corresponding to S0 and S1. 120A. The storage control device 1
The same applies to 1B to 11D.

Here, the operation of the storage controller 11A is shown in FIG.
This will be described in detail with reference to FIG.

In the conflict check circuit 112A, there are provided access destination storage unit comparison circuits 23A to 23D for comparing access destinations between two access requests, and a conflict type determination circuit 25 for determining a conflict type from the comparison result. Is provided.

In the priority storage means 111A,
Priority storage bits 21A to 21F for storing priorities between the four access request control devices 100A to 100D (here, between access requests generated by the access request control devices 100A to 100D) are provided.

Now, the access requests 20A to 20D are held in the access request holding units 110A to 110D, and the access destination storage unit comparison circuit 23A is connected to the access request holding unit 1A.
10A, 110C and access destination storage unit comparison circuit 23
B is access request holding units 110A and 110D, and access destination storage unit comparison circuit 23C is access request storage units 110B and 110C and access destination storage unit comparison circuit 2
It is assumed that 3D is connected to access request holding units 110B and 110D.

The access destination storage unit comparison circuits 23A to 23D use the access requests 20 between different ports.
A and 20C, 20A and 20D, 20B and 20C, 20B
And 20D conflicts. This contention check is performed by comparing a bit 410 (FIG. 4) for specifying an access destination storage unit in an access destination address.

Further, the access destination storage unit comparison circuit 23
The result of the comparison at A to 23D is sent to the competition mode determination circuit 25 via lines 24A to 24D, and the competition mode is determined. The signals represented by the lines 24A to 24D correspond to the access destination storage unit comparison circuits 23A to 23A corresponding to "1".
D indicates that a match was detected. In this case, no conflict occurs with an access request that does not exist.

Here, the details of the logic of the conflict type determination circuit 25 will be described with reference to Table 1. As shown in Table 1, there are 12 types of the competition, which are roughly divided into the following five types.

(1) When there is no conflict (2). When two access requests conflict (3). When three access requests conflict (4). Two access requests When two sets conflict with each other (5). When four access requests conflict with each other

[0053]

[Table 1]

In Table 1, item number 2 indicates that only the line 24A is "1", that is, the access destination storage unit comparison circuit 23A detects a match and the access requests 20A and 20C are in conflict.

In item 6, line 24A, 24B is "1", that is, access destination storage unit comparison circuit 23A, 2
3B detects a match, and requests access requests 20A and 20C,
0A and 20D conflict with each other, that is, access requests 20A and 20D.
This indicates that three access requests C and 20D are in conflict. Others are the same.

As described above, a total of 12 pieces of information in the form of contention in Table 1 are transmitted via the line 26, and information on the presence / absence of the access requests 20A to 20D in the access request holding means 110A to 110D is transmitted through the lines 27A to 27D. Via the conflict resolution circuit 1
13A and 113B.

The priority storage bits 21A to 21F
Are prepared for the number of combinations of all two different access requests 20A to 20D, and the priorities among the assigned access requests 20A to 20D are stored. Table 2 shows the access request in charge of each of the priority storage bits 21A to 21F and the contents of the priority represented by the bit value.

[0058]

[Table 2]

In Table 2, for example, priority storage bit 21C is in charge of the priority between access requests 20B and 20C. When the bit value is "0", access request 20B has a bit value of "1". "Indicates that the access request 20C has a higher priority. In addition,
The same applies to the other priority storage bits 21A to 21F.
The priority held by the priority storage bits 21A to 21F is determined by the conflict resolution circuit 1 via the lines 22A to 22F.
13A and 113B.

In the conflict resolution circuits 113A and 113B, access is made from the priority information (lines 22A to 22F), the information on the conflict mode (line 26), and the information on the presence or absence of the access requests 20A to 20D (lines 27A to 27D). Request 20A-2
0D is selected and sent to the storage device 12.

First, an outline of a method of selecting the access requests 20A to 20D will be described with reference to FIGS. In FIG. 5 to FIG. 9, the priority order is represented by upper and lower positions of the access requests 60A to 60D, and arrows passing through the conflict resolution circuits 113A and 113b indicate selection of the access requests 60A to 60D.

(1). When there is no contention (see FIG. 5) Access requests 60A, 60C, 60F, and 60H having a high priority are selected for each port according to only the priority.

(2) Two access requests 61A and 61C,
When 61F and 61H compete (see FIG. 6): conflicting access requests 61A and 61C, 61F and 6
1H, access requests 61A, 61 having higher priority
Select F. The access requests 61A and 61F have different ports and are not included in the conflict.
D and 61G are also selected.

(3) When three access requests 62B, 62C and 62D compete with each other, and 62E, 62F and 62G compete (see FIG. 7). Conflicting access requests 62B, 62C and 62D, 62D
The access requests 62B and 62E having the highest priority are selected from 2E, 62F and 62G. If there is an access request 62H that is different from the ports of the access requests 62B and 62E and is not included in the conflict, this is also selected.

(4). Two access requests 63A and 63C,
63B and 63D, 63E and 63G, 63F and 63H are 2
When there is a group conflict (see FIG. 8), of all the access requests 63A to 63D and 63E to 63H, the access requests 63A and 63E having the highest priority order
Select Among the two sets of two mutually conflicting access requests 63B and 63D, 63F and 63H which do not conflict with the access requests 63A and 63E, the access requests 63A and 63E which are selected first and have the highest priority. If the ports are different, this access request 63H is selected.

(5) Four access requests 63A to 63D,
When 63E to 63H compete (see FIG. 9), access requests 64C and 64F having the highest priority among all access requests 63A to 63D and 63E to 63H.
Select

The conflict resolution circuit 113 using the above policy
The specific processing of A and 113B will be described in detail with reference to FIG.

The conflict resolution circuit 113A is divided into an access request selection signal generation circuit 30A and an access request selection circuit 32A, and includes a signal (line 26) indicating a conflict mode, a signal indicating a priority (lines 22A to 22F), Access request 20
A signal (lines 27A to 27D) indicating the presence or absence of A to 20D is received by the access request selection signal generation circuit 30A, and access request selection signals 31A and 31B are generated. Similarly, in the conflict resolution circuit 113B, the access request selection signals 31C, 3C
Generate 1D.

In this case, the access request selection signal 31A
Indicates "1", the access request 20A held in the access request holding unit 110A is selected. Similarly, when the access request selection signals 31B to 31D indicate "1", the access requests 20B to 20D are similarly selected. Here, the access request selection signals 31A and 31B and 31C and 31D do not become "1" at the same time.

Then, the access request selection signal 31A
Through 31D, 0-1 access requests 20A-2 selected by the conflict resolution circuits 113A and 113B, respectively.
0D is stored in the corresponding storage unit 12 in the storage group 120A via the corresponding access path 130A, 130B.
00A to 1200C.

Further, the access request selection signal generation circuit 3
The detailed logic of 0A and 30B is shown in Table 3 using a truth table. The access request selection signal generation circuits 30A, 30
B determines the access requests 20A to 20D to be selected in synchronization with each other according to the contention mode. Therefore, for convenience, in Table 3, the logics of the access request selection signal generation circuits 30A and 30B are shown together in one table, and in the table, the case where the priority order storage bits 21A to 21F are inconsistent is omitted.

[0072]

[Table 3]

Here, some items will be taken as examples of the contention form of the access requests 20A to 20D, and the contents of Table 3 will be specifically described.

(1) When No. 7 Does Not Conflict Access requests 20A and 20B exist and access request 2
Since the information (line 22E) indicating the priority between 0A and 20B is "0", that is, the priority of the access request 20A is higher than that of the access request 20B, the access request selection signal 31A is "1".
And the access request 20A is selected.

(2) Item No. 12 is access requests 20A and 20A
When C conflicts Since the information (line 22A) indicating the priority between the access requests 20A and 20C is "0", that is, the priority of the access request 20A is higher than that of the access request 20C, the access request selection signal 31A is "1". And the access request 20 on the port 0 side
Select A.

Further, there is an access request 20D on the port 1 side which does not conflict with the access request 20A, and the access request selection signal 31D becomes "1" to select this.

(3) Item No. 27 is access requests 20A and 20A
When C and 20D compete, information indicating the priority between the access requests 20A and 20C (line 22A) is "0", and information indicating the priority between the access requests 20A and 20D (line 22B) is "0". That is, the priority of the access request 20A is changed to the access request 20C,
Since it is higher than 20D, the access request selection signal 31A becomes "1", and the access request 20A on the port 0 side is selected.

The port 1 side receives an access request 20C,
Nothing is transmitted because both 20D conflict with the access request 20A.

(4) Item No. 33 is access requests 20A and 20A
In the case where B and 20C are competing, in the same manner as in No. 27, the port 0
Select A. The port 1 side has an access request of 20A.
There is an access request 20D that does not conflict with the access request 20D, and the access request selection signal 31D becomes "1" to select this.

(5) Item No. 47 is access requests 20A and 20A.
When C, 20B and 20D are competing respectively, the information (line 22A) indicating the priority between the access requests 20A and 20C is “0”, and the information (line 22B) indicating the priority between the access requests 20A and 20D is “0”. “0”, information indicating the priority between the access requests 20A and 20B (line 22)
E) is "0", that is, the priority of the access request 20A is the highest, the access request selection signal 31A becomes "1", and the access request 20A on the port 0 side is selected.

Information indicating the priority of the priority storage bit 21D between the access requests 20B and 20D (line 22).
D) is “1”, that is, the access request 20 on the port 1 side
D has a higher priority than the access request 20B, the access request selection signal 31D becomes “1”, and the access request 2
Select 0D.

(6) Item No. 48 is access requests 20A and 20A
C, 20B and 20D are in conflict with each other.
Select A. Information indicating the priority of the priority storage bit 21D between the access requests 20B and 20D (line 2).
2D) is “0”, that is, access request 2 on the port 1 side
The priority of 0D is lower than that of the access request 20B, so that the port 1 side does not send anything.

(7) Item No. 63 is the access request 20A, 20
B, 20C and 20D are all in conflict. Priority storage bit 2 between access requests 20A and 20C
Information indicating the priority of 1A (line 22A) is “0”, and information indicating the priority between access requests 20A and 20D (line 2).
2B) is "0", the information (line 22E) indicating the priority between the access requests 20A and 20B is "0", that is, the priority of the access request 20A is the highest, and the access request selection signal 31A is "1". Select the access request 20A.

The same applies to other item numbers.

Here, the effects of the problems shown in the above-mentioned problem column after countermeasures according to this embodiment will be described.

(1) Measures against excessive suppression of access requests 20A to 20D The priority of access requests 20A to 20D is 20A, 20
B, 20C, and 20D in the order of the access requests 20A, 20A.
C is competing. This corresponds to item No. 12 in Table 3.
In this case, according to the conventional method, the access request 20A at the S0 port and the access request 20C at the S1 port are determined according to the priority order.
Are selected, and since the access requests 20A and 20C conflict, only the access request 20A is transmitted according to the priority order, and the access request 20C is suppressed.

However, according to the method of this embodiment, Table 3
As shown in (1), the access requests 20A and 20D can be sent out, thereby preventing the access requests from being excessively suppressed as in the conventional system.

(2). Countermeasures against reversal of priority This corresponds to item 19 in Table 3, and the effect of the processing is shown in FIG.
This will be described with reference to the timing chart of FIG. That is, among the access requests 50B and 50C competing between the ports, the access request 50B on the S0 side having the higher priority is transmitted (502B). By doing so, the storage unit 5
In 1B, the access requests 50B, 50C follow the priority order.
(512B, 513B).

Here, since the access request 50B is the same S0 port as 50A, the access request 50B precedes the access request 50A with the highest priority (502A, 502B), and the reverse occurs. However, since the storage unit 51A of the access destination of the access request 50A does not become bank busy, it can be transmitted in the next cycle (502A, 512A). As a result, the delay when the priority is reversed can be reduced to one cycle.

Therefore, according to the computer system of this embodiment, the access destination storage unit comparison circuits 23A to 23D and the conflict type determination circuit 2 are provided in the storage control devices 11A to 11D.
5, conflict resolution circuits 113A to 112D having priority order storage means 111A to 111D, access request selection signal generation circuits 30A and 30B, and access request selection circuits 32A and 32B.
13H, access conflicts between access requests 20A-20D of different access request control groups are checked in advance, and access requests 20A-20
D can be selected from those having the highest priority among the competing ones of D, so that the access requests 20A-2A
Delay due to excessive suppression of 0D and inversion of priority can be reduced, and the processing speed of access requests 20A to 20D can be increased.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, in the computer system of the present embodiment, 2 × 2 access request control devices 100A to 100A-1
00D and 3 or more × 4 storage units 1200A to 120
A case has been described in which the storage control devices 11A to 11D each having 4 × 2 access request selection circuits 32A and 32B are connected between the storage device 12 and the storage device 12 composed of 0M. It is needless to say that the present invention is not limited to this, and that the present invention can be applied to other device configurations of less than or more than this number.

In this case, in particular, any device configuration in which the relationship of n × t access request control devices, storage devices composed of m × s storage units, and s × t access request selection circuits is established. The access request control group and the storage group may be set to t and n to s, respectively.

[0094]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, a conflict check circuit having a plurality of access-destination storage unit comparison circuits and an access conflict type discriminating circuit corresponding to a storage group is provided in the storage controller, and a priority storage means and an access request selection signal generation signal are further provided. With the provision of the circuit, when selecting an access request corresponding to each access request control group from a plurality of access requests, the access destination storage unit comparison circuit preliminarily selects all of the different access request control groups connected to the same storage group. Comparing the storage unit of the access destination between the access requests of the combination of, the access contention type determination circuit determines the contention type between the access request control groups,
Then, the access request selection signal generation circuit first selects the access request with the highest priority among the plurality of competing access requests according to the contention mode between the access request control groups, and selects the access request among other access requests. Since an access request that does not conflict with the given access request can be selected according to the priority order, the conflict can be resolved in access request units without being aware of the vector access instruction.

As a result, it is possible to select all access requests that can be transmitted within a range that does not reverse the priority of the access requests for one cycle or more, thereby improving the transmission efficiency of the access requests without disturbing the priority of the processing of the access requests. Further, it is possible to obtain a storage control device capable of increasing the processing speed when accessing the storage device.

In particular, since the delay when the priority is reversed is reduced from the access time to the storage unit to one cycle, the sinking of a part of the read / write operation of the instruction sequence for performing the pipeline processing is prevented. A storage control device capable of improving processing efficiency can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a computer system using a storage control device according to one embodiment of the present invention.

FIG. 2 is a configuration diagram of a storage control device of the present embodiment.

FIG. 3 is a detailed view of a main part of the storage control device of the present embodiment.

FIG. 4 is an explanatory diagram showing assignment of addresses accompanying an access request in the embodiment.

FIG. 5 is an explanatory diagram illustrating an outline of a conflict resolution process when there is no conflict process in the embodiment.

FIG. 6 is an explanatory diagram illustrating an outline of a conflict resolution process when one set of two access requests conflicts in the present embodiment.

FIG. 7 is an explanatory diagram showing an outline of a conflict resolution process when three access requests conflict with each other in the embodiment.

FIG. 8 is an explanatory diagram illustrating an outline of a conflict resolution process in a case where two sets of two access requests conflict with each other in the embodiment.

FIG. 9 is an explanatory diagram illustrating an outline of a conflict resolution process in a case where all four access requests conflict with each other in the embodiment.

FIG. 10 is a timing chart showing a delay when the priority is reversed due to a conflict in the embodiment.

FIG. 11 is a timing chart showing a delay in the case where priorities are reversed due to contention in an example of the related art.

[Explanation of symbols]

 10A, 10B Instruction processor 11A to 11D Storage controller 12 Storage device 20A to 20D Access request 21A to 21F Priority storage bit 22A to 22F line 23A to 23D Access destination storage unit comparison circuit 24A to 24D line 25 Competition type discrimination circuit 26 line 27A-27D line 30A, 30B access request selection signal generation circuit 31A-31D access request selection signal 32A, 32B access request selection circuit 40 upper address 41 lower address 50A-50C access request 51A, 51B storage unit 60A-60H access request 61A- 61H access request 62A-62H access request 63A-63H access request 64A-64H access request 100A-100D access request control device 110A-110P access request holding means 111A to 111D Priority storage means 112A to 112D Conflict check circuit 113A to 113H Conflict resolution circuit 120A to 120D Storage group 130A to 130H Access path 410,411 bits 1200A to 1200M Storage unit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mihoko Hashiba 1st Horiyamashita, Hadano City, Kanagawa Prefecture General Computer Division, Hitachi, Ltd. (56) References JP-A-3-296154 (JP, A) JP-A Heisei 1-261780 (JP, A) JP-A-64-91273 (JP, A) JP-A-59-165160 (JP, A)

Claims (5)

(57) [Claims] An nxt access request control device that independently generates an access request and an mx access device that can access independently.
a storage device composed of s storage units and a storage control device between the access request control device and the storage device, wherein t access requests in which the access request control devices are grouped every n units A control group and s storage groups in which the storage units are grouped every m are set, and s × t access requests corresponding to the storage group and the access request control group are set in the storage control device. A selection unit, wherein each of the access request selection circuits comprises a storage unit in a storage group corresponding to the access request selection circuit, wherein n access request control devices in the access request control group corresponding to the access request selection circuit are provided. , And selects at most one access request from the access requests issued to the access request selection circuit, and via an access path provided for the access request selection circuit, A system for sending to a corresponding storage unit in a corresponding storage group, wherein a conflict check circuit is provided in the storage controller in correspondence with the storage group, and the access request is selected by t access request selection circuits corresponding to the storage group. Prior to selecting the storage mode, the contention check circuit compares the access destination storage units for all combinations of all access requests issued to the storage group, which are different access control groups. A storage control device, wherein an access request is selected by the t access request selection circuits according to the contention mode. 2. A plurality of access destination storage unit comparison circuits and an access conflict type discrimination circuit are provided in the contention check circuit, and each access destination storage unit comparison circuit is in charge of the access destination storage unit comparison circuit. Comparing the access destination storage units of the two access requests to output match / mismatch information, and the access conflict type determination circuit outputs the match output from all access destination storage unit comparison circuits in the conflict check circuit. 2. The storage control device according to claim 1, wherein the type of contention between access destination storage units of a plurality of access requests handled by the contention check circuit is determined from the information on the mismatch. 3. The storage control device further comprises a priority storage unit for storing a priority set between the access request control devices, wherein the priority is stored when the access request is selected in the access request selection circuit. 3. The storage control device according to claim 1, wherein the access request is selected using the priority order of the order storage means. 4. An access request selection signal generation circuit for deciding an access request to be selected in accordance with a form and a priority of competition between access request control groups in said storage control device, wherein The access request having the highest priority is determined, and an access request that does not conflict with the access request selected from other access requests is determined according to the priority. The storage control device according to any one of the preceding claims. 5. A storage controller according to claim 1, wherein, when an access request is selected, when a conflict occurs between different access request control groups, a plurality of conflicting access requests are selected. An access request selection method for a storage controller, wherein an access request having the highest priority is selected first.