JPS60136849A - Storage control system - Google Patents

Abstract

PURPOSE:To improve transfer efficiency by dividing access requests generated from respective access request control devices into units each of which consists of m access requests, and while guaranteeing the order of reading data, replacing the order of generation of access requests to a storage device. CONSTITUTION:The access requests generated from the unshown access request control devices are divided into groups each of which consists of (m) access requests, access request indentifying elements 0-(m-1) are added to respective groups and the indentifying element-added groups are sent to a priority determining circuit 80. Since the circuit 80 returns the access request identifying element to said access request control device generating the access request, the access request control device can generate at least m access requests continuously and unconsciously whether these access requests are selected or not. If the signal selected for the 1st generated access request (identifying element ''0'') by said circuit 80 is returned, an access request having the identifying element (0) can be continuously generated after the access request having the identifying element (m-1).

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a storage control method for a uniform storage system, and more particularly, to a storage control method that guarantees orderliness between consecutive accesses issued to a storage device. This is how it was done.

[Background of the invention]

A conventional storage control system will be explained with reference to FIG.

In FIG. 1, reference numerals 1, 2, and 5.4 are access request control devices, which are sources that issue access requests. 5, 6,
7.8 is an access soft water stack device which stacks access requests issued from access request control devices 1, 2, and 5゜4, and prioritizes access requests in the stacked order according to their address information. It is sent to any of the ranking determining devices 9, 10, 11, and 12. 15 is a storage device consisting of storage banks 13A, 13B, 13C, and 13D.

Regarding the access request control device 1, the access request issued from the device 1 is stacked in the stack 5A in the access request stacking device 5, and the address of the access request in the storage device 16 is stacked in the stack 5A in the access request stacking device 5. is sent to the access water absorption priority determining device corresponding to the storage bank indicated by. The access watering priority determination devices 9, 10, 11.12 prioritize the access requests sent from the access request stack devices 5, 6.7.8, select one of them, and send it to the storage device 16. Send to.

Regarding the access request priority determining device 9, the access request stacking device 5, 6, 7.8
A priority determination logic 9A determines the priority order among the access requests sent from the access requests, and one of the access requests is selected and sent to the storage device. Access requests that are not selected at this time are kept waiting at the entrance of the priority determination logic 9A.

Here, the access request is stored in the access request stack device 5.
Access requests are sent from the control device 1 until the stack 5A is full. 1, from the access request stack device M5, the previous MC (MC: Machine Cyc
The access watering priority determining device 9 receives a signal 5D indicating that the access request 5C issued during a periodic constant time interval in which the sequential circuit groups constituting the 7 stems operate synchronously. Upon return from , a subsequent access request 5C is sent. This is a control method necessary to ensure that the access data is read from the storage device 16 in the order of the access requests issued by the access request control device 1. In order for the access requests 5C to be sent from the request stack device 5 at a pitch of 1 MC, as shown in FIG. After the selection signal (Ack
-) needs to return to the access request stack device 5,
If it does not return to the same MC, for example, as shown in FIG.
ty ) extends over 2 MCs, the decision on whether to issue subsequent access requests is postponed until 2 MCs later, and as a result, the access request 5C from the abstract access security stack device 5 is MC pitch, which leads to a deterioration in the performance of the entire device.

On the other hand, in order to improve the performance of the overall system, a large number of access request control devices and access request stack devices have been provided, and multiple storage banks that can operate independently have been provided. With this increase in the amount of hardware, the physical spread of the 7λth mechanism that determines the priority fi1 among access requests and the complexity of the implementation circuit have increased, resulting in an increase in the number of access requests 1 until receiving a signal indicating that has been selected
It would be impossible to achieve this within MC. Therefore, even if the hardware is increased as described above for the purpose of improving performance, the problem arises that the access request issuing pitch from the access request control device decreases and the performance of the entire system is not improved.

Furthermore, in the above configuration, since there is a membership fee that guarantees the order of successive data corresponding to consecutively issued access requests, access requests issued from the access request control device are processed by the access request priority determining device. Subsequent access requests cannot be issued unless selected by .

As a result, a situation occurs in which subsequent access requests of the same access request controller cannot be sent even though they can be processed by one of the multiple storage devices, and this causes access requests to be issued. This not only leads to a decrease in pitch but also to a decrease in the usage rate of the storage device, which is a factor that significantly reduces system performance.

[Purpose of the invention]

An object of the present invention is to provide an access request control system that allows a large number of access request control devices to issue access requests at every clock pitch while guaranteeing the order of read data in response to access requests.

[Summary of the invention]

The key point of the present invention is that in an access operation for a series of data such as vector data, the accesses issued by the access request control device are divided into groups of m groups in the order of occurrence of requests, and each of the %m access requests is 0~(+7l-
1) The access request is issued with the access request identifier added, and the access request priority determining device directly connected to one of the storage units issues the access request's Yumiya Besshi, which indicates that the issued access request has been selected. By returning the access request to the access request control device that issued the request, the access request control device can continuously issue access requests up to the minimum amount (fil) without being aware of whether or not they have been selected by the access request priority determining device. It is about making it possible to do.

Furthermore, the access request issued 14th time (identifier l01)
If the signal indicating that the device has selected the device has returned, the access request with the identifier (01) is issued consecutively following the access request with the identifier (m-1). This makes it possible to issue successive access requests in the same manner thereafter.

On the other hand, a read data control device that sends read data in response to an access request to the access request issuer recognizes the discriminator t attached to the read data and stores the data in a buffer position corresponding to the identifier. The gator sends the data to the data requester in the order of the identifiers. This makes it possible to guarantee the order of successive data corresponding to access requests issued without checking the signal indicating selection by the priority determining device that is sent back to the access request control device. .

[Embodiments of the invention]

FIG. 6 shows an example of the configuration of the main parts of a computer system employing an embodiment of the present invention. Here, the computer system includes an arithmetic unit 20, a plurality of (four in this embodiment) access control devices 40, 41, 42, 43. Storage control device 50. Storage device 60. A vector register device @30 is provided which serves as a data buffer between the storage device 6O and the arithmetic device.

The storage device 60 includes a plurality of (four in this embodiment) storage panchromatic 00.6'IO, each of which can be accessed independently.
It consists of 620 and 80.

In Fig. 4, the memory panchromatic 00, 610° 620 of Fig. 3 is shown.
．． An example of the configuration of the storage control device 5O including the storage controller 630 is shown. The storage control device 50 includes an access request stack circuit 70A,
70B, 70C, 70D, priority j song position determination circuit 80. Access request identifier control circuits 81A, 81B, 81C, 8
1D, read data transfer circuit 85, read data buffer circuits 90A and 90B.

Consists of 9 QC and 90D.

The access request containing the address information of the storage device to be referenced issued by the access request control device is sent to the access request stack circuits 70A and 70 provided corresponding to the device.
B, 70C, 70D, here, for example, arrives at 70A. The ACMOS request that arrives at the access friend request stack circuit 70A is sent to the stack position indicated by the input control circuit 71.
o (72a).

81 (72b), 52 (72c), or 55 (72d), for example, is set in stack 3o (72a) here. The input control circuit 71 selects stack positions IQ1 to IQ1 (So(72a) to
55 (corresponding to 72a)) to the stack signal 71a.
Each time one access request is stored in the stack, the signal 71a indicating the next stack position to be stored is sent to 10+ → 111 → 121 → 13 → IQ+.
・Send as follows.

On the other hand, Star, Tsuku 5o (72a), 51 (72b).

The access requests stored in 82 (72c) and 53 (72d) are sent from the stack position indicated by the output control circuit 74, for example, the stack 3o (72a), via the selection circuit 76 to the priority determination circuit 8O. Here, the output control circuit 7
4 is the stack position where the access request should be taken out + 01
The value of −151 is indicated by the signal 74a, and the value is changed every time an access request is output like IQI→°1°→゛2°→“3゛→'0°” in the same way as the input control circuit. It is sent to the selection circuit 76. However, the output control circuit 74 is the input control circuit.

The point that is approximately 71 and 4 is the stack 30 (72a).

Access request sending control clip-flop 73 corresponding to 31 (72b), 52 (72c), and 55 (72d)
The output of the access request from the stack is controlled by the values of a, 75b, 73c, and 75d.

If the access request sending control clip-flop 75a corresponding to the stack that the output control circuit 74 attempts to take out, for example S O (, 72a), is 111, the access to the stack 5o (72a) will be accessed by the priority determining circuit 8.
0, while the flip-flop 75a outputs 101
Then, the access request is sent f3 from the stack 50 (72a) until the clip-flop 73a is set to 11- by the access request sending control circuit 75:
411+ is stopped, and the stack number of the signal 74a sent by the output control circuit 74 is also controlled to be held lot K.

Note that when the clip flop 73a goes +1- and takes out an access request from the corresponding stack S'0 (72a) and sends it to the priority determination circuit 80, the output control circuit 74 sends information that it has been sent to the access request. The value of the knob 75a of the knob 70 is reset to IQ+ through the Yasugi transmission control circuit 75. Furthermore, in order to avoid conflicts between storage and retrieval of access requests to the stack, the input control circuit 71 and the output control circuit 74
Stack numbers 10I to +51 indicated by 1 are output control circuits 7
A value 0 to 3 larger than the stack number indicated by 4 (rnod,
In the addition of 4, the stack numbers IQ1 to IQ3I indicated by the output control circuit 74 are controlled to be smaller than the stack numbers indicated by the input control circuit 71 in the addition of 4. . Therefore, in order to guarantee this stack value relationship, if necessary, stack 80
(72a), 51 (72b), 52 (72c), 33 (
storage and retrieval of access requests to 72d).

On the other hand, the access request 76a sent to the priority order determination circuit 80 includes, for example, the address information stored in the stack 5o (72, a), as well as the request identifier generation circuit 77a.
, 77b, 77c, and 77d, access request identifiers (00, 01, 02, 05) indicating the number and stack number of the stored access request stack device 70A
), for example, 00 corresponding to the stack 50 (72a).

The access request 76a that has arrived at the priority order determination circuit 80 is stacked in another access request stack circuit 70B for each storage bank that it wishes to access.

Priority is determined between the access requests sent from 70C and 70D, and if a selection is made, the access request 80a is sent to the storage bank to be accessed, for example MS o (600).

With the sending of this access request 8'Oa, the access request identifier 80b is changed to the access request identifier control circuit 81A.
(or 81B, 81C, 811)) and is sent to the access request stack circuit 70A, 70B, 7 of the access request issuer by the access request identifier decoder 82.
0C, 70D is recognized and, for example, if the access luxury identifier is one of 00, 01, 02, or 03, the access request identifier 75a indicating that the access request has been sent to the storage bank is sent to the access request sending control. It is sent back to circuit 75. In the access request sending control circuit 75, based on the returned access request identifier, the corresponding access request sending control flip 70 tabs 73a, 73b, 75c,
Set 73d to +1°.

For example, if the returned access request identifier is 00,
The flip-flop 75a is set to Ml. As a result, subsequent access requests stored in the stack 5o (72a) can be sent to the priority determination circuit 80.

On the other hand, the read data 600a corresponding to the access request 80a sent to the storage bank MSO (60 entries) is
The access request identifier buffer 83 adjusts the time with the memory bank access, and sends it to the read data transfer circuit 85 together with the access request identifier aXa. In the read data transfer circuit 85, based on the access request stack circuit number indicated by the access request identifier, the successive data buffer circuits 9 (IIA, 9GB, 90C) respectively correspond to the access request stack circuits 70A, 70B, 70C, 70L).

90D K successive data, access request identifier, e.g. 8
Distribute 5a and 85b. Read data buffer circuit 90
In A, input control times #! r91 is access request identifier 8
5b and the value 00°0112.00°0112.
Data buffers B0 (94a) and B1 (corresponding to 05)
94b), B2 (94c), or B5 (94d), for example, if the identifier 85b is 00, Bo (94a)
Continuation data 85a is stored in .

At the same time, data validity display flip-flops 95a, 95b, and 95c corresponding to the data buffers.

95d, for example, if the identifier 85b is 00, the 7 lip-flop 95a is set to '11'.

On the other hand, independently of the storage in the data buffer, the output control circuit 92 outputs Bo(94a)y>·et B1(94b).

B2 (94c), B3 (94d) and 1st consecutive data are sent to the access water irrigation control device via the selection circuit 96. However, the data validity display flip-flop 95a corresponds to the buffers 94a, 94b, 94c, and 94d that the output control circuit attempts to take out.

If 95b, 95c, and 95d indicate IQI, sending of the read data to the access request control device is inhibited.

Data transmission to the access request control device is delayed until 95d is set to lit. Further, when read data is sent from the data buffer to the access request control device, for example, if it is from the data buffer BO (94a), the corresponding data validity display clip-flop 9
5a to "0I".

As explained above, according to this embodiment, on the access request sending side, it is possible to send four consecutive access requests to the storage bank in random order, and the preceding access requests This eliminates the problem that subsequent access requests are forced to wait because they cannot be sent to the storage bank, and it becomes possible to overtake up to three access requests.

As an example, 5 inputs to the access request stack circuit
Let's think about individual access Yasugi. Assuming that the five access requests are AO, AI, A2゜Al, and A4, first 4
access requests AO, AI, A2, A3 are stacked SQ, (72a), Sl (72b), 52, respectively.
(72c), 53 (72d). The access requests are sequentially sent from the stack 50 (72a) to the priority determination circuit, and the stack 50 (72a) is sent to the next MC (Machine Cy) to which the access request A0 was sent.
cle), the access request A4 is stored. Note that the access request sending control flip-flops 73a, 73b, 73c, which correspond to the stack that sent the access request,
73d is “Reset to 01.

The access request selected by the priority determination circuit 80 and sent to the storage bank sends its identifier back to the access request sending control circuit 75. Here, assuming that AIs other than access request A0; A2, A3 are sent to the storage bank, the seven lip-flops 73b, 75c, 76
d is set to +1+. Unfortunately, at this stage, the order of sending data to the storage banks has been changed within the range of four access requests. However, since the access request sending control clip-flop 75a corresponding to the stack 80 (72a) is not set to 1°, the access request A4 is suppressed from being sent to the priority determination circuit, and the output control circuit 74 The stack position from which to take out is also 50 (72a), that is, the value IQ+ -1. It will be retained. Therefore, the sending order to the storage bank will not be changed beyond the range of four access requests.

On the other hand, on the read data buffer side, the output control circuit 92 controls the buffer from which successive data is taken until the read data corresponding to the access request A0 arrives at the buffer BO (94a) and sets the read data valid display clip-flop 95a to 11+. The position is maintained as shown in the BO (94a), and the order of read data is not disturbed within the range of four access requests. Furthermore, for the range of access requests exceeding four, the ordering r is guaranteed on the access request sending side as described above, and the order of the corresponding read data will not be disrupted.

Therefore, in the present invention, it is possible to completely guarantee the order of read data supplied to the access request control device.

〔Effect of the invention〕

According to the present invention, in access requests issued by a plurality of access Yasugi control devices, the access requests of each access request control device are divided into units of m pieces, and the order of the read data is guaranteed. Since the issuing order to the storage device can be changed within the scope of the access request,
Even in a storage control device equipped with a complex multi-stage priority determination circuit, access requests can be issued from the access request control device at every clock pitch, and the number of access requests issued from the same access request control device can be within the range of m. If so, it is possible to completely change the order of access requests that can be accepted by the storage device and process them, increasing the usage rate of the storage device 4, which has the effect of significantly improving the access request processing capacity of the storage control device. There is.

In this embodiment, one memory bank is associated with a set of access request receiving/outputting data port (boat), but in general, the operation of the memory elements within the memory bank is controlled by a storage control device, etc. Since the speed is relatively low, a configuration may be adopted in which one bank is shared among a plurality of storage banks.

Furthermore, although a simple priority determination circuit is shown in this embodiment, as the number of access request control devices and storage banks increases, a multi-stage priority determination circuit or a network configuration priority determination circuit may be used.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the configuration of a conventional he storage control device;
The figure shows the relationship between the time required to determine the first priority and the access request issuance pitch, and FIG.
FIG. 4 is a diagram showing an example of the configuration of the storage control device shown in FIG. 6. 70A, 70B, 70C, 70D...Access request stack circuits 73a, 75b, 75c, 75d...Flip-flops for access request transmission control 71...Input control circuit 74/Output control circuit 75...Access request Sending control circuit 82...Access request identifier % firearms 77a, 77b
, 77c, 77d...access request identifier generation circuit 91
... Input control circuit 92 ... Output control circuits 95a, 95b, 95c, 95d - Flip-flop for displaying read data validity 1st mth 21i1EI ((b'') /MC 1--1111th 32nth 4vJ ``

Claims (1)

[Scope of Claims] (1) A plurality of access request control devices independently generate access requests to a storage device composed of a plurality of independently accessible storage units, and the access request is made for each storage unit. In a storage control method that determines the priority among requests and sends the selected access request to the corresponding storage unit, the access request of the control device is requested even for access requests generated by multiple access request control devices. Divide into m groups in the order of occurrence, add an access request identifier of 0 to (m-1) to each of the m access requests, and determine access request priority for each storage unit. A storage control method 0 characterized in that a storage control method 0 ( 2) In a device that generates an access request with an access request identifier, reset the access request at the time the access request is sent, and set the access request at the time the access request is selected in a ten-stage request priority determination system provided for each storage unit. The storage control system according to claim 1, characterized in that it has all seven lip-flops corresponding to access request identifiers. (6) The storage control system according to claim 1, further comprising a read data buffer having a similar function of storing data read from the storage device in a position corresponding to an access request identifier. (4) In a read data buffer that stores read data from a storage device in a position corresponding to an access request identifier,
A flip/70-bit storage control system that is set when read data is written to the position corresponding to the access request identifier of the buffer and reset when it is read from the buffer.