JP2693442B2 - Recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a recording apparatus such as a thermal inkjet printer capable of performing gradation recording in 2 ⁿ steps for each dot. (Prior Art) Conventionally, as a recording device capable of performing gradation recording in 2 ⁿ steps for one dot, there is a thermal ink jet printer specified in Japanese Patent Application No. 60-156502.
As a method of performing gradation recording by this type of thermal inkjet printer, a method of expressing a pseudo halftone by performing dither processing on recording image data and a dot having a low density for one dot There is a method that is realized by repeatedly striking a plurality of times. In the method of expressing a halftone in a pseudo manner by performing the dither processing, an m × n dot matrix is configured to have a gradation pattern of m × n + 1 stages,
The image data for recording is dithered by this gradation pattern (dither pattern). However, in the case of gradation recording using the above-mentioned dither processing, the resolution and the gradation are in conflict with each other, and if the gradation is emphasized, the resolution is lowered, and if the resolution is emphasized, the gradation is lowered. For this reason, the print quality of the obtained output is deteriorated depending on how the dither pattern is taken, and moire, blurring, and unevenness may occur. On the other hand, in the method of obtaining the gradation degree by the dot overprinting, when n gradations are obtained, 1 / of the density difference of white / black is obtained.
Dots having a density of (n-1) are overlapped until reaching a target gradation. Gradation recording by overprinting of dots uses the head printing time as a parameter, and the application time of the voltage applied to the thermal head (recording head) by the head drive circuit that outputs 2 ⁿ gradation levels per dot. The recording density (printing density) is changed by controlling the print density according to the gradation data. Therefore, in the thermal inkjet printer in which the head drive circuit is assembled outside the thermal head, the circuit scale becomes very large, which leads to an increase in the size of the apparatus (thermal inkjet printer). Further, when gradation recording is performed by dot overprinting, the time required for recording one dot increases as the gradation degree increases. This is because the output based on the binary level of white / black is performed by driving the head once for each dot, whereas the output by gradation recording is performed by driving the head multiple times for one dot. It For this reason, the time required for output depends on the number of over-strikes, and there is a problem that output takes time. (Problems to be Solved by the Invention) In the present invention, in the method of performing gradation recording by utilizing dither processing, the print quality is deteriorated, and in the method of performing gradation recording by overlapping dots, the apparatus is large. In addition, the problem that the output takes a long time is eliminated, so that the deterioration of the print quality can be avoided, the size of the entire device can be reduced, and the recording speed can be increased. The purpose is to provide. [Structure of the Invention] (Means for Solving the Problems) In the recording apparatus of the present invention, recording is performed by mounting a head drive circuit corresponding to each dot as a component of the head to drive the recording head. In the apparatus, the head drive circuit holds the input gradation data represented by binary n bits corresponding to one dot by a shift clock pulse change, and a floor held by the shift register. A latch circuit that latches the measurement data in correspondence with a latch signal and a comparison signal that is output in binary n bits, and updates the comparison signal in a specific order in response to a clock signal of a predetermined cycle. The output counter and the comparison signal output from this counter are compared with the gradation data latched by the latch circuit, and the two do not match. The signal of the first level is output during the interval, and when they match each other, after that, until the time required for the gradation data to reach the maximum density is reached, Comparing means for outputting signals of different second levels, and the first means from the comparing means.
Output means for outputting a drive signal that changes based on the output time of the signal of the level of, and in the initial state, the comparison means is reset so as to output a specific initial comparison signal, and the clock signal is input to the comparison signal. And a means for canceling this blocking state when the head is energized. (Operation) According to the present invention, in a recording apparatus for driving a recording head by mounting a head drive circuit corresponding to each dot as a head constituent component, the head drive circuit is input 1
Gradation degree data represented by binary n bits corresponding to a dot is held by a change in a shift clock pulse, the held gradation degree data is latched in correspondence with a latch signal, and a comparison signal represented by binary n bits is stored. To output,
The comparison signals are updated and output in a specific order corresponding to a clock signal of a predetermined cycle, the output comparison signal and the latched gray scale data are compared, and when the two do not match, the first comparison signal is output. When a level signal is output, and both match, a second level different from the first level thereafter until the gradation data reaches the time required to obtain the maximum density. Is provided, and a drive signal that changes based on the output time of the signal of the first level from the comparing means is output, and in the initial state, the comparing means outputs a specific initial comparison signal. In addition to the resetting, the clock signal is prevented from being input to the comparison signal, and the blocking state is released when the head is energized. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the basic concept of the present invention, and the basic structure of the head drive circuit will be described with reference to the timing chart shown in FIG. That is, the gradation data D1 to Dn for one dot is input to the serial input terminals SI1 to SIn and is shifted by the change of the shift clock pulse (CKS) level from "L (low)" to "H (high)". It is held in the registers DF / F1 to DF / Fn. The gradation data D1 to Dn held in the shift registers D-F / F1 to D-F / Fn are changed from the "L" level of the latch signal (LATCH) to the "H" level (in this case, LATCH
Is maintained at the "H" level) and latched by the latch circuits L1 to Ln, respectively. The gradation data D1 to Dn latched by the latch circuits L1 to Ln are continuously supplied to the EX-OR (exclusive OR) circuits a1 to an until the next gradation data is latched. In the initial state, that is, when the head (not shown) is not energized, the enable low power signal (ENLP), which is a time division drive signal, is at "H" level, the enable low delay signal (ENLDLY) is also at "H" level, and By setting the enable high signal (ENH) to “L” level,
The output terminal OUT of the driver 9 is kept at the "H" level.
That is, when ENLP is at "H" level and ENH is at "L" level, the output of the AND circuit 1 is at "L" level. Therefore, the output of the AND circuit 6 to which the output of the AND circuit 1 is supplied is at the “L” level. Also, ENLDLY is "H" level,
When ENH is at "L" level, the output of the AND circuit 2 is at "L" level. Therefore, the output of the AND circuit 3 to which the output of the AND circuit 2 is supplied is at the "L" level. Therefore, the output of the OR circuit 8 to which the output of the AND circuit 6 and the output of the AND circuit 3 are respectively set to the "L" level, and the output of the driver 9 is set to the "H" level. Further, inside the circuit, the "L" level as the output of the AND circuit 2 is the clear signal input terminal of the n-bit counter 10.
It will be supplied to the CL. Therefore, in the initial state, the outputs from the output terminals Q1 to Qn of the n-bit counter 10 are all at the "L" level. That is, the gradation data D1 to Dn are latched by the latch circuits L1 to Ln,
When supplied to the OR circuits a1 to an, since the outputs from the output terminals Q1 to Qn of the n-bit counter 10 are at the "L" level in the initial state, the gradation degree data D1 latched by the latch circuits L1 to Ln. EX-OR circuit a1 unless ~ Dn are all "L" level
The output of ~ an does not go to "L" level. Therefore, the output of the NAND circuit 5 is set to the "H" level and supplied to the AND circuits 3 and 4, respectively. The output of the AND circuit 4 is supplied as "L" level as the output of the AND circuit 2, and is always at "L" level. Therefore, the clock signal is not supplied to the clock input terminal row CK of the n-bit counter 10, and n
The outputs Q1 to Qn of the bit counter 10 are all stable at “L” level. On the other hand, the output of the NAND circuit 7 is stable at "H" level unless all the gradation data D1 to Dn latched by the latch circuits L1 to Ln are "L" level. When the gradation data D1 to Dn latched by the latch circuits L1 to Ln are all at the "L" level, the outputs of the EX-OR circuits a1 to an are all at the "L" level. The output becomes "L" level.
However, there is no change in the outputs of the AND circuits 3 and 4 to which the output of the NAND circuit 5 is supplied, and the outputs are stable at the "L" level. Further, the output of the NAND circuit 7 also becomes "L" level, but the output of the AND circuit 6 to which the output of the NAND circuit 7 is supplied does not change and is stable at "L" level. When the head is energized, a clock signal (CKDLY) having a period of T is supplied. Here, the cycle T of CKDLY is the time "t2 ⁿ -1" required to obtain the maximum density "D2 ⁿ -1" that the gradation data SI1 to SIn have when the gradation is "2 ⁿ -1". , The difference time "t ₂ ⁿ _-1 -t ₁ " from the time "t ₁ " required to obtain the density "D ₁ " that the gradation data D1 to Dn have when the gradation "1" is "1" divided by the 2 ⁿ -2, "" _{^{T = (t 2 n - 1}} -t 1) is a / (2 ⁿ -2) ". In this case, ENH is set to "H" level, and NELP is set to "L" level for the time "t ₁ -T". Then, the output of the AND circuit 1 is set to the "H" level for the time "t ₁ -T". In response to this, the AND circuit 6 outputs the OR circuit 8 during the time "t ₁ -T" if the output of the NAND circuit 7 is at "H" level.
"H" level is output to. As a result, the driver 9
During the time "t ₁ -T", the "L" level is output from the output terminal OUT. The output of the NAND circuit 7 for gradient data D1~Dn latched in the latch circuit L1~Ln is set to the "H" level unless all "L" level, always the time "t ₁ -T" Meanwhile, the driver 9 outputs the "L" level. This means that after the current has been energized for the time "t ₁ -T" for the gradation "1 to 2 ⁿ -1" of the gradation data D1 to Dn, the cycle T of CKDLY is energized by the data value. It is the previous pre-energization. Therefore, immediately after the end of this pre-energization, that is, when ENLP changes from “L” level to “H” level and ENLDLY changes from “H” level to “L” level, the time “t ₂ ⁿ
- outputs "L" level between ₁ -t ₁ + T ". The ENLDLY is supplied with a timing at which the CKDLY changes from the “H” level to the “L” level at any time when the CKDLY changes from the “H” level to the “L” level. In this case, when ENLDLY goes to "L" level, ENH is at "H" level, so the output of the AND circuit goes to "H" level. The output of the AND circuit 3 to which the output of the AND circuit 2 is supplied becomes the "H" level by the output of the NAND circuit 5 which is the "H" level in the initial state. For this reason, the output of the OR circuit 8 receives the output of the NAND circuit 5 and is set to the “H” level, so that the output of the driver 9 becomes the “L” level. The output of the AND circuit 2 is the n-bit counter 10
The clear signal input terminal CL is set to "H" level to release the clear state, and the input to the AND circuit 4 is set to "H" level. In this case, since the input of the AND circuit 4 to which the output from the NAND circuit 5 is supplied also becomes "H" level in the initial state, the output of the AND circuit 4 outputs the clock of CKDLY to the clock input terminal CK of the n-bit counter 10. Supply to. As a result, the n-bit counter 10 starts counting, and the outputs from the output terminals Q1 to Qn increase from the gradation level “0” to “2 ⁿ −1”. This output terminal Q1 ~
While the output from Qn does not have the same value as the gradation data D1 to Dn latched in the latch circuits L1 to Ln, the EX-OR circuits a1 to an
One or more of the outputs of the NAND circuit 5 are at the "H" level, and the output of the NAND circuit 5 is at the "H" level. When the count of the n-bit counter 10 advances and becomes the same value as the gradation data D1 to Dn latched by the latch circuits L1 to Ln, all the outputs of the EX-OR circuits a1 to an become "L" level. . As a result, the n-bit counter 10 stops counting and the output of the NAND circuit 5 maintains the "L" level.
When the NAND circuit 5 outputs the “L” level, the output of the AND circuit 3 becomes “L” and is supplied to the OR circuit 8. The output of the OR circuit 8 is determined by the output of the AND circuit 3 and the output of the AND circuit 6. However, currently, the output of the AND circuit 3 is "L" level, and the output of the AND circuit 6 is
ENLP is at "H" level. Therefore, by supplying the output of the AND circuit 1 to the AND circuit 6 as the "L" level, the output of the AND circuit 6 is at the "L" level. Therefore, the output of the OR circuit 8 becomes "L" level,
The output of the driver 9 changes from "L" level to "H" level. After that, ENLDLY changes from the “H” level to the “L” level, and after a time “T × (2 ⁿ −1)”, changes from the “L” level to the “H” level. This is the gradation data D1 to Dn
This is because it is not necessary to set ENLDLY to the “L” level any more when n has the value of n, and the output of the AND circuit 2 is forcibly set to the “L” level. As a result, the output of the AND circuit 3 is set to "L" level, the output of the OR circuit 8 is set to "L" level, and the output of the driver 9 is set to "H" level. That is, the output of the driver 9 is “t ₁ −T + T × gradation degree”, which is the sum of the time “t ₁ −T” when ENLP is at “L” level and the time “T × gradation degree data value”. It goes to "L" level only during the time corresponding to "data value". However, when the gradation data is "0", the inputs to the NAND circuit 7 are all at the "L" level, so the output of the NAND circuit 7 is at the "L" level and the output of the AND circuit 6 is the AND circuit. It is always at "L" level regardless of the output of 1. After the energization of one dot is completed, ENH is changed from the "H" level to the "L" level to return to the initial state in which the head is not energized. As can be seen from the timing chart of FIG. 2, the output terminal OUT changes when the gradation levels of the gradation level data D1 to Dn held in the latch circuits L1 to Ln change to "0 to ²ⁿ to 1".
The "L" level time output from is proportional to the value of the data except when the data is "0". That is, when the value of the gradient data D1 to Dn is "0", the energization time of the head is "0", and when the gradient data D1 to Dn is "1 to ^2n- 1", the time "t _1- ". After being energized for "T", the energization is further performed for the time obtained by multiplying the period T of CKDLY by the number of data. The relationship between the pulse width and the gradation data is similar to the "pulse width-recording density characteristic diagram" shown in FIG. 3, and the recording density corresponding to the gradation data can be obtained by changing the pulse width. You can 11 to 13 schematically show the structure of a thermal head (recording head) applied to a thermal ink jet printer, for example, as a recording apparatus of the present invention. That is, the thermal head 35 includes a metallic round bar 91 on which a large number of heating elements 50 are formed, an aluminum support member 93 that supports the round bar 91 and dissipates heat from the round bar 91, and the round bar 91. The thermistor 94 for detecting the temperature of the thermal head 35 and the supporting member 93.
The printed circuit board (hereinafter referred to as a PC board) 97 for mounting the driving integrated circuit (hereinafter, referred to as a driving IC) 95 of the heating element 50 and the printed circuit board 97 are mounted on the PC board 97. It is composed of a driving IC95. In addition, the driving IC
95 is covered with a protective layer 99 made of epoxy resin. Further, as shown in FIG. 13B, the round bar 91 is provided with a driving side electrode pattern 101 and a common side electrode pattern 103 of the heating element 50. Among the many heating elements 50 formed on the round bar 91, the driving side electrode pattern 101 of each effective heating element 50a is bonded to the corresponding output signal pad 105 of the driving IC 95 as shown in FIG. Connected by wires 109. Further, the common side electrode pattern 103 of the heating element 50 is
The common lead wires 104a and 104b are connected to the drive power source patterns 111a and 111b formed on both left and right sides of the head portion. Here, the driving IC 95 in this embodiment is provided with 32 output signal pads 105 and is time-divisionally driven in units of 32 bits. A total of 54 driving ICs 95 are used, and the number of effective heating elements 50a is 1728. Therefore, the effective heating element 50a is time-divisionally driven in units of 32 bits. Therefore, the common-side electrode pattern 10
The current flowing in 3 is usually much smaller than that of a commonly used thermal head, and it is possible to prevent problems caused by voltage drop, heat generation of electrodes, etc. 4 to 6 show the internal circuit of the thermal head 35. In FIG. 4, the effective heating element 50a is shown.
For all heating elements (H0 to H1727) of the drive power supply voltage (+24
V) Va is being supplied. Further, as described above, each effective heating element 50a is connected to each output terminal of the corresponding driving IC (IC1 to IC54). Gradation degree data D1 to Dn are supplied to the serial input terminals SI1 to SIn of the driving IC 54, and the serial input terminal of the next driving IC 53 is connected to the serial output terminal of the driving IC 54. Has been done. As described above, by connecting all the driving ICs (IC54 to IC1) in series, the gradation data D1 to Dn supplied to the driving IC 54 are sequentially shifted in the driving IC1 direction. ing. That is, the gradation data D1 to Dn input in synchronization with the shift clock pulse (CKS) is held in the shift registers D-F / F1 to D-F / Fn in the driving ICs 54 to IC1, and these levels are stored. The adjustment data D1 to Dn are latched in the respective latch circuits L1 to Ln of the driving ICs 54 to IC1 by the latch signal (LATCH) supplied when the input is completed. The gradation data D1 to Dn are
Enable high signal (ENH1 ~
7), enable low power signal (ENLP1 to 8), enable low delay signal (ENLDLY1 to 8), as shown in FIG. 5, supplied to one drive IC selected from drive ICs 54 to IC1. As a result, the effective heating element 50a is time-divisionally driven in 32-bit units. In FIG. 4, V _DD is a logic power source (+5 V) for the driving ICs 54 to IC1, 94 is a thermistor for temperature detection, and a and b are output terminals of the thermistor 94. FIG. 6 shows the driving IC 95, that is, the driving ICs 54 to IC1.
It shows the configuration of FIG. The gate input terminal ENHm to which the ENH is supplied and the gate input terminal EN to which the ENLP is supplied
LPn and the gate input terminal ENLDLY1 to which the ENLDLY is supplied are supplied with respective signals via an inverter or a buffer. In this case, each logic 0-31 has the circuit configuration shown in FIG. Next, the signal input timing for driving the thermal head will be described with reference to FIGS. 7 to 10 in which the head driving circuit has a circuit configuration for outputting gradation levels of 2 ³ steps. The head drive circuit in FIG. 7 is configured as 3 of n of the basic circuit of the head drive circuit shown in FIG. FIG. 8 shows that each gradation data SI1 to SI3 of 1728 dots is serially input from the serial input terminal of the driving IC 54, and each latch circuit L1 to L3 (1727 ₃ , 1727 ₂ , 172) in the driving IC 54 to IC1.
7 ₁ , 1726 ₃ , 1,726 ₂ , 1,726 ₁ , ..., 0 ₃ , 0 ₂ , 0 ₁ ) is a timing chart for latching. Driver IC54 to IC1
Gradation data SI1 to SI3 input to is synchronized with CKS to 1
It is held in the shift register DF / F of each driving IC with 728 pulses, and then the latch circuit L of each driving IC is held by LATCH.
Latched to 1 to L3. After the gradation data SI1 to SI3 of each dot is latched,
ENH1 to 7, ENLP1 to 8 and ENLDLY1 to 8 are input at the timing shown in FIG. 9 in order to perform time-division driving in units of 32 dots 1 IC. As a result, each driver IC54 to IC1
Time when NH is "H" level, ENLP is "L" level and ENH is "H"
"L" level according to the gradation data is output from each terminal OUT at the timing shown in Fig. 10 by the logic in each driving IC selected when the level and ENLDLY are at "L" level. . During this "L" level output, the drive power supply voltage Va is applied to the selected effective heating element 50a. The tenth
In the figure, as an example, the case where the gradation data is "5" is shown. Therefore, the "L" level is output from the terminal OUT between (0) and (5). (0) to (7) show the timing at which the “L” level output changes to the “H” level output with respect to the gradation data, and actually (0)
From the time point of to the time point indicated by the data of each gradation level, the “L” level is output from the terminal OUT. As described above, a head drive circuit that outputs 2 ⁿ gradation levels per dot by driving the recording head by dividing the drive time during black output by binary output for 1 dot is integrated. A circuit (IC) is mounted inside the head, and gradation recording is performed by driving the head only once for recording one dot. As a result, it is possible to perform gradation expression that satisfies both the characteristics of high resolution and multiple gradations, and further improve the efficiency of the device.
Therefore, it is possible to prevent the deterioration of the print quality and the occurrence of moire, blur, and unevenness, which are problems when expressing the gradation by utilizing the dither processing, and further, it is necessary when the circuit is provided outside the head. Since the space for installing the circuit can be reduced, the entire device can be downsized, and
It is possible to speed up recording by recording one dot by driving the head once. In the above embodiment, a case has been described applied to a thermal head of a thermal ink jet printer as an example, ze limited thereto, when the head exposure time as a parameter, the 2 ⁿ gradations per dot It can also be applied to LED printers, liquid crystal printers, etc. that can record in stages, and also to laser beam printers, etc. Besides, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. [Effects of the Invention] As described above in detail, according to the present invention, it is possible to avoid deterioration of print quality, etc., and it is possible to reduce the size of the entire apparatus and to increase the recording speed. Can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a basic configuration of a head drive circuit which is the basic concept of the present invention, FIG. 2 is a timing chart shown for explaining the basic configuration of a head drive circuit, and FIG. Is a characteristic diagram showing the relationship between the pulse width and the recording density, FIG. 4 is a diagram showing the internal circuit of the thermal head and the time-division drive signal supplied to this circuit, and FIG. 5 is the selection operation by the time-division drive signal. Fig. 6 shows the layout of the driving ICs for driving.
FIGS. 7 to 13 show an internal structure of the IC, and FIG. 7 shows an embodiment of the present invention. FIG. 7 shows an example of the structure of a head drive circuit, and FIG. 8 shows gradation data. Timing chart showing transmission timing, FIG. 9 is a timing chart showing operation timing of each driving IC for 1-dot line printing, FIG. 10 is a timing chart showing head driving timing for 1 dot, and FIG. 11 is a thermal head. Is a configuration diagram showing the thermal head from the back side, FIG. 12 is a configuration diagram showing the thermal head from the front face, and FIG. 13 is a configuration diagram showing the thermal head from the side face. 1,2,3,4,6 …… AND circuit, 5,7 …… Nand circuit, 8 ……
OR circuit, 9 ... driver, 10 ... n bit counter,
a1, a2, --- EX-OR circuit, L1, L2, ---... Latch circuit, D
-F / F1, D-F / F2, ... shift register, 35 thermal head, 50 heating element, 50a effective heating element, 95
...... Driving IC.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-60-237764 (JP, A)                 JP-A-62-179962 (JP, A)                 JP 58-166074 (JP, A)                 JP 62-116165 (JP, A)

Claims (1)

(57) [Claims] 1.1 In a recording apparatus for driving a recording head by mounting a head drive circuit corresponding to each dot as a component of the head, the head drive circuit is input, A shift register that holds gradation data represented by binary n bits corresponding to a dot by a change in a shift clock pulse, and a latch circuit that latches the gradation data held in this shift register in correspondence with a latch signal. , A counter for outputting a comparison signal represented by binary n bits, for updating and outputting the comparison signals in a specific order corresponding to a clock signal of a predetermined cycle, and the comparison output by the counter. The signal and the gradation data latched by the latch circuit are compared, and when the two do not match, a signal of the first level is output and both match. If, after that, until the gradation data reaches the time required to obtain the maximum density,
Comparing means for outputting a signal of a second level different from the first level; output means for outputting a drive signal that changes based on the output time of the signal of the first level from the comparing means; and an initial state In the above, the comparison means resets so as to output a specific initial comparison signal, prevents the clock signal from being input to the comparison signal, and cancels the prevention state when the head is energized. A recording device characterized by being provided.