JP2572156B2 - Driver IC for line print head - Google Patents

Description

The present invention relates to a line print head driver IC, and is particularly suitable for use as a driver IC for driving a line print head of a non-impact printer. .

<Prior Art> As is well known, a printer is provided with a driver IC, which supplies a drive signal from the driver IC to a write element to operate the write element, and a predetermined signal corresponding to a given data signal. The print information is printed on a print medium.

FIG. 3 shows a circuit configuration diagram of a conventional driver IC. This driver IC includes an n-bit shift register 41, an n-bit latch circuit 42, an AND gate circuit 43, a driver circuit 44, and the like. In the circuit of FIG. 3, the data signal supplied from the data input terminal T ₁ DATA is synchronized with the clock signal CLOCK input from the clock input terminal T _2,
continue to move through the n-bit shift register 41, when moved n bits outputted from the data output terminal T ₅ to the outside.
Then, data input to the n-bit shift register 41 is latched by the n-bit latch circuit 42 when the load signal LOAD is supplied from the load input terminal T _3.

The data latched by the n-bit latch circuit 42 is
Strobe signal STROBE and and supplied from the strobe input terminal T ₄ in the AND gate circuit 43 is taken. Thus, only when the strobe signal STROBE is ON, the output terminals OUT1, OUT2,.
Is turned on.

FIG. 4 is a circuit diagram showing an example in which a line print head of 1 × N × n bits is formed by using a driver IC performing such an operation. In FIG. 4, a data input terminal
Data signal DATA entering from T _1, the first driver IC 20 _-1
And moves in the n-bit shift register 41 to the left in the figure in synchronization with the clock signal CLOCK as shown by the arrow. Therefore, when n clocks are supplied, an n-bit shift register
Go to the end of 41, the (n + 1) output from the data output terminal in -th clock first driver IC 20 _-1, these pins at the data input terminal of the second driver IC 20 _-2 (Fig. 4 given by that) are omitted, one bit eyes of n-bit shift register 41 of the second driver IC 20 _-2.

The data signal DATA is moved in this manner, so that the Nth driver IC moves by N × n clocks.
This is the n-th bit of the 20- _N n-bit shift register 41. That is, data inputted from the data input terminal T ₁ of the first driver IC 20 _-1 is, n in order of input
Moving through the bit shift register 41, the first input data enters the n-th bit of the _N- th driver IC 20- _N at the N × n-th clock, and the next input data is the (n-1) enters the eye, the most recently entered data is the first bit enters the eyes of the first driver IC 20 _-1. That is, the data of the first dot input first enters the n-bit shift register 41 of the driver IC provided at a position separated from the signal input unit. When all the data for one line enters each shift register, the load signal LOAD is input, whereby the data for one line is latched by the n-bit latch circuit 42. Then, the strobe signal
When STROBE is input, the write element 45 is turned on according to the data for one line.

<Problems to be solved by the invention> Data signal DATA, clock signal CLOCK, load signal LOA
Signals such as D and the strobe signal STROBE are supplied from the control board to the signal input unit of the line print head, and supplied from the signal input unit of the line print head to the driver IC to the signal input unit. Generally, the data signal DATA is sent in order from the signal corresponding to the first dot.

By the way, the manner in which the print head and the control board are mounted on the printer 6 is roughly classified into two arrangement modes, as shown in FIG. That is,
5 (a), the control board 8 is arranged on the opposite side of the first dot, and as shown in FIG. 5 (b), the control board 8 is on the same side as the first dot. There are two types of arrangement.

Of these two arrangements, as shown in FIG.
When the control board 8 is arranged on the opposite side of the first dot,
As shown in FIG. 6A, the signal input section 9 can be provided on the opposite side of the first dot. Therefore, in this case, since the signal input section 9 of the line print head and the signal input section of the driver IC are close to each other,
Data signal DATA, clock signal CLOCK, load signal LOAD
Etc. can be shortened.

However, when the control substrate 8 is arranged on the same side as the first dot as shown in FIG. 5 (b), as shown in FIG. Since the input unit 9 cannot be provided on the opposite side of the first dot, the first
The signal input unit 9 must be provided on the same side as the dots. For this reason, the signal input section 9 of the line print head and the signal input section of the driver IC become far from each other, so that the data signal DATA, the clock signal CLOCK, and the load signal L
When wiring signal lines for transmitting OAD or the like, each signal line must be wired as long as the length of one line.

Therefore, in this case, the following inconvenience occurs. In other words, the print head becomes larger due to the increase in the substrate area corresponding to the increase in the wiring length, and the cost increases accordingly. In addition, when the signal line is long, the signal line is susceptible to noise from external electromagnetic waves and the risk of malfunction is increased. Furthermore, if the signal line is lengthened, it acts as an antenna, so that electromagnetic wave noise is easily radiated to the outside. In particular, since a clock signal usually uses a high frequency, there is a problem that electromagnetic waves are easily radiated to the outside. In addition, when the dot density of printing increases, the printing width increases, or the printing speed increases, the frequency of the clock signal further increases, and the noise increases accordingly.

Radiation of electromagnetic wave noise may cause other electronic devices to malfunction, so it has been particularly required to prevent radiation of electromagnetic waves. In addition, recently, various standards for regulating the magnitude of noise have been created, and if the above-mentioned standards are not satisfied, it will become difficult to sell printers.

SUMMARY OF THE INVENTION In view of the above-described problems, an object of the present invention is to make it possible to shorten a signal line in a line print head when a signal input terminal of the line print head must be provided on the same side as the first dot. .

<Means for Solving the Problems> A driver IC for a line print head according to the present invention converts a data signal supplied to one end from a signal input section of the line print head into another end in synchronization with a clock signal. Side, and an n-bit shift register that outputs these data in parallel when a load signal is input, and a data signal output from the n-bit shift register is fetched and held at its output terminal. The logical AND of an n-bit latch circuit, the n-bit, the latch circuit, and the strobe signal given from the signal input unit of the line print head, and the data signal of the next stage is supplied during the period when the strobe signal is given. AND to output to circuit
An n-bit circuit generally configured by a gate circuit and a driver circuit for driving a writing element based on the data signal given from the AND gate circuit and printing print information according to the data signal on a print medium An n-ary counter for counting a clock signal supplied from a signal input unit of the line print head to the data control drive unit and resetting the count value by the load signal; and a count-up signal output from the n-ary counter. A first switching circuit that sends the data signal to the n-bit data control driver or the data output terminal of the driver IC according to
The switching operation is performed in response to the count-up signal output from the n-ary counter in the same manner as the switching circuit of the above, and the clock signal is sent to the n-bit shift data control driver and the n-ary counter, or
A second switching circuit for sending to the clock output terminal of the IC is added.

<Operation> The clock signal supplied from the signal input unit of the line print head is counted by an n-ary counter, and when a predetermined number is counted, a count-up signal is output to the first and second switching circuits, thereby being input. A data signal is sent to the n-bit data control driver or a data output terminal, and the clock signal is selectively supplied to the n-bit data control driver and the n-ary counter or the clock output terminal of the driver IC. This enables each driver IC to input a data signal at a position far from the signal input terminal and to shift the data signal closer to the signal input terminal. This makes it possible to put the input data signal in a position near the output input terminal in the order of input over the entire line print head.

Embodiment FIG. 1 is a circuit configuration diagram of a driver IC showing one embodiment of the present invention.

As is clear from FIG. 1, the driver IC 10 of the embodiment is
Is a data control drive unit 11 including an n-bit shift register 1, an n-bit latch circuit 2, an AND gate circuit 3, and a driver circuit 4, an n-ary counter 12, a first switching circuit 13, and a second switching circuit 14. And the like.

The n-bit shift register 1 of the embodiment has a data shift characteristic opposite to that of the conventional shift register shown in FIG. 3, and shifts data from the left side to the right side as shown by the arrow in FIG. .

The n-ary counter 12 is configured to output a count-up signal 12a each time n clock signals CLOCK are counted, and to be reset by a load signal LOAD.

The first switching circuit 13 has its switching terminal connected to the data input terminal T ₁ , and performs an operation of switching the switching terminal according to a count-up signal 12 a output from the n-ary counter 12. As a result, when the switching terminal is switched to the fixed terminal a, the data signal DATA is sent to the n-bit shift register 1, and when the switching terminal is switched to the fixed terminal b, the data signal DATA is output to the data output terminal. It is sent to the terminal T ₅ side.

The clock in which the second switching circuit 14 performs an operation of switching the switching terminal in response to the first count up signal 12a outputted from the switching circuit 13 and also n-ary counter 12 is applied to the clock input terminal T ₂ the signal cLOCK, and supplies the n-bit shift register 1 side by switching the switching terminal to the fixed terminal c side, and supplies the clock output terminal T ₆ by switching to the fixed terminal d side.

In the driver IC 10 of the embodiment configured as described above, in the first reset state, the first switching circuit 13
Is switched to the fixed terminal a side,
Data signal DATA supplied from the data input terminal T ₁ is sent to the n-bit shift register 1. The second switching circuit 14 at this time, have been switched to the fixed terminal c side, the clock signal CLOCK that is supplied from the clock input terminal T ₂ are sent to the n-bit shift register 1 and n-ary counter 12. Therefore, in the initial state, the data signal DATA input in synchronization with the clock signal CLOCK is
Are sent to the n-bit shift register 1 and are sequentially shifted from a side far from the data input terminal to a side closer thereto.

The n-ary counter 12 counts the input clock signal CLOCK. Then, when counting for n clocks, that is, when n-bit data is input to the n-bit shift register 1, the count-up signal 12a is output to the first and second switching circuits. This allows
In the first switching circuit 13, the switching terminal is switched to the fixed terminal b side, and the data signal DATA is applied to the data output terminal.
It is sent to the T _5. In the second switching circuit 14, switching terminal is switched to the fixed terminal d side, a clock signal CLOCK is sent to the clock output terminal T _6. As a result, the n-bit shift register 1 stops shifting data, and the n-ary counter 12 outputs the clock signal CL.
Stop counting OCK. In this state, when the load signal LOAD is input, the data stored in the n-bit shift register 1 is latched by the n-bit latch circuit 2. At the same time, the n-ary counter 12 is reset, the switching terminal of the first switching circuit 13 is switched to the fixed terminal a, and the switching terminal of the second switching circuit 14 is switched to the fixed terminal c.

FIG. 2 is a configuration diagram showing an example in which a line print head is configured using N driver ICs 10 according to the embodiment configured as described above.

First, in the reset state, the first driver IC 10 _-1 .
In all of the Nth driver ICs 10- _N , the n-ary counter 12
Has been reset. Also, a first switching circuit
The switching terminal 13 is switched to the fixed terminal a side, and the second
The switching terminal of the switching circuit 14 is switched to the fixed terminal c side.

In this state, when the data signal DATA synchronized with the clock signal CLOCK is supplied to the line print head, the first
The n-bit shift register 1 of the driver IC 10 _-1, it contains the data signals DATA from the farther to the input terminal, which is successively shifted to closer to synchronization with the input terminal to the clock signal CLOCK. Further, n-ary counter 12 of the first driver IC 10 _-1 starts counting at the same time. When the n-bit data is sent as described above, the n-ary counter 12 outputs the first and second switching circuits 13, 1
The count-up signal 12a is output toward 4. Thus, the first switching circuit 13, the switching terminal is switched to the fixed terminal b, the data signal DATA is transmitted to the data output terminal T _5. Also, the second switching circuit 14
In the switching terminal is switched to the fixed terminal d side, a clock signal CLOCK is sent to the clock output terminal T _6. Thus, the n-bit shift register 1 stops shifting data, and the n-ary counter 12 stops counting the clock signal CLOCK. The first to the n-bit shift register 1 of the driver IC 10 _-1 point, enters toward the first dot of data sent to the first is closest to the input terminal, the n sent to the n-th The dot is in the farthest.

Next, the data of the (n + 1) th dot is input to the data input terminal.
Given from T _1, in the first driver IC 10 _-1, since the first switching circuit 13 is switched terminal is switched to the fixed terminal b side, the data signal DATA and the second
It sent towards the driver IC 10 _-2. Also, switching terminal the second switching circuit 14 so that switched to the fixed end view d side, a clock signal CLOCK is also sent towards the second driver IC 10 _-2 as well.

The second driver IC 10 _-2 has been using the clock signal CL until then.
Since OCK is not input in the time of the (n + 1) th dot data is sent from the preceding driver IC 10 _-1 remains in the reset state. Therefore, the second
The first Suichinngu circuit 13 in the driver IC 10 _-2 in conjunction are switched to the fixed terminal a, a second switching circuit 14 is switched to the fixed terminal c side. Therefore, the data of the (n + 1) -th dot enters the portion farthest from the data input terminal and shifts toward the data input terminal. At this time, the n-ary counter 12 starts counting the clock signal CLOCK. Then, when the 2n-th dot data is sent, the same operations as those of the first driver IC 10 _-1 which is also described above in the second driver IC 10 _-2 is performed, the first switching circuit 13 is switched terminal fixing Switching to the terminal b side, the switching terminal of the second switching circuit 14 switches to the fixed terminal d side.
At this point, the (n + 1) th dot data is located closest to the input terminal, and the 2nth dot data is located farthest from the input terminal.

Next, when the data of the (2n + 1) th dot is sent,
This is sent to the third driver IC, and the same operation is repeated in each driver IC 10 thereafter. And nx
When the data of the N-th dot is sent, n of each driver IC 10
Data is input to the bit shift register 1 in the order from the data input terminal. When the load signal LOAD is input, the data of each n-bit shift register 1 in each driver IC 10 is latched by the n-bit latch circuit 2. At this point, the n-ary counter 12 of each driver IC 10 is reset, and the data signal DA of the next line is reset.
It becomes possible to start sending TA.

The data latched by the n-bit latch circuit 2 is supplied to the driver circuit 4 through the AND gate circuit 3 when the strobe signal STROBE is input. As a result, the driver circuit 4 outputs the write element 5 based on the given data.
And printing is performed based on the input data.
At this time, the writing element 5 is driven according to the data of the first dot, the second dot,...

<Effects of the Invention> As described above, the present invention counts a clock signal supplied from a signal input unit of a line print head by an n-ary counter, and counts up a count-up signal when a predetermined number is counted. It outputs the data signal to the circuit and sends it to the 6-bit shift register for holding the input data, or sends it to the data output terminal for outputting the data to the driver IC connected to the next stage. Sending the clock signal to the n-bit shift register and the n-ary counter, or sending the clock signal to a driver IC clock output terminal to input a data signal at a position far from the signal input terminal;
This can be shifted in each driver IC so as to be shifted closer to the signal input terminal, so that the input data signal is put in a position near the output input terminal in the order of input over the entire line print head. be able to. Therefore, when the signal input terminal of the line print head must be provided on the same side as the first dot, the signal line in the line print head can be shortened and the substrate area can be reduced, so that a compact and inexpensive line can be provided. A print head can be provided. Further, since each signal line can be shortened, it is possible to reduce the influence of electromagnetic wave noise from the outside, and to greatly reduce the amount of electromagnetic wave noise radiated to the outside.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a driver IC showing one embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an example of a line print head using the driver IC of the present invention, and FIG. FIG. 4 is a circuit configuration diagram showing an example of a line print head using a conventional driver IC, and FIG. 5 is a diagram for explaining an arrangement state of a control board. FIG. 5 (a) is a diagram showing a case where a control substrate is on the opposite side of the first dot, FIG. 5 (b) is a diagram showing a case where a control substrate is on the same side as the first dot, and FIG. FIG. 6A is a diagram showing the configuration of a line print head. FIG. 6A is a diagram showing a case where the first dot and the signal input unit are on the opposite side, and FIG. It is a figure showing the case where an input part is on the same side. 1 ... n-bit shift register, 2 ... n-bit latch circuit, 3 ... AND gate circuit, 4 ... driver circuit, 5 ... writing element, 7 ... line print head, 10 ... driver IC, 11 ... ... Data control driver, 12... N-ary counter, 13... First switching circuit, 14.

Claims (1)

(57) [Claims] A data signal supplied from a signal input section of a line print head to one end side is shifted to the other end side in synchronization with a clock signal, and a load signal is inputted. Driving a write element based on a circuit holding these data and the data signal,
A data control drive unit configured by a driver circuit that prints print information according to the data signal on a print medium; counts a clock signal provided from a signal input unit of the line print head; A counter that is reset by a signal, and sends the data signal to the data control driver in response to a count-up signal output from the counter,
Alternatively, a first switching circuit that sends the clock signal to the data output terminal of the driver IC, and performs a switching operation in response to a count-up signal output from the counter similarly to the first switching circuit, and converts the clock signal to data. A driver IC for a line print head, comprising: a control drive unit; and a second switching circuit that sends the signal to the counter or the clock output terminal of the driver IC.