JP2692813B2 - Scan circuit conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a method for automatically converting a digital logic circuit including a plurality of gates and storage elements into a digital logic circuit which can be easily tested. (Prior Art) In order to improve the testability of a large-scale logic circuit, a pre-scannable F / F or latch is used instead of a normal flip-flop (hereinafter referred to as F / F) or latch. A scan design method is used in which F / Fs and latches are connected by a scan path, and a sequential circuit can be divided into a shift register array including the F / Fs and latches and a combination circuit. (The scan-in / out circuit configuration is, for example, Japanese Patent Publication No. 57-3107.) However, there are rules that the logic circuit designer must keep in performing the scan design, and the logic design itself. Are severely restricted. For example, the following scan design rules exist when a master / slave type is used for the scanning F / F. There should be no loop circuit consisting only of gates other than storage elements (F / F and latches) in the logic circuit. The system clock applied to the scan F / F is
It must be possible to turn it on and off from outside the entire circuit. Do not take AND gates between system locks. (The clock must not be generated inside the entire circuit.) Asynchronous clocks, clears, and preset signals are not allowed. Therefore, if the above rules are observed, the time required for logic design increases. In addition, it takes a lot of labor to manually convert a large-scale logic circuit that does not follow such rules into a scannable logic circuit, and human error may occur. On the other hand, recently, for example, as can be seen in "One Method of Automation of Design for Easy Inspection" of Information Processing Society of Japan, Proceedings of the 31st National Convention P.1661, a normal logic circuit can be automatically tested easily. There is also a way to convert to. This method consists of creating scan information and adding the scan function. The addition of the scan function is (1) F /
Mechanical replacement of F with F / F with scan function, (2) generation of peripheral circuits for external scan pins, and (3) addition of scan circuits such as scan address decoder. However, with respect to a logic circuit that is hierarchically designed, scan circuit conversion is not performed by making use of the hierarchy. On the other hand, a system for supporting the design work of a logic circuit to which a test facilitation circuit is added is disclosed in JP-A-60-27985.
However, the addition of the circuit is performed through the pattern information of the circuit diagram and not through the object format created by compiling the logic circuit connection language. (Problems to be Solved by the Invention) In the above-described conventional technology, it is necessary for a logic designer to perform a logic design in advance in compliance with a scan design rule, and the scan design rule lowers the degree of freedom of the logic design. There is an adverse effect that it takes extra time to design a logic circuit. Further, as the number of F / Fs in the logic circuit increases, there is also a disadvantage that an additional circuit such as a large address decoder circuit used in the address scan method becomes large in scale. An object of the present invention is to provide a method for converting a non-scanning circuit into a circuit that can be automatically scanned with a minimum addition of circuits in order to eliminate the above-mentioned problems. [Structure of the Invention] (Means for Solving Problems) A database for hierarchically managing and storing object format data in which logical connection descriptions are compiled and logically designed hierarchically in module units, and a scan The conversion circuit conversion information storage unit, the scan design rule violation information storage unit, and the scan conversion circuit automatic conversion unit, and the scan conversion circuit automatic conversion unit violates the scan conversion circuit automatic conversion information and the scan design rule. The module information of the logic circuit being read is read, and the hierarchical module name, the lower module type name and the module identification name in the hierarchical module are read from the database, and whether the hierarchical module name is the scan target circuit conversion module or not. If it is, read only the data of the corresponding module from the database. However, it performs a scan of,
It is a feature of the present invention that the data of the module after the scan circuit conversion can be written in the database again. (Operation) Since the result of compiling the logical connection description that is hierarchically designed logically is stored in the database hierarchically, it can be easily extracted as an object format for each hierarchy and is suitable for automatic conversion of scan circuits. An information table is created, and data is inserted and replaced on the information table to perform automatic conversion, which enables high-speed processing. Furthermore, after the scan circuit automatic conversion is performed, only the data of the module that has undergone the scan circuit automatic conversion is written in the database, so that another system (for example, a layout logic simulator, a test generation system) can be connected via the database. Interface is possible. (Embodiment) FIG. 1 shows a diagram for explaining the configuration of the present invention. 101
Is a language that describes the connection relationship of logic circuits and is described hierarchically in module units so that logic circuits can be designed top-down or bottom-up. Reference numeral 102 is a compiler of the language description, and 103 is a database in which information on logical connection is stored. Reference numeral 104 is a cell library database that stores information on cells that are constituent elements of the logical connection description 101. Reference numeral 105 denotes a linker that links the logical connection information database (103) and the cell library database (104) and expands the hierarchically set data, and 106 is a database that stores the data after the hierarchical expansion. 107 is a scan design rule check system, 108 is a logic simulator, 109 is a test generation system, 110 is a layout system, and hierarchical development information data is input. Reference numeral 120 is a portion showing the configuration of the present invention, 121 is scan circuit conversion information, 122 is a scan circuit automatic conversion system, 123 is a scan circuit conversion command that can be specified by the user, and 124 is a scan design rule. Violation information. The scan design rule violation information is output from the scan design rule check system 107. The arrows indicate the flow of data, and the logical connection information database (10
The bidirectional arrow marked between 3) and the scan circuit automatic conversion system (122) indicates that the scan circuit automatic conversion system reads necessary information from the logical connection information database and performs the scan circuit automatic conversion. , Indicates that writing to the logical connection information database is possible again. By being writable in the above-mentioned database, there is a feature that logic simulation, test generation, and layout can be performed by using circuit information after automatic conversion of the scanning circuit. Further, since the system is closed via the scan design rule check system (107), it is possible to check the result of the scan circuit automatic conversion again. FIG. 2 shows a processing flow of the automatic conversion of the scanning circuit shown by 120 in FIG. 201 and 211 are terminals, 202 to 20
5, and 208 to 210 indicate processing, and 206 and 207 indicate judgment.
First, the process is started (201). The scan circuit conversion command specified by the user is read (202). This information is specified by the user and has priority over the scan circuit conversion information that has already been ruled. What kind of scan F / F is used to replace the normal F / F, and in what order the scan paths between modules are connected. And what type of module name (type name of external or internal buffer etc. of scan clock) to be inserted into which module. Next, scan conversion circuit conversion information is read (203). Here, like the user-specified scan circuit conversion information, the type name of the F / F to be replaced, the scan path connection order, the scan-related data, the clock, the type of the external input / output buffer such as the mode signal, etc. The name and the information for converting into a scannable circuit corresponding to the type of scan design rule violation are read. Then, the scan design rule violation information is read (20
Four). Details will be described later. Next, the module name, lower module type name, and module identification name are read from the logical connection information database (205). It is determined whether all module names have been read from the logical connection information database (206), and if they have been read, the process proceeds to 209. Otherwise, the read data above is the user-specified scan circuit conversion command information, scan circuit conversion information, or the module name, module type name, or module identification name stored in the scan design rule violation information. It is determined whether it is equal to (207). If no, the process returns to 205. If they are the same, the corresponding module attaches a tag for identifying whether or not scan conversion circuit conversion is necessary. After completion, return to 205. At 209, the tag reads the connection information of the module requiring the scan circuit conversion from the database, creates the conversion table, and performs the conversion. (209).
After the conversion, the data is output to the work file, and after the conversion is completed, the logical connection information database is rewritten (210). With that, all the processes are completed (211). The scan design rule violation information and the circuit conversion information corresponding to the type of scan design rule violation in the scan circuit conversion information will be described with reference to FIG. FIG. 3A is a first example of scan design rule violation, where FF is a normal F / F module type name, and ID1 and ID2 are module identification names. To the system clock input terminal C of 302,
When the uncontrollable signal IS is input to the '0' and '1' from the outside of the whole circuit, the input signal IS of the module identification name ID2
Violates the scan design rules. As another example of the scan design rule violation, as shown in FIG. 3C, a preset signal IS1 asynchronous with the input terminal PS of 305 is used.
And the asynchronous clear signal IS2 of the input terminal CR is input, the input signals IS1 and IS2 of the module identification name ID1
Violates the rule. Such scan design rule violation information stores a module identification name, a signal name, and a violation type. On the other hand, as the scan circuit conversion information, for the violation example of FIG. 3A, the system clock input of the scan F / F (304) is set as shown in FIG. 3B. A module type name AD2 having an AND function that enables OFF at 0'is inserted so that the gate can be taken with the test mode signal TM. For the violation of FIG. 3 (c), a module (307, 308) of the type name ND2 having the function of NAND is inserted, and each scan mode signal SM
And specify to take the gate. FIG. 4 shows an overall view of the conversion table created to perform the scan circuit automatic conversion. 401 is a module for reading the logical connection information database and then identifying the module name in the scan circuit conversion command specified by the user, the module name in the scan circuit conversion information, or the module in the scan design rule violation information. It is the converted module name and tag that match after identification and comparison with the identification name (the module type name is also required to indicate the module identification name in the hierarchically designed logic circuit).
402 is a table of the lower module type name used in the module 401 and the tag of scan circuit conversion,
Reference numeral 3 is a table showing the identification name and the type name added to each of the lower modules. A table 403 stores point information indicating what kind of signal name the input terminal and output terminal of the lower module are connected to.
Has been pointed to by. A pointing destination 405 of the table 404 is a table having a signal name, an input / output section for identifying any of an input, an output, and an internal signal in the module 401 of the signal name, and link pointer information. Reference numeral 406 is a link information table showing which terminal of which module each signal is connected to,
Pointing to tables 403 and 404. The table 406 is pointed by the link pointer of the table 405. Next, the scan conversion circuit automatic conversion will be described taking a specific circuit as an example. FIG. 5 is a hierarchical connection diagram of a logic circuit having the function of a 4-bit serial adder. FIG. 5 (a) is a diagram before the conversion into the scanning circuit, and FIG. 5 (b) is a diagram after the conversion into the scanning circuit. The box 501 indicates the entire hierarchy, and the module name is A. Lower modules 502 to 506 exist in 501, module identification names are ID1 to ID5, and module type names are B, B, C, FF, and E in order. 502 and 503 (module name B) are 4-bit shift registers, 504 (module name C) is a full adder and 505 (module name FF) is a D type F / F, 506
(Module name E) is a 5-bit shift register. Input signals of the module A is IN _1, IN ₂ and ICK, IN ₁ 502
And ICK are input, and IN ₂ and ICK are input to 503. Also signal ICK
Has also entered 505,506. On the other hand, the output signal IS _{1 of} 502, the output signal IS _{2 of} 503, and the output signal IS _{3 of} 505 are input to 504. The output signal IS ₄ of 504 is input to 506 and IS ₅
Is typing in 505. The output signals of the whole module 501 are composed of the output signals of 506 and are OT ₁ to OT ₅ . FIG. 5 (b) is a hierarchical connection diagram having the same function as FIG. 5 (a) and after the automatic scan conversion. Signals equivalent to those in FIG. 5A are given the same signal names. Similarly, regarding the module name, the module name of 511 is A, and the remaining lower module names and module identification names are also the same as the names before the scan conversion. (However, FF of 505 is replaced with SFF). 512 and 513 (module name B) are 4-bit shift registers composed of scanning F / Fs, and 516 (module name E) is also composed of scanning F / Fs. Further, since 515 is the circuit-to-be-scanned conversion module, the module name is replaced with FF from SFF.
Dotted lines ISCK ₁ and ISCK ₂ are scan clock signals and supply clocks to the modules (512, 513, 515, 516) in which the scanning F / F exists. The alternate long and short dash line is the scan path, SI
_{N 1, SIS 1, SIS 2} , SIS 3, are connected in the order of SOT _1. FIG. 6 shows a 4-bit shift register. FIG. 6 (a) shows 502 in FIG. 5 (a) and FIG. 6 (b) shows 5 in FIG. 5 (b).
Equal to 12. FIG. 6 (a) is a diagram before the scan conversion circuit automatic conversion, and FIG. 6 (b) is a diagram after the scan conversion circuit conversion. Reference numerals 602 to 605 are D-type F / Fs, module names are FF, and module identification names are ID _{1 to} ID ₄ in order. The input signals of 601 (module name B) are IN ₁ and ICK, the output signals are OT ₁ , and the internal signals are IS _{1 to} IS ₃ . 612 to 615 have a scanning D-type F / F module name of SFF and a module identification name of FIG. 6 (a).
Equal to that of Signal names equivalent to those in FIG. 6 (a) are directly attached to FIG. 6 (b). However, scan clocks ISCK ₃ and ISCK ₄ are supplied to each SFF, and buffers 616 and 617 for enhancing the drive capability of the scan clocks are inserted. The module type names for the 616 and 617 buffers are
In B1, the module identifiers are ID ₅ and ID ₆ , respectively. Again 61
The input signals for 6 and 617 are ISCK ₁ and ISCK ₂ . On the other hand, in the scan path, SIN ₁ is an input signal of the module B, SOT ₁ is an output signal, and they are sequentially connected to SIN ₁ , SIS ₁ , SIS ₂ , SIS ₃ , and SOT ₁ . Finally, the means for automatic conversion of the scan circuit is shown in FIGS.
A description will be given using the logic circuit in the figure. First, the user selects the scan clock internal buffer in the module type name B.
B1 and (input signal name ISCK ₁ ) are also described in the scan circuit conversion command to insert the buffer name B1 (input signal name ISCK ₂ ). Also, information indicating the type of insertion indicating that this is the insertion of the buffer of the first phase clock of the scan clock and the buffer of the second phase clock is also described. On the other hand, as scan conversion circuit conversion information, first, as replacement information of F / F, the module type name FF is replaced with SFF, and the scan path connection order is the logic of the scan target circuit conversion module. It is a sequence in the connection description. Further, since the circuits taken as examples are not in a chip level hierarchy, description of scan-related data and clock mode signal input / output buffers will be omitted. Further, the scan design rule violation information is also omitted. As already described with reference to FIG. 2, after reading the user-specified scan circuit conversion command and scan circuit conversion information, the module name, lower module type name, and module identification name are read from the logical connection information database. Read. Now, it is assumed that the logical connection information database stores the connection information in the module in the order of B, C, E, A for each module. Then, first read the module name B, then read the lower module type name FF,
Module ID names ID _{1 to} ID ₄ are also read. Since we have not read all the module names yet, these are the module names in the scan circuit conversion information specified by the user,
It is determined whether the module name is in the scan circuit conversion information. As described above, since "B" is designated as the user-specified scan circuit conversion module name, it is regarded as the scan target circuit conversion module name. Similarly, since "FF" is specified as the replacement target F / F name as the scan conversion circuit conversion information, it is considered to be the scan conversion circuit conversion module name even in this case, and the tag of the scan conversion circuit conversion is included in the tag. It has an identifier. Next, the module name C is read, and there is no FF in the lower module type name in C (the explanation of the lower module connection relationship in C is omitted). Since the name does not match, the tag has an identifier indicating that no conversion is performed. Although the module E will not be described in detail, it is regarded as a scan target circuit conversion module because FF exists in the lower module type name. These module names and tags to be scanned circuit conversion are stored in the main storage device, and are used when determining whether or not a scanned circuit conversion module is selected when the upper module is read from the logical connection information database. Finally, the module name A is read, and it is determined whether the lower module type name is the scanned circuit conversion module name or not based on the scan circuit conversion information and the module name and tag information. In this case, the lower module type name is B, C, FF, E, so FF corresponds as the F / F name to be replaced, and B, E from the above tag information,
It is determined that the module A is the scan target circuit conversion module. Since the module information is not necessarily stored in the logical connection information database in the order of B, C, E, A, the sequential module name and the lower module type name are re-created in the process (209) of FIG. reading,
If the lower module type name is the above-mentioned scanned circuit conversion module name, it is determined using a tag. If the scanned circuit conversion module name is the scanned circuit conversion module name, all the connection relation data in the module are obtained from the above database. read out. Of course, when the module name is read out, if the tag determines that the module name is the scanned circuit conversion module name, the lower module type name is further read to determine whether or not the scanned circuit conversion module name. Needless to say. Next, using the work table of FIG. 4, the procedure of scan circuit conversion of the circuit of FIG. 6 will be described. The module name of 401 is B, and the tag for scan conversion circuit conversion indicates that it is a scan conversion circuit conversion module. Also, 402
The lower module type name of FF is FF, indicating that the tag for scan circuit conversion is also the scan target circuit conversion module. The lower module identification names of 403 are ID _{1 to} ID ₄ , and the module type name corresponding to the module identification name is FF. The table 405 contains signal names in the order of OT ₁ , IN ₁ , ICK, IS ₁ , IS ₂ , IS ₃ , and the input / output classification is output, input,
Contains code numbers that mean input, internal, internal, internal. In addition, the module identification name ID 403 of the table 404
_As it is pointed to ₁ , the numbers 4, 2 and 3 are entered in order, and the address of the signal name of 405 is pointed. The link information of 406, which the link pointer of the signal name IN ₁ of 405 points to, points to the lower module identification name ID ₁ and also the lower module terminal number 2 (the address of the table of 404 is the second). ing. Conversion in the table is done in the next step. First, the lower module type name in the table 402 is replaced with FF from SFF. Second, the lower module type name FF in the table 403 is replaced. The number of simultaneous F / Fs is counted, and since there are four in this case, five signal names of the scan path are generated. Third
, The scan clock signal name is generated, but in the present case,
Since the input signal name of the scan two-phase clock buffer is specified in the scan circuit conversion command specified by the user, the output signal name of the buffer is generated. Fourth, in the signal name table 405, SIN ₁ , SIS ₁ , SIS ₂ , SIS ₃ , SOT
₁ scan path signal name and ISCK ₁ ,, ISCK ₂ ,, ISCK ₃ ,, ISCK ₄
Insert the signal names for the four scan clocks.
At this time, input / output classification and link pointer information are also created. Also, the link information of 406 is created. And the fifth
The lower module terminal number and the pointing information of the tables 403 to 404 are updated. Finally, the tag for scan circuit conversion is cleared, and the scan circuit automatic conversion for module B ends. Similarly, automatic conversion of the scan circuit can be performed for modules E and A. By performing the processing as described above, the scan circuit automatic conversion can be performed even for the chip level circuit, and the logic circuit insertion when the scan design rule is violated can also be converted into the scan circuit. Further, when there are a plurality of scan paths, the scan path identifier information is stored in the scan conversion circuit conversion information, and the scan path identifier is assigned to the module to be scanned circuit conversion in the scan conversion circuit conversion processing. A plurality of scan paths can be generated by the above-mentioned method by adding an identifier to the scan path signal name between lower modules. As described above, according to the present embodiment, FIG.
As explained using the figure, only the connection data of the modules that need scan conversion circuit conversion is read from the logical connection information database, high-speed processing is possible, and non-scan circuits can be easily scanned. Can be converted into a digital circuit. [Effects of the Invention] As described above, according to the present invention, a hierarchically designed logic circuit incapable of scan operation can be converted into a scan circuit with a minimum number of additional circuits in each hierarchical module. , The converted circuit information is written in the database storing the logical connection information, and the interface with other logic simulator test generation system and layout system can be easily taken. Further, when the scan design rule check system is interfaced with the above database, it is possible to recheck the circuit after the automatic conversion of the scanning circuit via the scan design rule violation information.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a relation between an automatic scanning circuit conversion system according to an embodiment of the present invention and another system, and FIG. 2 is a scanning circuit conversion according to an embodiment of the present invention. FIG. 3 is a process flow diagram, FIG. 3 is an explanatory diagram of scan design rule violation information, FIG. 4 is a diagram showing a conversion table created when performing scan circuit conversion processing, and FIG. 5 is an embodiment of the present invention. A logic circuit connection diagram and FIG. 6 are logic circuit connection diagrams of the lower hierarchy of FIG. 101 ... Logical connection description, 102 ... Compiler, 103 ... Logical connection information database, 122 ... Scanned circuit automatic conversion system.

Claims (1)

(57) [Claims] A method for automatically converting a non-scanned logic circuit, which is hierarchically designed top-down or bottom-up, into a scan testable logic circuit, and a logic in which a compilation result of a connection description of the non-scanned logic circuit is stored. A step of reading the module type, the lower layer module name, and the lower layer module identification name assigned to each layer before expanding the layer from the connection information database and determining whether or not to perform the scan circuit conversion And a step of determining whether or not the module name to be scanned circuit conversion is used in another layer, a step of reading only the connection information in the module to be scanned circuit conversion, and a layer Steps to perform scan circuit conversion for each hierarchical module before expansion, and after scan circuit conversion It characterized by having a step of writing the module information in the logical connection information database, scanning circuit conversion method.