JPS6027985A - Designing device of logical circuit - Google Patents

Abstract

PURPOSE:To support the designing operation of a logical circuit added to a test facilitating circuit by adding an automatic adding mechanism for the test facilitating circuit to the logical circuit designing device. CONSTITUTION:Various basic patterns are stored as fixed data in a data controller 4, and read out successively under the control of an operation processor 3. Then a finding mechanism 6 for a test facilitating circuit additional part retrieves whether a circuit pattern corresponding to a basic pattern is found in an input circuit diagram or not. When it is not found, the processing for the basic pattern is ended and the processing for a next basic pattern is started. When found, a test system deciding and selecting mechanism 7 selects one of stored test systems as to the corresponding pattern, and the test facilitating circuit adding mechanism adds the test facilitating circuit corresponding to the circuit pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a 1:1 improvement to a logic circuit design device for supporting the design of logic circuits.

It is equipped with an input device for inputting all circuit information, an output device for displaying and printing circuit diagrams, an arithmetic processing device for data processing, and a data management device for accumulating logic circuit information. Logic circuit design devices that support circuit design are well known.

A logic circuit designed with the aid of such a conventional logic circuit design apparatus sufficiently satisfies the required basic functions. However, in general, logic circuits are required to be able to be tested easily, and for this reason, it is necessary to construct a logic circuit that is easy to test by adding all appropriate circuits to a circuit that satisfies the basic functions. It is being done. Therefore, designing to add all the testability circuits is a task that is not supported by conventional logic circuit design equipment, and conventionally this task had to be performed by the designer himself.

This kind of circuit additive design for testability is work outside the original functional design of logic circuits, and having to design without the support of logic circuit design equipment is a heavy burden on designers. .

This invention was made in order to eliminate all the drawbacks of the conventional ones as described above, and by adding a testability circuit automatic addition mechanism to a logic circuit design device, it is possible to create a logic circuit with a testability circuit added thereto. The overall purpose of this invention is to provide a logic circuit design device that can support the design work.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a tllU input device, (2) an output device, (31
is an arithmetic processing unit, (41 is a data management device, and (5) is a test facilitation circuit automatic addition mechanism. Input device (1),
Output device (2), arithmetic processing device (3), data management device (part 41) I correspond to a conventional logic circuit design device, and the input device (1) and output device (2) allow man-machine design.
It configures the inkface, assists the designer in the design task of the desired@logic circuit, and stores the designed logic circuit diagram (stored by a code representing the circuit diagram or stored in a data management device (
It is well known that the data is stored in 41, so
The explanation will be omitted.

Test) IJ - Automatic circuit addition mechanism for test facilitation (51) - Test facilitation circuit realized by software or program-controlled software; Modification discovery mechanism (6)
, test method determination selection mechanism (7), nII mechanism with test nephrization circuit 18), and side effect determination mechanism (9) (1
will be completed.

Figure 2 shows the testability circuit automatic addition mechanism (5) in Figure 1.
This is a flowchart showing the operation of (201) in the figure.
to (208) u each program step.

3 is an explanatory diagram showing the operation of the test facilitation circuit addition part discovery mechanism shown in FIG.
) (where j = a,...m) is the circuit pattern, (
2) is a designed logic circuit diagram stored in the data management device (41); in this specification, it is assumed that the input circuit diagram a
It's called a. The circuit patterns (11a to l1m) are each part of the input circuit diagram (2).

FIG. 4 is a format diagram showing a state in which the circuit information added by the test facilitation circuit addition mechanism (81) of FIG. 1 is stored in the data management device (41; It is an information structure table, (14k) (
However, =a, . . . n) is connection data in the circuit information, and its structure consists of a (situation tag) and (connection information tag).

Next, VC, the operation of the apparatus shown in FIG. 1 will be explained.

The input circuit diagram α created by operating the input device lj fi+, output device (2), arithmetic processing unit (3j1) as a conventional logic circuit design device is stored in the data management device (41). In addition, various basic patterns (10i) are stored as fixed data in the data management device (41), but are sequentially read out under the control of the arithmetic processing unit +31, and the read basic patterns (10i) are stored as fixed data in the data management device (41).
It is searched whether a circuit pattern (llj) corresponding to 0i) is found in the input circuit diagram (6). This process is shown in FIG.
). Stemp (203)
The result of step (202) is judged in step (202), and if it is not found, go to step (204), complete the entire process for the basic pattern (10□), and perform the next basic pattern (1
The writing starts from step (201) for 01+1). However, if the processing for the basic turn (i ot) is completed, the process tl in FIG. 2 is ended without returning to step (201).

If a circuit turn corresponding to the basic pattern (10i) is found in the input circuit diagram (6), step (205
), the test method determination selection mechanism (7) selects one test method from among the test methods stored for the corresponding basic pattern (10i), and then proceeds to step (206), where test y is selected. In contrast to the test method described above, all the test-facilitating circuits are added in turn 1 (the corresponding circuit according to 4'f'j 181). At this time, as shown in FIG. 4, the changed circuit information r is stored in the data management device (4) as a (situation tag) and (connection information) with new status information.

Next, in step (207), side effect determination processing is performed by the side effect determination mechanism (9). Step (207)
Then, it is determined by various simulators (timing simulator, logic simulator, etc.) whether the basic functions of the input circuit diagram (6) will not be impaired by adding the testability circuit to the circuit pattern. Step (208) is the determination result of step (,207),
If NO (if side effects occur) step (20
9) and instructed to change the test method. In this case, the original circuit is restored according to the contents of the (situation tag) shown in Figure 4, and then the process returns to step (205).
205) determines the next test method and performs the same process as above. If step (, 208) is YES, return to step (202) and repeat the same basic pattern (101).
The input circuit diagram αa is searched for the next circuit ζ turn corresponding to . In this way, one basic turn (
When all the circuit patterns corresponding to 10i) have been processed, the judgment in step (203) becomes No, and the process proceeds to step (204), where the basic pattern is converted to the next (lO1+□
9 and restart from step (201). All basic no(processing for turns (10,) (i =
When steps a to t) are completed, all processing by the apparatus shown in FIG. 1 is completed. Among these steps, step <205),
(206), (207), and (20B) The loop composed of VC2 performs the process of determining the test circuit by trial and error. Although the operation of the power 11 Isoyoko (5) is shown in the program steps of FIG. 2, the operation is similar when the testability circuit automatic addition mechanism (51) is configured by hardware.

According to this invention, a testability circuit property JJ11 part discovery mechanism, a test method determination selection mechanism, a testability circuit addition mechanism, a side effect determination mechanism, and a data management device that fully utilizes tags are designed for logic circuit design. Since it is built into the device, it has the effect of automating circuit design for testability, which was previously done manually.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a flowchart explaining the operation of the automatic testability circuit addition mechanism shown in Fig. 1, and Fig. 3 1-1: Testability shown in Fig. 1. FIG. 4 is an explanatory diagram showing the operation of the integrated circuit addition section discovery mechanism, and FIG. 4 is a format diagram showing the state in which added circuit information is stored. (11... Input device〆, (2)... Output device, (3
)... Arithmetic processing device, (41... Data management device,
(51...Testability circuit automatic addition mechanism, (6)-
・・Test-facilitating circuit with power section discovery mechanism, (7)...
Test method determination selection mechanism, 18) Test facilitation circuit addition mechanism, (9) Side effect determination mechanism, (10□)
(i=a,...t)...Basic pattern, (11j)
(j=a*...m)...Circuit pattern, u3...
Input circuit diagram. Agent Masuo Oiwa Figure 2

Claims (1)

[Claims] (1) An input device for logic circuit information, an arithmetic processing device that performs necessary processing on the logic circuit information input from this input device, and an arithmetic processing device that stores the results processed by this arithmetic processing device and stores all of the above-mentioned storage contents. In a logic circuit design device that supports the design of logic circuits and is equipped with a data management device that outputs data in response to a request from the data management device, and an output device that displays the stored contents of this data management device, the fixed storage area of the data management device is means for storing various basic patterns of a logic circuit diagram to which test circuits are to be added in correspondence with their test methods; and a circuit pattern for sequentially reading out the various basic patterns and corresponding to the read basic patterns. A test-facilitating circuit additional part discovery mechanism that searches for the stored basic functions from a designed logic circuit diagram manually in a data management device, and a circuit pattern searched by the test-facilitative circuit additional part discovery mechanism. , a test method judgment selection mechanism that selects one test method from among the test methods of the basic pattern; and a test method judgment selection mechanism that adds a testability circuit to the basic pattern based on the test method selected by the test method judgment selection mechanism. A side effect determination for determining whether the basic function of the input circuit diagram is not impaired for the circuit pattern to which the testability circuit is added by the testability circuit addition mechanism and the testability circuit addition mechanism. If the circuit pattern to which the above-mentioned test facilitation circuit is added impairs the basic function of the above-mentioned input circuit diagram by the stiffness/side effect judgment mechanism, the test method selected for the circuit pattern shall be completely changed. A logic circuit design device characterized by comprising: means. +zgTest '6 - A test facilitation circuit to be added to the facilitation circuit addition mechanism is determined by trial and error based on a test method selected by a test method determination and selection mechanism. Logic circuit design device according to item 1.