JP2690175B2 - Unequal length code decoding circuit - Google Patents

Description

The present invention relates to a decoding circuit for unequal length codes used in facsimile, image compression and the like.

[Prior Art] In the above-mentioned application, unequal-length code words having different lengths are transmitted as a concatenated bit string. Conventionally, as a technique of decoding each code word from such data, a technique of directly decoding data from an input data using a decoding table (hereinafter referred to as conventional technique A) and a variable-length code having a tree structure are used. It is well known that a technique of sequentially tracing a tree by 1 bit and decoding (hereinafter referred to as a conventional technique B).

First, the prior art A will be described with reference to FIG. The barrel shifter 1 inputs data to be decoded, divides it into, for example, 16 bits, and outputs them in parallel. And with this output ROM2
Address. The ROM 2 stores the decoded data for each unequal length code word and the code length thereof. Here, the 16-bit delimiter is defined so as to correspond to the maximum code length as a code word. For codewords shorter than the maximum code length,
The decoded data is recorded so that it can be decoded with a 16-bit address. The code length is output from the ROM 2 together with the decoded data, and the code length is integrated by the adder 3. Based on the addition information of the adder 3, the barrel shifter 1 shifts by the number of bits of the decoded codeword, and further inputs the data to be decoded into 16 bits. As a result, the head of the output of the barrel shifter 1 is always the head of the next code word.

Next, the related art B will be described with reference to FIG. ROM4
Is a decoding table, which advances the search along the tree structure contained in ROM4 for each bit of the input data, finally reaches the cell storing the end index and the decoded data, and outputs this decoded data. Is. If the Nth bit of the data to be decoded is 1, 1000 is output from ROM4. If the next (N + 1) th bit is 0, the addresses 1000 and 0 are combined to form the address to be searched next. In this way, the tree structure can be traced to reach the cell having the end index, and its decoded data can be extracted.

[Problems to be solved by the invention]

In the prior art A, the data width of the ROM becomes extremely large in order to store the code length while making it correspond to the maximum code length data. In addition, a complicated circuit such as a barrel shifter is required, which makes timing difficult. In the conventional technique B, the number of ROM entry addresses increases, and the ROM capacity increases.

The object of the present invention is to compare the code words bit by bit, find a code word that matches each bit with a simple configuration, and obtain the decoded data corresponding to this code word from the one-to-one correspondence ROM. It is to provide a decoding circuit adapted to be obtained.

[Means for solving the problem]

According to the present invention, all the code words are arranged in the row direction so that the most significant bits are aligned and stored, and a matrix-shaped code table is sequentially stored, one bit at a time from the beginning of the input data. Compare the column from the lower row to the lower row, and for each column, match signal bit “1” from the matched row,
The comparison circuit that outputs “0” for unmatched rows and the AND circuit / latch circuit connected from the input side for each row, and has a circuit configuration that positively feeds back the output of the latch circuit to the AND circuit, Only when the output is input and both the current output of the comparison circuit and the output one bit before are "1",
Regarding the intermediate code match determination unit that sets the output of the latch circuit to “1” and the plurality of lines whose output of the code match determination unit is “1”, the highest priority and the lowest order are given in the line numbers of the code table. It includes two priority encoders for obtaining the number of priority row numbers, and a decoding means for performing data decoding by detecting that a code word coincidence determination is made from the added value of the number numbers of the two encoders. .

[Action]

If the row numbers from 0 to n are assigned to the matrix of the code table, this number indicates each code word. The first bit of the input data is compared with the most significant bit of each code word, and then the next bit of the input data is compared with the next bit of the code word. To detect. The comparison information of this comparison circuit (for example, "1" when they match and "0" when they do not match) is input to the intermediate code matching determination section for each row. The sign matching determination unit stores the result of the previous bit comparison,
If the previous bit comparison does not match, a mismatch “0” is output even if the current bit matches. In this way, the code coincidence determination unit sets the output of each row to "1" only when the results of bit comparison up to this time and up to that time all match. Whether there are a plurality of "1" lines or one line in the code matching determination unit can be determined by adding the output values (row numbers) of the upper and lower priority encoders and from the added value.
If there is only one "1" row, it means that the codeword is finally identified, and the decoded data can be obtained from the ROM using the row number as an address.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram, in which 100 is a code table, in which eight code words are displayed in a matrix with the most significant bits aligned. Data 110 to be decoded is continuously input as a series of bit strings without interruption.
Although not shown in the figure for holding the data, a 1-bit flip-flop may be used. The comparison circuit 120 sequentially compares the data bit and each bit in the column direction of the code table 100 by the clock CK. Therefore, the input data bit to be compared and the column direction bit 100 are moved and compared. The comparison circuit 120 includes an EX-NOR circuit for each row, and outputs "1" as the row output when the corresponding bits of the input and the code word match.

Next, 130 is a code matching determination unit, the internal configuration of which consists of an AND circuit and a latch circuit for latching its output. The output of the latch circuit becomes the output of the code matching determination unit, and this output is positively fed back. It is one input of the AND circuit on the input side. As can be seen from this circuit configuration, only the rows where the output of the comparison circuit 1 is “1” continuously are the code matching determination unit 130.
Outputs "1". As an initial condition, each row output of the code matching determination unit 130 is set to "1".

Next, the priority encoders 140 and 141 are shown in FIGS.
Outputs the number of line numbers of higher priority and lower priority according to the truth table of. For example, if there are two lines that are "1" in the code matching determination unit 130 and there are a sixth line and a third line, the output of the priority encoder 140 as a 3-bit output is 110 (that is, 6),
The priority encoder 141 becomes 101 (that is, 5). The above priority output value is added by the adder circuit 150, and the added value (MOD
8), 011 (that is, 3). On the other hand, if only one row in the 6th row is "1", it becomes 110,001 and is added to 111 (that is, 7), which is a number obtained by subtracting 1 from the code number 8. In this relationship, when only one row has a value of "1" in any row, the added value is 111, so that it is possible to detect that the code determination is completed.

When the output of the addition circuit 150 becomes 111, the end detection circuit 151
It is possible to distinguish and identify the codewords by detecting with, and the ROM 152 that outputs the output of the priority encoder 140 as an address input,
The end detecting circuit 151 forms a decoding means, and the detection signal 151a from the end detecting circuit 151 causes the decoded data to be output from the ROM 152. In this way, in this embodiment, it is possible to continuously obtain decoded data for continuous input data.

Below, in order to clarify the operation of the present embodiment, the operation of the present embodiment circuit will be traced and shown concretely bit by bit in FIGS. 3 (a) and 3 (b). Figure 3 (a) shows the default settings.
The outputs of the code matching determination unit 130 are all set to "1". Further, the priority encoders 140 and 141 are the same circuit, and only the input connections are inverted and continued. Although the description of this operation is omitted, when the adder circuit 150 becomes 111 (that is, 7), the decoding is completed, the decoded data is output from the ROM 152, and the detection signal is output.
151a initializes all outputs of the code matching determination unit 130 to 1.

〔The invention's effect〕

As described above, the present invention sequentially compares the input data bit by bit with the bits of each row of the code table,
As long as each bit continuously matches each bit of the code table, the output of the code match determination unit is set to "1" and the output of the code match determination unit is "1", that is, the code word number in the code table. Is calculated by the upper and lower priority encoders, and when the output value of this encoder is added to reach a specific output value, it is detected that the output of the code matching determination unit is "1" in only one row. , Separates codewords from input data. Since the line that becomes "1" represents the codeword number,
By using this code word number as the address of the ROM decoding table, the decoded data can be obtained in a one-to-one manner.

Therefore, the ROM in the present invention need only be a code table and a decoded data memory.
M capacity is minimum. Furthermore, input data can be input by a clock to obtain decoded data in real time.
Further, the barrel shifter and its timing circuit, which are required in the prior art A, are not necessary, and the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a truth table of a priority encoder, and FIGS. 3 (a) to 3 (d) are diagrams showing a circuit operation for each bit, and FIG. 5 and FIG. 5 respectively show the prior art. 100 ... Code table, 110 ... Input data, 120 ... Comparison circuit, 130 ... Code matching determination section, 140,141 ... Priority encoder, 150 ... Addition circuit, 151 ... End detection circuit, 152 ... For decoding ROM.

Claims (1)

(57) [Claims] 1. A circuit for identifying and decoding each codeword from data input as consecutive bits by concatenating unequal-length codewords, and a. Are arranged in a row direction and stored in a matrix form, and b. The input data is sequentially bit by bit from the beginning, and the uppermost matrix of the code table is compared to the low-order example. ,
A comparison circuit that outputs a match signal bit “1” from the matched row and a “0” for the non-matched row, and c. An AND circuit / latch circuit is connected from the input side for each row, and the output of the latch circuit is an AND circuit. The output of the comparison circuit is input, and the output of the latch circuit is set to "1" only when both the current output of the comparison circuit and the output one bit before are "1". An intermediate code match determination unit, and d. The number of lines having the highest priority and the lowest priority in the line numbers of the code table for a plurality of lines for which the output of the code match determination unit is "1". And a decoding means for performing data decoding by detecting that a codeword coincidence determination is made from the added value of the number numbers of the two encoders. Isometric code decoding circuit.