JPH0444466A - Unequal length code decoding circuit - Google Patents

Abstract

PURPOSE:To obtain a decoding data in real time with simple circuit constitution by providing two priority encoders obtaining number of lines with highest priority and lowest priority on line numbers of a code table as to plural lines of logical 1 being outputs of a code coincident discrimination section and a decoding means detecting the coincidence discrimination of a code word from a sum of the numbers of the two encoders to decode data to the coding decoding circuit. CONSTITUTION:A code coincidence discrimination section 130 outputs a logical l level when the section 130 discriminates a line being an output of a comparator circuit 120 to be consecutively '1'. Moreover, each output of each line of the code coincidence discrimination section 130 is set to '1' as the initial condition. Moreover, priority encoders 140,141 output a line number with highest priority and lowest priority. An adder circuit 150 adds outputs with priority. A code word is discriminated and identified by using an end detection circuit 151 to detect it that an output of the adder circuit 150 is 111 and a ROM 152 taking an output of the priority encoder 140 as an address input and the end detection circuit 151 form a decoding means and a detection signal 151a from the end detection circuit 151 is used to output a decoded data from the ROM 152.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding circuit for unequal length codes used in facsimile, image compression, and the like.

[Conventional technology]

In the above application, unequal-length codewords of different lengths are transmitted as a concatenated bit string. Conventionally, as a technique for decoding each code word from such data, there is a technique for decoding data directly from input data using a decoding table (hereinafter referred to as conventional technique A).
(hereinafter referred to as prior art B) is well known.

First, prior art A will be explained with reference to FIG.

The barrel shifter 1 inputs data to be decoded, divides it into 16 bits, for example, and outputs it in parallel. Then, ROM2 is addressed with this output. The ROM 2 stores decoded data for each unequal length code word and its code length. Here, the 16-bit delimiter is determined to correspond to the maximum code length of the code word. Even for code words shorter than the maximum code length, decoded data is recorded so that they can be decoded using 16-bit addresses. The code length is output from the ROM 2 along with the decoded data, and this code length is integrated by the adder 3. Based on the addition information of adder 3,
The barrel shifter 1 shifts the decoded code word by the number of bits, and further inputs data to be decoded to 16 bits. As a result, the beginning of the output of barrel shifter 1 is always the beginning of the next code word.

Next, prior art B will be explained with reference to FIG.

ROM4 is a decoding table, which searches along the tree structure contained in ROMA for each bit of input data.
It finally reaches the cell that stores the end index and decoded data, and outputs this decoded data. If the Nth bit of the data to be decoded is 1, it is 100 in ROM4.
0 is output.

If the next (N+1) focal point is 0, the 1000 and 0 are combined to form the address to be searched next. In this way, the tree structure can be followed to reach the cell with the end index and its decoded data can be extracted.

[Problem to be solved by the invention]

In prior art A, the data width of the ROM becomes extremely large in order to accommodate data with the maximum code length and to store the code length. Moreover, a complicated circuit such as a barrel shifter is required, and the timing becomes complicated. In prior art B, the number of entry addresses in the ROM increases, and the capacity of the ROM increases.

The purpose of the present invention is to compare bit by bit with the code word,
A code word that matches each bit is found with a simple structure, and the decoded data corresponding to this code word is converted into a one-to-one correspondence R
The object of the present invention is to provide a decoding circuit that can be obtained from OM.

[Means to solve the problem]

The present invention uses a matrix-like code table that stores all code words arranged in the row direction with their most significant bits aligned, and one bit at a time sequentially from the beginning of input data.
A comparison circuit compares the code table from the highest column to the lowest example, and outputs a match signal bit "1" from the matched row for each column and "0" from the mismatched row; It has a circuit configuration in which an AND circuit/latch circuit is connected, and the output of the launch circuit is fed back to the AND circuit, and the output of the comparison circuit is input, and both the current output and the previous output of the comparison circuit are An intermediate code match determination section that sets the output of the launch circuit to "1" only when the code is "1", and a row number of the code table for a plurality of rows in which the output of the code match determination section is "1". Two priority encoders calculate the numbers of rows with top priority and lowest priority, and data decoding is performed by detecting that a code word match has been determined from the added value of the number numbers of the two encoders. and decoding means for performing the decoding.

[Effect]

If the matrix of the code table has row numbers from 0 to n, this number will indicate each code word. The first bit of the input data is compared with the most significant bit of each code word, and then the next bit of the input data is compared with the next most significant bit of the code word. To detect. Comparison information of this comparison circuit (for example, if it matches, it will be “1°”, and if it does not match, it will be “0”)
is input to an intermediate code match determination unit for each row. The code match determination unit stores the result of the previous via comparison, and outputs a mismatch "O" even if the bits match this time if there is a mismatch in the previous bit comparison. In this way, the code match determination unit outputs "1" for each row only when all the bit comparison results from this time and before match.
It is said that Whether there are a plurality of rows with "1" in the code match determination unit or one row can be determined by adding the output values (row numbers) of the upper and lower priority encoders and from the added value. If there is only one line with “1”, it means that the code word has finally been identified, and R
Decoded data can be obtained from OM.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram, and 100 is a code table, in which eight code words are displayed in a matrix with their most significant bits aligned.

Reference numeral 110 indicates data to be decoded, which is continuously input as a series of bit strings. Although this data is not shown, a 1-bit flip-flop may be used to hold the data. Sequential data bit and code table 10 by clock CK
A comparator circuit 120 compares each 0 bit in the column direction. Therefore, the input data bit to be compared and the column direction bit 100 are moved and compared. The comparison circuit 120 includes an EX-NOR circuit for each row, and outputs "1" as the output when the corresponding bits of the input and code words match.

Next, 130 is a code match determination unit, whose internal configuration consists of an AND circuit and a latch circuit that latches its output, and the output of the latch circuit becomes the output of the code match determination unit.
This output is positively fed back and becomes one input of the AND circuit on the input side. As can be seen from this circuit configuration, only rows in which the output of the comparator circuit 1 is continuously "1" are outputted as "1" by the code match determination unit 130. Note that, as an initial condition, each printing power of the code match determination unit 130 is set to "1".

Next, the priority encoders 140 and 141 are as shown in FIG. 2(a).
Using the truth table in (b), output the number of row numbers with higher priority and lower priority. For example, “11” of the code match determination unit 130
If there are two rows, the 6th and 3rd rows, then 3
The output of priority encoder 140 as bit output is 110
(i.e. 6), priority encoder 141 is 101 (
In other words, 5).

The above-mentioned priority output values are added by the adder circuit 150, and the added value (MOD8) is 011 (that is, 3).

On the other hand, if only one item in the 6th row is 61", it will be 110.
The result is 001, which is added to 111 (that is, 7), which is the number excluding 1 from the code number 8. In this relationship, when only one row becomes "al" in any row, the added value becomes 111, so that it can be detected that the sign determination is completed.

By detecting that the output of the adder circuit 150 is 111 with the end detection circuit 151, code words can be separated and identified.
The OM 152 and the end detection circuit 151 form a decoding means, and the detection signal 151a from the end detection circuit 151 causes the ROM 152 to output decoded data. In this manner, in this embodiment, decoded data can be continuously obtained for continuous input data.

Below, in order to clarify the operation of this embodiment, Figure 3 (
8) to (dl), the operation of the circuit according to the present invention is specifically traced bit by bit.

Furthermore, the priority encoders 140 and 141 are the same circuit, and only the input connections are reversed.

Although the explanation of this operation is omitted, the addition circuit 150
(i.e. 7), the decoding is completed and ROM1
52 outputs decoded data, and also outputs a detection signal 151.
All outputs of the code match determination unit 130 are initialized to 1 by a.

〔Effect of the invention〕

As explained above, the present invention sequentially compares the input data bit by bit with the bits in each row of the code table, and as long as each bit successively matches each bit of the code table, the code match determination unit The output of the encoder is set as "1", and the row in which the output of the code matching determination unit is "1", that is, the code word number in the code table, is determined by the upper and lower priority encoders, and the output values of these encoders are added to determine the specific When the output value is reached, it is detected that the output of the code matching determination section is "1" only in one row, and the code word is separated from the input data. Since the above-mentioned row that becomes "1" represents the code word number, decoded data can be obtained on a one-to-one basis by using this code word number as the address of the decoding table of the ROM.

Therefore, the ROM in the present invention only needs to be two, a code table and a decoded data memory, and this R
OM capacity is minimal. Furthermore, by inputting clock input data, decoded data can be obtained in real time. Furthermore, the barrel shifter and its timing circuit, etc., which were necessary in prior art A, are not required, and the circuit configuration can be simplified.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a truth table of a priority encoder, FIGS. 3(a) to (d) are diagrams showing circuit operation for each bit, and FIG. 4 and FIG. 5 respectively show the prior art. 100-m-code table, 110-human data,
120--comparison circuit, 130-code match determination unit, 1
40.141--priority encoder, 150-addition circuit, 151--end detection circuit, 2-
...ROM for decoding.

Claims (1)

[Scope of Claims] A circuit for identifying and decoding each code word from data inputted as continuous bits in which code words of unequal length are concatenated, comprising: a. A matrix-like code table in which the bits are aligned and stored in a row-wise manner, and b. Compare the input data one bit at a time starting from the top of the code table, starting from the most significant column to the lowest column. For each
A comparison circuit that outputs a match signal bit "1" from a matched row and "0" for a mismatched row; c. An AND circuit/latch circuit is connected from the input side for each row, and the output of the latch circuit is connected to an AND circuit. The output of the comparison circuit is inputted, and the current output of the comparison circuit and the previous output of 1 bit are both "1".
an intermediate code match determination section that sets the output of the latch circuit to "1" only when d. , two priority encoders that calculate the number numbers of the rows with the highest priority and the lowest priority; An unequal length code decoding circuit comprising: decoding means for performing decoding.