JP2687733B2 - Failure detection circuit for large screen display unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection circuit for a large screen display unit.

[0002]

2. Description of the Related Art FIG. 2 shows a large-sized image display device (large screen) which is formed by arranging a plurality of display units in a matrix of vertical lines and horizontal lines so that a large number of units can be viewed from a distance. 2 shows a control circuit of the display elements of the matrix arrangement (N × M) that constitute the display unit, 1 is a flip-flop, and 2 is a driver of the display element (writing tube) 3. The data signal D, the set signal S, and the reset signal R sent from a main controller (not shown)
The level of the output Q changes. The data signal D is common to one vertical line display element of the display unit, and the set signal S and the reset signal R are common to one horizontal line display element. Therefore, by applying the set signal S in a state where the data signals D for one horizontal row are prepared, the display elements for one horizontal row are turned on. This operation is sequentially performed row by row to form an image. Reset signal R
Determines the lighting time of the display element 3, and the brightness is controlled by this.

[0003]

In this conventional device,
If the display control signal (data signal D, set signal S or reset signal R) is not properly input to the control circuit of the corresponding display element due to poor contact of the connector, etc., this cannot be detected. There is a problem that an image different from the expected image is displayed.

The present invention has been made to solve this problem, and an object thereof is to provide a failure detection circuit for a display unit for a large screen capable of detecting normality or abnormality of the input system of a display control signal. And

[0005]

In order to achieve the above object, the present invention provides pulse generation for vertical lines and horizontal lines for generating pulses respectively synchronized with display control signals of vertical lines and horizontal lines for a display unit. A circuit, a counter for vertical lines and a horizontal line that counts an internal clock and uses the outputs of the pulse generation circuits for vertical lines and horizontal lines as reset signals, and a counter for vertical lines and horizontal lines. A circuit having a circuit for generating an abnormality detection signal when either one counts a set value and counts up.

[0006]

According to the present invention, a counter for counting the internal clock for each display control signal is provided, and if the display control signal is not input even after the input cycle of the display control signal to the display element control circuit has elapsed, The counter counts up and detects and stores the abnormality.

[0007]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 41 denotes a horizontal line pulse generation circuit (monostable multivibrator) which generates a pulse in synchronization with the rising of the Q ₂ output of the flip-flop 1, and this pulse is used for the horizontal line. It serves as a reset signal for the counter 51. Reference numeral 42 denotes a vertical line pulse generation circuit (monostable multivibrator)
A pulse synchronized with the rising edge of is generated, and this pulse serves as a reset signal for the vertical line counter 52. The counters 51 and 52 count the internal clocks and output when the count value reaches (counts up) a set value. Reference numeral 6 is a latch circuit which receives the output of the counter 51 or 52 through the OR element and latches it. An open collector transistor 7 is driven by the output of the AND element that receives the alarm confirmation signal A and the output of the latch circuit 6, and outputs a failure detection signal (alarm signal) B. The monostable multivibrator 41 and the counter 51 are provided for all set signals S and reset signals R, and the monostable multivibrator 42 and the counter 52 are provided.
Are provided for all data signals D.

In this structure, the data signal D supplied to the flip-flop 1 is branched and supplied to the monostable multivibrator 42, and the monostable multivibrator 42 is synchronized with the rising edge of the data signal D and has a pulse of a predetermined width. To occur. When the data signal D arrives at the flip-flop 1 without any abnormality (within a predetermined input cycle), the counter 52 receives the output of the monostable multivibrator 42 before it is counted up and is reset. Keeps the "L" level, but if the data signal D does not arrive at the flip-flop 1, the counter 52 counts up after the input cycle and the output changes to the "H" level. Similarly, when the set signal S and the reset signal R arrive at the flip-flop 1 without any abnormality, the counter 51 receives the output of the monostable multivibrator 41 before counting up, so the output of the counter 51 is “L”. to maintain the level, but if you did not come to the set signal S or reset signal R flip-flop 1, the counter 51 whose output counts up to change to "H" level. The set of the monostable multivibrators 41 and 42 and the counters 51 and 52 is provided for all the flip-flops 1, and the outputs of all the counters 51 and 52 are O.
It is input to the latch circuit 6 through the R element. If even one of the outputs of all the counters 51 and 52 becomes "H",
The latch circuit 6 stores "abnormal" and outputs its output "H".
Changes to (abnormal signal). When the alarm confirmation signal A (H level) is given, the output of the AND element changes to "H", so that the transistor 7 outputs (failure detection signal B).

[0010] Incidentally, when there is no full set signal to the (screen non-display period), and ON / OFF by software input D to flip flop 1, enabling fault detection.

Further, the multiple display units in large screen arranged in a matrix manner, a common alarm confirmation signal A next La <br/> Inn, if a common collector output B of the transistor 7 in the vertical line, necessary Cables can be minimized.

[0012]

As described above, the present invention is provided with the counter for counting the internal clock for each display control signal, and the display control signal is not input even after the input cycle of the display control signal to the control circuit has elapsed. the, with the construction of detecting an abnormality the counter counts up when, co
An abnormality in the input line of the display control signal, such as a contact failure of the connector , can be detected easily for each input line with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional display element control circuit.

[Explanation of symbols]

 1 Flip-flop 2 Driver 3 Display element 6 Latch circuit 7 Transistor 41, 42 Monostable multivibrator 51, 52 Counter A Alarm confirmation signal B Failure detection signal D Data signal S Set signal R Reset signal

Claims (2)

(57) [Claims] 1. A vertical line for generating a pulse synchronized with a display control signal of a vertical line and a horizontal line for each display element of a display unit for a large screen in which a plurality of display elements are arranged in a matrix. And a horizontal line pulse generation circuit, a vertical line and horizontal line counter that counts the internal clock and uses the outputs of the vertical line and horizontal line pulse generation circuits as reset signals, and the vertical line counter. And a circuit for generating and storing an abnormal signal when any one of the horizontal line counters counts up, and a failure detection circuit for a large screen display unit. 2. The abnormal signal is inputted to an open collector transistor on condition that an alarm confirmation signal is given, and the collector output of the transistor is sent to the outside as an abnormal signal. Failure detection circuit for the large screen display unit described.