JP2685048B2 - Method for manufacturing substrate assembly for plasma display panel - Google Patents

Method for manufacturing substrate assembly for plasma display panel

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Publication number
JP2685048B2
JP2685048B2 JP7997A JP7997A JP2685048B2 JP 2685048 B2 JP2685048 B2 JP 2685048B2 JP 7997 A JP7997 A JP 7997A JP 7997 A JP7997 A JP 7997A JP 2685048 B2 JP2685048 B2 JP 2685048B2
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JP
Japan
Prior art keywords
pattern
glass substrate
electrodes
plasma display
predetermined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7997A
Other languages
Japanese (ja)
Other versions
JPH09171770A (en
Inventor
衛 宮原
利之 南都
傳 篠田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
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Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7997A priority Critical patent/JP2685048B2/en
Publication of JPH09171770A publication Critical patent/JPH09171770A/en
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Publication of JP2685048B2 publication Critical patent/JP2685048B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】この発明は、プラズマディス
プレイパネル用基板構体の製造方法に係り、特に電極の
絶縁層やクロストーク防止用隔壁の焼成工程におけるガ
ラス基板の収縮による寸法誤差を補償した電極あるいは
クロストーク防止用隔壁のパターン形成法に関する。 【0002】 【従来の技術】プラズマディスプレイパネル(以下PD
Pと記す)を構成する一対の基板(基板構体)の内の一
方の基板には、所定パターンの電極、ガラスの絶縁層
(以下IF層と略す)、隣接放電セルのクロストーク防
止用隔壁を順次積層したものや、前記クロストーク防止
用隔壁上にさらに電極を形成したものがある。一方、そ
れら電極、クロストーク防止用隔壁のパターンは高密度
化、多素子化が進み、ピッチ360μm、パターン層1
00μm、パターン総数640本に及んでいる。 【0003】従って、精度が高く、作業効率の良いパネ
ル用基板構体の製造方法が要望されていた。 【0004】 【発明が解決しようとする課題】PDP用基板構体のベ
ースとなるガラス基板にはソーダライムガラスが用いら
れるが、この材質はクロストーク防止用隔壁やIF層の
焼成温度である500〜600℃を経過後、図2に代表
例にて示す如く焼成前の寸法に対し、焼成1回で収縮代
0.0323%、収縮後0.999679、同じく2回
でそれぞれ0.0537%、0.999473になる。
尚、これら収縮代は焼成条件により、それぞれ0.02
61〜0.0398%、0.0407〜0.0549%
のばらつきがある。 【0005】この収縮は、230mmのガラス基板では
それぞれ74μm、124μmに及ぶ。従来ピッチが大
きく、パターン幅も大きく、総本数が少ない場合には、
この程度の誤差は無視できたが、既述の如く最近はピッ
チ360μm、電極幅100μm、総数640本の微
小、多数パターンが用いられるようになり、これらの収
縮値は無視できない値となってきた。 【0006】この発明は、以上のような従来の状況か
ら、簡易な方法で精度の高い電極およクロストーク防止
用隔壁のパターン形成が可能なPDP用基板構体の製造
方法を提供することを目的としている。 【0007】 【課題を解決するための手段】この発明は、ガラス基板
上に所定パターンの電極を形成し、その上に所定温度で
焼成される絶縁層を形成した後、所定パターンのクロス
トーク防止用隔壁を形成するプラズマディスプレイパネ
ル用基板構体の製造において、前記ガラス基板上に所定
ピッチで相互に平行な複数本の線状電極を形成する際、
当該電極の幅方向のピッチと全電極の占有幅が前記絶縁
層を焼成する時のガラス基板の収縮量を見込んだ寸法分
だけ所定寸法よりも大きな寸法となるパターンで形成
し、この後前記絶縁層をガラスペーストを塗布し焼成す
ることにより形成し、さらに該絶縁層上に前記電極パタ
ーンの間に位置する関係で所定間隔の平行なパターンに
よりクロストーク防止用隔壁を形成することを特徴とす
るプラズマディスプレイパネル用基板構体の製造方法を
提供するものである。 【0008】ガラス基板上に形成された前記電極のパタ
ーンは、その上に絶縁層を形成した時に所定量収縮する
けれども、その収縮パターンが絶縁層上に形成されるク
ロストーク防止用隔壁のパターンと適度な位置関係にな
るので、電極およびクロストーク防止用隔壁のパターン
間の位置ずれは実質的に皆無になる。 【0009】 【発明の実施の形態】 〔第1の実施形態〕図1は第1の実施形態に係るメモリ
形PDPにおける一方の基板構体の構成図である。図に
おいて、1はガラス基板、2は線状パターンの電極、3
はIF層、4はクロストーク防止用隔壁である。 【0010】電極パターン2は、ガラス基板1上に蒸着
やスパッタ等の方法により形成される。IF層3は、電
極パターン2上にガラスペーストを塗布した後、500
〜600℃にて焼成することで形成される。クロストー
ク防止用隔壁4は、上記IF層焼成後の電極パターン2
に位置合わせ、すなわち隔壁4のピッチの中央に電極パ
ターン2が正しく配置されるようにしてプリント法によ
り形成される。 【0011】今、これらパターンの寸法を具体的な数値
により説明する。完成後の電極パターンがピッチ360
μm、総数640本の場合、ガラス基板上のこの全パタ
ーンが占める幅(全電極パターンの占有幅)は0.36
×(640−1)=230.04mmである。従って、
IF層3を焼成する前の電極パターン2のピッチおよび
全電極パターンの占有幅は、IF層焼成条件により0.
9996〜0.9998倍にばらついて収縮するので、
実際の焼成条件に適応した収縮比を選択して適用する
が、今その代表的な値として、収縮率の中心値0.99
97を用いると次のように求められる。即ち、 ピッチ=360/0.9997=360.11μm 占有幅=230.04/0.9997=230.11mm である。この寸法による電極パターン2を形成後、IF
層形成のためにIF層用ガラス3を塗布し、500〜6
00℃の所定の温度で焼成すると、前述したように電極
パターンはガラス基板1と共に収縮するが、収縮後のピ
ッチおよび全パターン占有幅はこの上に位置合わせされ
るクロストーク防止用隔壁パターン4のピッチおよび全
パターン占有幅と一致する。 【0012】なお収縮には、焼成条件により2.30〜
3.98×104 のばらつきがあるので、その焼成条件
に従った最適値が上記範囲から決定される。 〔第2の実施形態〕本発明者らが先に特願昭60−16
0952号(特開昭62−22352号)により提案し
た面放電型ガス放電パネルにおいては、一方のガラス基
板に電極、IF層、クロストーク防止用隔壁、電極が順
次積層して形成されており、IF層およびクロストーク
防止用隔壁の形成において500〜600℃の焼成工程
が含まれる。 【0013】このように焼成工程が2回の場合、図2に
示す如く更に収縮が進み、第1回目焼成前の寸法から
0.0537%収縮する。従って、2回の焼成工程を有
する場合は、その2回目の焼成後に位置合わせされるパ
ターンの寸法を0.9993〜0.9996の中から、
焼成条件に適して選ばれた収縮比で割った値を第1回目
焼成前の寸法とする。 【0014】焼成工程が3回以上に及ぶ場合も、同様の
考え方を適用する。 【0015】 【発明の効果】この発明によれば、極めて簡易な方法
で、高精度の電極パターンおよびクロストーク防止用隔
壁パターンがガラス基板上に効率よく形成できるので、
PDPの品質向上と原価低減に寄与しその工業的効果は
頗る大である。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate structure for a plasma display panel, and more particularly to a glass substrate in a firing process of insulating layers of electrodes and barrier ribs for preventing crosstalk. To a pattern forming method of electrodes or crosstalk preventing partition walls that compensates for dimensional error due to shrinkage of particles. Plasma display panels (hereinafter referred to as PD
One of the pair of substrates (referred to as P) constituting the substrate (substrate structure) is provided with an electrode having a predetermined pattern, a glass insulating layer (hereinafter abbreviated as IF layer), and a crosstalk preventing partition wall of an adjacent discharge cell. There are those sequentially laminated, and those in which an electrode is further formed on the partition wall for crosstalk prevention. On the other hand, the pattern of the electrodes and the partition wall for crosstalk prevention is becoming denser and the number of elements is increasing, and the pitch is 360 μm and the pattern layer
The number of patterns is 00 μm and the total number of patterns is 640. Therefore, there has been a demand for a method of manufacturing a panel substrate assembly having high accuracy and high work efficiency. [0004] Soda lime glass is used for the glass substrate that is the base of the PDP substrate assembly, and this material is the firing temperature of the partition wall for preventing crosstalk and the IF layer, which is 500 to 500. After 600 ° C., the shrinkage allowance is 0.0323% after one firing, 0.999679 after shrinkage, and 0.0537% after two shrinks, respectively, as compared to the dimensions before firing as shown in the representative example in FIG. It becomes 0.99473.
The shrinkage allowance is 0.02 each depending on the firing conditions.
61-0.0398%, 0.0407-0.0549%
There are variations. This shrinkage reaches 74 μm and 124 μm on a 230 mm glass substrate, respectively. When the conventional pitch is large, the pattern width is large, and the total number is small,
Although such an error can be ignored, recently, as described above, a minute and a large number of patterns with a pitch of 360 μm, an electrode width of 100 μm, and a total of 640 are used, and these contraction values have become values that cannot be ignored. . In view of the above conventional circumstances, it is an object of the present invention to provide a method of manufacturing a PDP substrate structure capable of forming a highly precise pattern of electrodes and crosstalk preventing partitions by a simple method. I am trying. According to the present invention, an electrode having a predetermined pattern is formed on a glass substrate, and an insulating layer which is fired at a predetermined temperature is formed on the electrode, and then crosstalk of the predetermined pattern is prevented. In the production of a plasma display panel substrate structure for forming partition walls, when forming a plurality of linear electrodes parallel to each other at a predetermined pitch on the glass substrate,
The electrodes are formed in a pattern in which the pitch in the width direction of the electrodes and the occupied width of all the electrodes are larger than a predetermined dimension by a dimension that allows for the amount of shrinkage of the glass substrate when firing the insulating layer, and then the insulating layer is formed. The layer is formed by applying a glass paste and baking it, and further, the crosstalk preventing partition wall is formed on the insulating layer by a parallel pattern having a predetermined interval so as to be located between the electrode patterns. A method of manufacturing a substrate structure for a plasma display panel is provided. The pattern of the electrodes formed on the glass substrate shrinks by a predetermined amount when the insulating layer is formed thereon, but the contracted pattern is the pattern of the partition for crosstalk prevention formed on the insulating layer. Since there is an appropriate positional relationship, there is substantially no positional deviation between the patterns of the electrodes and the crosstalk preventing partition. First Embodiment FIG. 1 is a configuration diagram of one substrate structure in a memory type PDP according to the first embodiment. In the figure, 1 is a glass substrate, 2 is a linear pattern electrode, 3
Is an IF layer, and 4 is a partition for crosstalk prevention. The electrode pattern 2 is formed on the glass substrate 1 by a method such as vapor deposition or sputtering. The IF layer 3 is formed by applying a glass paste on the electrode pattern 2 and then 500
It is formed by firing at ~ 600 ° C. The partition 4 for preventing crosstalk is the electrode pattern 2 after the above IF layer firing.
Is formed by the printing method so that the electrode pattern 2 is aligned correctly at the center of the pitch of the partition walls 4. Now, the dimensions of these patterns will be described with specific numerical values. The completed electrode pattern is pitch 360
In the case of μm and the total number is 640, the width occupied by all the patterns on the glass substrate (width occupied by all electrode patterns) is 0.36.
X (640-1) = 230.04 mm. Therefore,
The pitch of the electrode pattern 2 and the occupying width of all the electrode patterns before firing the IF layer 3 depend on the firing conditions of the IF layer.
Since it contracts by 9996 to 0.9998 times,
The shrinkage ratio adapted to the actual firing conditions is selected and applied. Now, as a typical value, the central value of the shrinkage ratio is 0.99.
When using 97, the following is obtained. That is, Pitch = 360 / 0.9997 = 360.11 μm Occupied width = 230.04 / 0.9997 = 230.11 mm After forming the electrode pattern 2 having this size, the IF
IF layer glass 3 is applied to form a layer, and 500 to 6
When baked at a predetermined temperature of 00 ° C., the electrode pattern shrinks together with the glass substrate 1 as described above, but the pitch after shrinkage and the entire pattern occupancy width of the partition pattern 4 for crosstalk prevention are aligned on this. Matches the pitch and width of the entire pattern. It should be noted that the shrinkage is from 2.30 depending on the firing conditions.
Since there is a variation of 3.98 × 10 4 , the optimum value according to the firing conditions is determined from the above range. [Second Embodiment] The present inventors first filed Japanese Patent Application No. 60-16
In the surface discharge type gas discharge panel proposed by Japanese Patent Laid-Open No. 0952/1987, an electrode, an IF layer, a barrier for crosstalk prevention, and an electrode are sequentially laminated on one glass substrate, A firing step at 500 to 600 ° C. is included in the formation of the IF layer and the partition for crosstalk prevention. When the firing process is performed twice as described above, the shrinkage further progresses as shown in FIG. 2, and the shrinkage is 0.0537% from the size before the first firing. Therefore, in the case of having two firing steps, the dimension of the pattern to be aligned after the second firing is selected from 0.9993 to 0.9996.
The value obtained by dividing by the shrinkage ratio selected according to the firing conditions is the dimension before the first firing. The same concept is applied when the firing process is performed three times or more. According to the present invention, a highly accurate electrode pattern and crosstalk preventing partition pattern can be efficiently formed on a glass substrate by an extremely simple method.
It contributes to the quality improvement and cost reduction of PDP, and its industrial effect is great.

【図面の簡単な説明】 【図1】第1実施形態に係るプラズマディスプレイパネ
ル用基板構体の要部断面図、 【図2】焼成によるガラス基板の収縮測定値を説明する
ための図である。 【符号の説明】 1 ガラス基板、 2 電極パターン、 3 IF層、 4 クロストーク防止用隔壁
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a main part of a plasma display panel substrate assembly according to a first embodiment, and FIG. 2 is a diagram for explaining shrinkage measurement values of a glass substrate by firing. [Explanation of reference numerals] 1 glass substrate, 2 electrode pattern, 3 IF layer, 4 barrier for crosstalk prevention

Claims (1)

(57)【特許請求の範囲】 1.ガラス基板上に所定パターンの電極を形成し、その
上に所定温度で焼成される絶縁層を形成した後、所定パ
ターンのクロストーク防止用隔壁を形成するプラズマデ
ィスプレイパネル用基板構体の製造方法であって、 前記ガラス基板上に所定ピッチで相互に平行な複数本の
線状電極を形成する際、当該電極の幅方向のピッチと全
電極の占有幅が前記絶縁層を焼成する時のガラス基板の
収縮量を見込んだ寸法分だけ所定寸法よりも大きな寸法
となるパターンで形成し、この後前記絶縁層をガラスペ
ーストを塗布し焼成することにより形成し、さらに該絶
縁層上に前記電極パターンの間に位置する関係で所定間
隔の平行なパターンによりクロストーク防止用隔壁を形
成することを特徴とするプラズマディスプレイパネル用
基板構体の製造方法。
(57) [Claims] A method of manufacturing a substrate structure for a plasma display panel, comprising forming electrodes having a predetermined pattern on a glass substrate, forming an insulating layer that is baked at a predetermined temperature on the glass substrate, and then forming barrier ribs for preventing crosstalk having a predetermined pattern. Then, when forming a plurality of linear electrodes parallel to each other at a predetermined pitch on the glass substrate, the pitch in the width direction of the electrodes and the occupied width of all electrodes of the glass substrate when firing the insulating layer It is formed in a pattern having a size larger than a predetermined size by a size that allows for the amount of shrinkage, and then the insulating layer is formed by applying a glass paste and baking it, and further between the electrode patterns on the insulating layer. A method for manufacturing a substrate structure for a plasma display panel, characterized in that the barrier ribs for preventing crosstalk are formed by parallel patterns having a predetermined interval in relation to each other.
JP7997A 1997-01-06 1997-01-06 Method for manufacturing substrate assembly for plasma display panel Expired - Lifetime JP2685048B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7997A JP2685048B2 (en) 1997-01-06 1997-01-06 Method for manufacturing substrate assembly for plasma display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7997A JP2685048B2 (en) 1997-01-06 1997-01-06 Method for manufacturing substrate assembly for plasma display panel

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP61022560A Division JPH0831304B2 (en) 1986-02-03 1986-02-03 Method for manufacturing plasma display panel

Publications (2)

Publication Number Publication Date
JPH09171770A JPH09171770A (en) 1997-06-30
JP2685048B2 true JP2685048B2 (en) 1997-12-03

Family

ID=11464161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7997A Expired - Lifetime JP2685048B2 (en) 1997-01-06 1997-01-06 Method for manufacturing substrate assembly for plasma display panel

Country Status (1)

Country Link
JP (1) JP2685048B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4554778B2 (en) * 2000-07-18 2010-09-29 パナソニック株式会社 Machine difference verification method and plasma display panel manufacturing method
JPWO2006123392A1 (en) 2005-05-16 2008-12-25 日本たばこ産業株式会社 Deep rooting evaluation method for plants

Also Published As

Publication number Publication date
JPH09171770A (en) 1997-06-30

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