JP2682135B2 - IC package - Google Patents
IC packageInfo
- Publication number
- JP2682135B2 JP2682135B2 JP1114705A JP11470589A JP2682135B2 JP 2682135 B2 JP2682135 B2 JP 2682135B2 JP 1114705 A JP1114705 A JP 1114705A JP 11470589 A JP11470589 A JP 11470589A JP 2682135 B2 JP2682135 B2 JP 2682135B2
- Authority
- JP
- Japan
- Prior art keywords
- chip component
- protrusion
- package
- chip
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、表面実装用ICパッケージ形状に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mounting IC package shape.
従来の技術 電子回路基板の高密度化が進み、表面実装基板の割合
がますます増加している。表面実装基板ではクリーム半
田を用いたリフロー半田付け工程を用いるのが一般的で
ある。高密度化の進んだ基板では両面に実装することも
珍しくない。部品の小型化に伴って、リフロー半田付け
工程における半田付け不良が多発するようになった。た
とえば、ICのリード間が半田によりショートしてしまう
現象（ブリッジ）、チップ部品の片側の電極が浮き上が
り垂直に立ってしまう現象（マンハッタン現象、チップ
立ち）や半田がICのリードに吸い上がりランド上の半田
がなくなってしまう現象（ウィッキング）、半田の微粒
子が半田付け部の周辺に発生し（半田ボール）基板の絶
縁不良を引き起こす現象等が発生している。2. Description of the Related Art The density of electronic circuit boards is increasing, and the ratio of surface mount boards is increasing. It is common to use a reflow soldering process using cream solder for the surface mount board. It is not uncommon to mount on both sides of a highly dense board. With the miniaturization of parts, soldering defects have frequently occurred in the reflow soldering process. For example, a short circuit due to solder between IC leads (bridge), a phenomenon in which one side of the chip component floats and stands vertically (Manhattan phenomenon, chip standing), or solder sucks onto the IC leads and onto the land. There is a phenomenon in which the solder is lost (wicking), fine particles of solder are generated around the soldering portion (solder ball), and the insulation failure of the substrate is caused.
発明が解決しようとする課題 ところで、表面実装用ICを用いたリフロー半田付け工
程において、高密度化を実現するためにICの下にチップ
コンデンサーを実装することが多い。このような高密度
実装基板ではリフロー工程中にICの下部のチップコンデ
ンサーがマンハッタン現象を起こすこという半田付け不
良が多発している。すなわち、チップコンデンサーの片
側の電極が浮き上がり、ICパッケージの下面と接触して
しまうことをいう（第２図）。本発明の目的は、このよ
うなIC下部に実装されたチップ部品のマンハッタン現象
を防止することにある。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention By the way, in a reflow soldering process using a surface mounting IC, a chip capacitor is often mounted under the IC in order to achieve high density. In such a high-density mounting board, soldering failure that the chip capacitor under the IC causes a Manhattan phenomenon during the reflow process frequently occurs. That is, the electrode on one side of the chip capacitor floats up and comes into contact with the lower surface of the IC package (Fig. 2). An object of the present invention is to prevent such a Manhattan phenomenon of a chip component mounted under the IC.
課題を解決するための手段 本発明に係るICパッケージは、表面実装用ICの本体下
部に突起を設け、プリント基板上に既に実装されたチッ
プ部品の上から重ねてプリント基板上に実装する際、前
記突起が前記チップ部品の上部表面積より小さい面積
で、かつ前記チップ部品上面に接触するよう形成したも
のである。Means for Solving the Problems The IC package according to the present invention is provided with a protrusion on the lower part of the main body of the surface mounting IC, and when mounted on the printed circuit board by stacking the chip components already mounted on the printed circuit board, The protrusion is formed so as to have an area smaller than the upper surface area of the chip component and to contact the upper surface of the chip component.
作用 本発明においては、IC下部に実装されたチップ部品の
マンハッタン現象を防止することができる。Action In the present invention, the Manhattan phenomenon of the chip component mounted under the IC can be prevented.
実 施 例 第１図に本発明によるICのパッケージ形状と実装状態
の一例を示す。１はICパッケージの本体であり、その下
部に突起２を設ける。ICの下部とチップ部品３の間には
いくらかの隙間があり、この隙間を埋めるようにIC下部
の突起の突き出し長さを決定する。突起の面積はチップ
部品よりも小さくしておき、溶融半田と突起が接触する
のを防いでいる。突起は必ずしもチップ部品に接触して
いる必要はなく、チップ部品の片側の電極が浮き上がり
かけたときそれを抑止し、両方の電極に正常に半田付け
が可能な範囲とする。４はＪ字形のリードである。Practical Example FIG. 1 shows an example of the package shape and mounting state of the IC according to the present invention. Reference numeral 1 is a main body of an IC package, and a protrusion 2 is provided on the lower portion thereof. There is some gap between the lower part of the IC and the chip component 3, and the protrusion length of the protrusion under the IC is determined so as to fill this gap. The area of the protrusion is made smaller than that of the chip component to prevent contact between the molten solder and the protrusion. The protrusion does not necessarily have to be in contact with the chip component, and when the electrode on one side of the chip component rises, it is suppressed so that it can be normally soldered to both electrodes. 4 is a J-shaped lead.
なお、突起の形状は上記の実施例で示した形状以外の
ものでもよいことは言うまでもない。Needless to say, the shape of the protrusion may be other than the shape shown in the above embodiment.
発明の効果 従来、IC下部に実装したチップ部品のマンハッタン現
象を防止するための方法としてはリフロー方法の選定、
予熱温度や予熱時間などリフロー条件の設定、クリーム
半田や電極の材料選定、厳密な工程管理を必要としてい
たが、それでも発生原因が明確に解明されていないため
完全に防止することはできなかった。Effects of the Invention Conventionally, as a method for preventing the Manhattan phenomenon of chip parts mounted under the IC, selection of a reflow method,
Although it was necessary to set reflow conditions such as preheating temperature and preheating time, to select cream solder and electrode materials, and to strictly control the process, it was not possible to prevent it completely because the cause of the occurrence was not clearly understood.
とろこが、本発明によればIC下部に実装したチップ部
品のマンハッタン現象は物理的に発生の可能性がまった
くなる。このため、いかなるリフロー方法、リフロー条
件、クリーム半田を用いてもまったくマンハッタン現象
は発生しなくなる。According to the present invention, however, the Manhattan phenomenon of the chip component mounted under the IC has no possibility of physically occurring. Therefore, the Manhattan phenomenon does not occur at all even if any reflow method, reflow condition, or cream solder is used.
第１図（ａ）は本発明の一実施例におけるICのパッケー
ジ形状と実装状態を示す側面図、第１図（ｂ）は同底面
図、第２図は従来のICパッケージ形状と実装状態を示す
側面図である。 １……ICパッケージの本体、２……突起、３……チップ
部品、４……Ｊ字形リード。1 (a) is a side view showing the package shape and mounting state of an IC in one embodiment of the present invention, FIG. 1 (b) is a bottom view of the same, and FIG. 2 is a conventional IC package shape and mounting state. It is a side view shown. 1 ... IC package body, 2 ... protrusion, 3 ... chip component, 4 ... J-shaped lead.
フロントページの続き (72)発明者 壁下 朗 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 昭64−72546（ＪＰ，Ａ) 実開 平２−98654（ＪＰ，Ｕ)Front Page Continuation (72) Inventor Akira Moshishita 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-64-72546 (JP, A) JP, U)
Claims (1)
リント基板上に既に実装されたチップ部品の上から重ね
てプリント基板上に実装する際、前記突起が前記チップ
部品の上部表面積より小さい面積で、かつ前記チップ部
品上面に接触するよう形成したことを特徴としたICパッ
ケージ。1. A protrusion is provided on a lower portion of a main body of a surface-mounting IC, and when the chip component already mounted on the printed circuit board is overlaid and mounted on the printed circuit board, the protrusion is more than the upper surface area of the chip component. An IC package having a small area and being formed so as to come into contact with the upper surface of the chip component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1114705A JP2682135B2 (en) | 1989-05-08 | 1989-05-08 | IC package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1114705A JP2682135B2 (en) | 1989-05-08 | 1989-05-08 | IC package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02294055A JPH02294055A (en) | 1990-12-05 |
| JP2682135B2 true JP2682135B2 (en) | 1997-11-26 |
Family
ID=14644558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1114705A Expired - Fee Related JP2682135B2 (en) | 1989-05-08 | 1989-05-08 | IC package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2682135B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08125069A (en) * | 1994-10-24 | 1996-05-17 | Nec Kyushu Ltd | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6472546A (en) * | 1987-09-11 | 1989-03-17 | Kansai Nippon Electric | Semiconductor device |
| JPH0298654U (en) * | 1989-01-26 | 1990-08-06 |
-
1989
- 1989-05-08 JP JP1114705A patent/JP2682135B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02294055A (en) | 1990-12-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |